Re: [PATCH 20/49] perf/x86/intel: Add Alder Lake Hybrid support

From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH 20/49] perf/x86/intel: Add Alder Lake Hybrid support
Date: Tue, 09 Feb 2021 12:24:35 +0800	[thread overview]
Message-ID: <202102091224.blTrzSBS-lkp@intel.com> (raw)
In-Reply-To: <1612797946-18784-21-git-send-email-kan.liang@linux.intel.com>

[-- Attachment #1: Type: text/plain, Size: 34541 bytes --]

Hi,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on tip/perf/core]
[cannot apply to tip/master linus/master tip/x86/core v5.11-rc6 next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/kan-liang-linux-intel-com/Add-Alder-Lake-support-for-perf/20210209-070642
base:   https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 32451614da2a9cf4296f90d3606ac77814fb519d
config: x86_64-randconfig-a013-20210209 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project c9439ca36342fb6013187d0a69aef92736951476)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # https://github.com/0day-ci/linux/commit/b4dd7dba3e07b911b667e9c8052547a7af28298b
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review kan-liang-linux-intel-com/Add-Alder-Lake-support-for-perf/20210209-070642
        git checkout b4dd7dba3e07b911b667e9c8052547a7af28298b
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> arch/x86/events/intel/core.c:6110:7: error: use of undeclared identifier 'INTEL_FAM6_ALDERLAKE_L'
           case INTEL_FAM6_ALDERLAKE_L:
                ^
   1 error generated.

vim +/INTEL_FAM6_ALDERLAKE_L +6110 arch/x86/events/intel/core.c

  5499	
  5500	__init int intel_pmu_init(void)
  5501	{
  5502		struct attribute **extra_skl_attr = &empty_attrs;
  5503		struct attribute **extra_attr = &empty_attrs;
  5504		struct attribute **td_attr    = &empty_attrs;
  5505		struct attribute **mem_attr   = &empty_attrs;
  5506		struct attribute **tsx_attr   = &empty_attrs;
  5507		union cpuid10_edx edx;
  5508		union cpuid10_eax eax;
  5509		union cpuid10_ebx ebx;
  5510		unsigned int fixed_mask;
  5511		bool pmem = false;
  5512		int version, i;
  5513		char *name;
  5514		struct x86_hybrid_pmu *pmu;
  5515	
  5516		if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
  5517			switch (boot_cpu_data.x86) {
  5518			case 0x6:
  5519				return p6_pmu_init();
  5520			case 0xb:
  5521				return knc_pmu_init();
  5522			case 0xf:
  5523				return p4_pmu_init();
  5524			}
  5525			return -ENODEV;
  5526		}
  5527	
  5528		/*
  5529		 * Check whether the Architectural PerfMon supports
  5530		 * Branch Misses Retired hw_event or not.
  5531		 */
  5532		cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
  5533		if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
  5534			return -ENODEV;
  5535	
  5536		version = eax.split.version_id;
  5537		if (version < 2)
  5538			x86_pmu = core_pmu;
  5539		else
  5540			x86_pmu = intel_pmu;
  5541	
  5542		x86_pmu.version			= version;
  5543		x86_pmu.num_counters		= eax.split.num_counters;
  5544		x86_pmu.cntval_bits		= eax.split.bit_width;
  5545		x86_pmu.cntval_mask		= (1ULL << eax.split.bit_width) - 1;
  5546	
  5547		x86_pmu.events_maskl		= ebx.full;
  5548		x86_pmu.events_mask_len		= eax.split.mask_length;
  5549	
  5550		x86_pmu.max_pebs_events		= min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
  5551	
  5552		/*
  5553		 * Quirk: v2 perfmon does not report fixed-purpose events, so
  5554		 * assume@least 3 events, when not running in a hypervisor:
  5555		 */
  5556		if (version > 1 && version < 5) {
  5557			int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
  5558	
  5559			x86_pmu.num_counters_fixed =
  5560				max((int)edx.split.num_counters_fixed, assume);
  5561	
  5562			fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
  5563		} else if (version >= 5)
  5564			x86_pmu.num_counters_fixed = fls(fixed_mask);
  5565	
  5566		if (boot_cpu_has(X86_FEATURE_PDCM)) {
  5567			u64 capabilities;
  5568	
  5569			rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
  5570			x86_pmu.intel_cap.capabilities = capabilities;
  5571		}
  5572	
  5573		if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
  5574			x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
  5575			x86_pmu.lbr_read = intel_pmu_lbr_read_32;
  5576		}
  5577	
  5578		if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
  5579			intel_pmu_arch_lbr_init();
  5580	
  5581		intel_ds_init();
  5582	
  5583		x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
  5584	
  5585		if (version >= 5) {
  5586			x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
  5587			if (x86_pmu.intel_cap.anythread_deprecated)
  5588				pr_cont(" AnyThread deprecated, ");
  5589		}
  5590	
  5591		/*
  5592		 * Install the hw-cache-events table:
  5593		 */
  5594		switch (boot_cpu_data.x86_model) {
  5595		case INTEL_FAM6_CORE_YONAH:
  5596			pr_cont("Core events, ");
  5597			name = "core";
  5598			break;
  5599	
  5600		case INTEL_FAM6_CORE2_MEROM:
  5601			x86_add_quirk(intel_clovertown_quirk);
  5602			fallthrough;
  5603	
  5604		case INTEL_FAM6_CORE2_MEROM_L:
  5605		case INTEL_FAM6_CORE2_PENRYN:
  5606		case INTEL_FAM6_CORE2_DUNNINGTON:
  5607			memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
  5608			       sizeof(hw_cache_event_ids));
  5609	
  5610			intel_pmu_lbr_init_core();
  5611	
  5612			x86_pmu.event_constraints = intel_core2_event_constraints;
  5613			x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
  5614			pr_cont("Core2 events, ");
  5615			name = "core2";
  5616			break;
  5617	
  5618		case INTEL_FAM6_NEHALEM:
  5619		case INTEL_FAM6_NEHALEM_EP:
  5620		case INTEL_FAM6_NEHALEM_EX:
  5621			memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
  5622			       sizeof(hw_cache_event_ids));
  5623			memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
  5624			       sizeof(hw_cache_extra_regs));
  5625	
  5626			intel_pmu_lbr_init_nhm();
  5627	
  5628			x86_pmu.event_constraints = intel_nehalem_event_constraints;
  5629			x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
  5630			x86_pmu.enable_all = intel_pmu_nhm_enable_all;
  5631			x86_pmu.extra_regs = intel_nehalem_extra_regs;
  5632			x86_pmu.limit_period = nhm_limit_period;
  5633	
  5634			mem_attr = nhm_mem_events_attrs;
  5635	
  5636			/* UOPS_ISSUED.STALLED_CYCLES */
  5637			intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
  5638				X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
  5639			/* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
  5640			intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
  5641				X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
  5642	
  5643			intel_pmu_pebs_data_source_nhm();
  5644			x86_add_quirk(intel_nehalem_quirk);
  5645			x86_pmu.pebs_no_tlb = 1;
  5646			extra_attr = nhm_format_attr;
  5647	
  5648			pr_cont("Nehalem events, ");
  5649			name = "nehalem";
  5650			break;
  5651	
  5652		case INTEL_FAM6_ATOM_BONNELL:
  5653		case INTEL_FAM6_ATOM_BONNELL_MID:
  5654		case INTEL_FAM6_ATOM_SALTWELL:
  5655		case INTEL_FAM6_ATOM_SALTWELL_MID:
  5656		case INTEL_FAM6_ATOM_SALTWELL_TABLET:
  5657			memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
  5658			       sizeof(hw_cache_event_ids));
  5659	
  5660			intel_pmu_lbr_init_atom();
  5661	
  5662			x86_pmu.event_constraints = intel_gen_event_constraints;
  5663			x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
  5664			x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
  5665			pr_cont("Atom events, ");
  5666			name = "bonnell";
  5667			break;
  5668	
  5669		case INTEL_FAM6_ATOM_SILVERMONT:
  5670		case INTEL_FAM6_ATOM_SILVERMONT_D:
  5671		case INTEL_FAM6_ATOM_SILVERMONT_MID:
  5672		case INTEL_FAM6_ATOM_AIRMONT:
  5673		case INTEL_FAM6_ATOM_AIRMONT_MID:
  5674			memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
  5675				sizeof(hw_cache_event_ids));
  5676			memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
  5677			       sizeof(hw_cache_extra_regs));
  5678	
  5679			intel_pmu_lbr_init_slm();
  5680	
  5681			x86_pmu.event_constraints = intel_slm_event_constraints;
  5682			x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
  5683			x86_pmu.extra_regs = intel_slm_extra_regs;
  5684			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5685			td_attr = slm_events_attrs;
  5686			extra_attr = slm_format_attr;
  5687			pr_cont("Silvermont events, ");
  5688			name = "silvermont";
  5689			break;
  5690	
  5691		case INTEL_FAM6_ATOM_GOLDMONT:
  5692		case INTEL_FAM6_ATOM_GOLDMONT_D:
  5693			memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
  5694			       sizeof(hw_cache_event_ids));
  5695			memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
  5696			       sizeof(hw_cache_extra_regs));
  5697	
  5698			intel_pmu_lbr_init_skl();
  5699	
  5700			x86_pmu.event_constraints = intel_slm_event_constraints;
  5701			x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
  5702			x86_pmu.extra_regs = intel_glm_extra_regs;
  5703			/*
  5704			 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
  5705			 * for precise cycles.
  5706			 * :pp is identical to :ppp
  5707			 */
  5708			x86_pmu.pebs_aliases = NULL;
  5709			x86_pmu.pebs_prec_dist = true;
  5710			x86_pmu.lbr_pt_coexist = true;
  5711			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5712			td_attr = glm_events_attrs;
  5713			extra_attr = slm_format_attr;
  5714			pr_cont("Goldmont events, ");
  5715			name = "goldmont";
  5716			break;
  5717	
  5718		case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
  5719			memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
  5720			       sizeof(hw_cache_event_ids));
  5721			memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
  5722			       sizeof(hw_cache_extra_regs));
  5723	
  5724			intel_pmu_lbr_init_skl();
  5725	
  5726			x86_pmu.event_constraints = intel_slm_event_constraints;
  5727			x86_pmu.extra_regs = intel_glm_extra_regs;
  5728			/*
  5729			 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
  5730			 * for precise cycles.
  5731			 */
  5732			x86_pmu.pebs_aliases = NULL;
  5733			x86_pmu.pebs_prec_dist = true;
  5734			x86_pmu.lbr_pt_coexist = true;
  5735			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5736			x86_pmu.flags |= PMU_FL_PEBS_ALL;
  5737			x86_pmu.get_event_constraints = glp_get_event_constraints;
  5738			td_attr = glm_events_attrs;
  5739			/* Goldmont Plus has 4-wide pipeline */
  5740			event_attr_td_total_slots_scale_glm.event_str = "4";
  5741			extra_attr = slm_format_attr;
  5742			pr_cont("Goldmont plus events, ");
  5743			name = "goldmont_plus";
  5744			break;
  5745	
  5746		case INTEL_FAM6_ATOM_TREMONT_D:
  5747		case INTEL_FAM6_ATOM_TREMONT:
  5748		case INTEL_FAM6_ATOM_TREMONT_L:
  5749			x86_pmu.late_ack = true;
  5750			memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
  5751			       sizeof(hw_cache_event_ids));
  5752			memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
  5753			       sizeof(hw_cache_extra_regs));
  5754			hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
  5755	
  5756			intel_pmu_lbr_init_skl();
  5757	
  5758			x86_pmu.event_constraints = intel_slm_event_constraints;
  5759			x86_pmu.extra_regs = intel_tnt_extra_regs;
  5760			/*
  5761			 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
  5762			 * for precise cycles.
  5763			 */
  5764			x86_pmu.pebs_aliases = NULL;
  5765			x86_pmu.pebs_prec_dist = true;
  5766			x86_pmu.lbr_pt_coexist = true;
  5767			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5768			x86_pmu.get_event_constraints = tnt_get_event_constraints;
  5769			td_attr = tnt_events_attrs;
  5770			extra_attr = slm_format_attr;
  5771			pr_cont("Tremont events, ");
  5772			name = "Tremont";
  5773			break;
  5774	
  5775		case INTEL_FAM6_WESTMERE:
  5776		case INTEL_FAM6_WESTMERE_EP:
  5777		case INTEL_FAM6_WESTMERE_EX:
  5778			memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
  5779			       sizeof(hw_cache_event_ids));
  5780			memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
  5781			       sizeof(hw_cache_extra_regs));
  5782	
  5783			intel_pmu_lbr_init_nhm();
  5784	
  5785			x86_pmu.event_constraints = intel_westmere_event_constraints;
  5786			x86_pmu.enable_all = intel_pmu_nhm_enable_all;
  5787			x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
  5788			x86_pmu.extra_regs = intel_westmere_extra_regs;
  5789			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5790	
  5791			mem_attr = nhm_mem_events_attrs;
  5792	
  5793			/* UOPS_ISSUED.STALLED_CYCLES */
  5794			intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
  5795				X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
  5796			/* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
  5797			intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
  5798				X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
  5799	
  5800			intel_pmu_pebs_data_source_nhm();
  5801			extra_attr = nhm_format_attr;
  5802			pr_cont("Westmere events, ");
  5803			name = "westmere";
  5804			break;
  5805	
  5806		case INTEL_FAM6_SANDYBRIDGE:
  5807		case INTEL_FAM6_SANDYBRIDGE_X:
  5808			x86_add_quirk(intel_sandybridge_quirk);
  5809			x86_add_quirk(intel_ht_bug);
  5810			memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
  5811			       sizeof(hw_cache_event_ids));
  5812			memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
  5813			       sizeof(hw_cache_extra_regs));
  5814	
  5815			intel_pmu_lbr_init_snb();
  5816	
  5817			x86_pmu.event_constraints = intel_snb_event_constraints;
  5818			x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
  5819			x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
  5820			if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
  5821				x86_pmu.extra_regs = intel_snbep_extra_regs;
  5822			else
  5823				x86_pmu.extra_regs = intel_snb_extra_regs;
  5824	
  5825	
  5826			/* all extra regs are per-cpu when HT is on */
  5827			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5828			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  5829	
  5830			td_attr  = snb_events_attrs;
  5831			mem_attr = snb_mem_events_attrs;
  5832	
  5833			/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
  5834			intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
  5835				X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
  5836			/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
  5837			intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
  5838				X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
  5839	
  5840			extra_attr = nhm_format_attr;
  5841	
  5842			pr_cont("SandyBridge events, ");
  5843			name = "sandybridge";
  5844			break;
  5845	
  5846		case INTEL_FAM6_IVYBRIDGE:
  5847		case INTEL_FAM6_IVYBRIDGE_X:
  5848			x86_add_quirk(intel_ht_bug);
  5849			memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
  5850			       sizeof(hw_cache_event_ids));
  5851			/* dTLB-load-misses on IVB is different than SNB */
  5852			hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
  5853	
  5854			memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
  5855			       sizeof(hw_cache_extra_regs));
  5856	
  5857			intel_pmu_lbr_init_snb();
  5858	
  5859			x86_pmu.event_constraints = intel_ivb_event_constraints;
  5860			x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
  5861			x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
  5862			x86_pmu.pebs_prec_dist = true;
  5863			if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
  5864				x86_pmu.extra_regs = intel_snbep_extra_regs;
  5865			else
  5866				x86_pmu.extra_regs = intel_snb_extra_regs;
  5867			/* all extra regs are per-cpu when HT is on */
  5868			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5869			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  5870	
  5871			td_attr  = snb_events_attrs;
  5872			mem_attr = snb_mem_events_attrs;
  5873	
  5874			/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
  5875			intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
  5876				X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
  5877	
  5878			extra_attr = nhm_format_attr;
  5879	
  5880			pr_cont("IvyBridge events, ");
  5881			name = "ivybridge";
  5882			break;
  5883	
  5884	
  5885		case INTEL_FAM6_HASWELL:
  5886		case INTEL_FAM6_HASWELL_X:
  5887		case INTEL_FAM6_HASWELL_L:
  5888		case INTEL_FAM6_HASWELL_G:
  5889			x86_add_quirk(intel_ht_bug);
  5890			x86_add_quirk(intel_pebs_isolation_quirk);
  5891			x86_pmu.late_ack = true;
  5892			memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
  5893			memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
  5894	
  5895			intel_pmu_lbr_init_hsw();
  5896	
  5897			x86_pmu.event_constraints = intel_hsw_event_constraints;
  5898			x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
  5899			x86_pmu.extra_regs = intel_snbep_extra_regs;
  5900			x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
  5901			x86_pmu.pebs_prec_dist = true;
  5902			/* all extra regs are per-cpu when HT is on */
  5903			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5904			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  5905	
  5906			x86_pmu.hw_config = hsw_hw_config;
  5907			x86_pmu.get_event_constraints = hsw_get_event_constraints;
  5908			x86_pmu.lbr_double_abort = true;
  5909			extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
  5910				hsw_format_attr : nhm_format_attr;
  5911			td_attr  = hsw_events_attrs;
  5912			mem_attr = hsw_mem_events_attrs;
  5913			tsx_attr = hsw_tsx_events_attrs;
  5914			pr_cont("Haswell events, ");
  5915			name = "haswell";
  5916			break;
  5917	
  5918		case INTEL_FAM6_BROADWELL:
  5919		case INTEL_FAM6_BROADWELL_D:
  5920		case INTEL_FAM6_BROADWELL_G:
  5921		case INTEL_FAM6_BROADWELL_X:
  5922			x86_add_quirk(intel_pebs_isolation_quirk);
  5923			x86_pmu.late_ack = true;
  5924			memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
  5925			memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
  5926	
  5927			/* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
  5928			hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
  5929										 BDW_L3_MISS|HSW_SNOOP_DRAM;
  5930			hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
  5931										  HSW_SNOOP_DRAM;
  5932			hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
  5933										     BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
  5934			hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
  5935										      BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
  5936	
  5937			intel_pmu_lbr_init_hsw();
  5938	
  5939			x86_pmu.event_constraints = intel_bdw_event_constraints;
  5940			x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
  5941			x86_pmu.extra_regs = intel_snbep_extra_regs;
  5942			x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
  5943			x86_pmu.pebs_prec_dist = true;
  5944			/* all extra regs are per-cpu when HT is on */
  5945			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5946			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  5947	
  5948			x86_pmu.hw_config = hsw_hw_config;
  5949			x86_pmu.get_event_constraints = hsw_get_event_constraints;
  5950			x86_pmu.limit_period = bdw_limit_period;
  5951			extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
  5952				hsw_format_attr : nhm_format_attr;
  5953			td_attr  = hsw_events_attrs;
  5954			mem_attr = hsw_mem_events_attrs;
  5955			tsx_attr = hsw_tsx_events_attrs;
  5956			pr_cont("Broadwell events, ");
  5957			name = "broadwell";
  5958			break;
  5959	
  5960		case INTEL_FAM6_XEON_PHI_KNL:
  5961		case INTEL_FAM6_XEON_PHI_KNM:
  5962			memcpy(hw_cache_event_ids,
  5963			       slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
  5964			memcpy(hw_cache_extra_regs,
  5965			       knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
  5966			intel_pmu_lbr_init_knl();
  5967	
  5968			x86_pmu.event_constraints = intel_slm_event_constraints;
  5969			x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
  5970			x86_pmu.extra_regs = intel_knl_extra_regs;
  5971	
  5972			/* all extra regs are per-cpu when HT is on */
  5973			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  5974			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  5975			extra_attr = slm_format_attr;
  5976			pr_cont("Knights Landing/Mill events, ");
  5977			name = "knights-landing";
  5978			break;
  5979	
  5980		case INTEL_FAM6_SKYLAKE_X:
  5981			pmem = true;
  5982			fallthrough;
  5983		case INTEL_FAM6_SKYLAKE_L:
  5984		case INTEL_FAM6_SKYLAKE:
  5985		case INTEL_FAM6_KABYLAKE_L:
  5986		case INTEL_FAM6_KABYLAKE:
  5987		case INTEL_FAM6_COMETLAKE_L:
  5988		case INTEL_FAM6_COMETLAKE:
  5989			x86_add_quirk(intel_pebs_isolation_quirk);
  5990			x86_pmu.late_ack = true;
  5991			memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
  5992			memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
  5993			intel_pmu_lbr_init_skl();
  5994	
  5995			/* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
  5996			event_attr_td_recovery_bubbles.event_str_noht =
  5997				"event=0xd,umask=0x1,cmask=1";
  5998			event_attr_td_recovery_bubbles.event_str_ht =
  5999				"event=0xd,umask=0x1,cmask=1,any=1";
  6000	
  6001			x86_pmu.event_constraints = intel_skl_event_constraints;
  6002			x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
  6003			x86_pmu.extra_regs = intel_skl_extra_regs;
  6004			x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
  6005			x86_pmu.pebs_prec_dist = true;
  6006			/* all extra regs are per-cpu when HT is on */
  6007			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  6008			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  6009	
  6010			x86_pmu.hw_config = hsw_hw_config;
  6011			x86_pmu.get_event_constraints = hsw_get_event_constraints;
  6012			extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
  6013				hsw_format_attr : nhm_format_attr;
  6014			extra_skl_attr = skl_format_attr;
  6015			td_attr  = hsw_events_attrs;
  6016			mem_attr = hsw_mem_events_attrs;
  6017			tsx_attr = hsw_tsx_events_attrs;
  6018			intel_pmu_pebs_data_source_skl(pmem);
  6019	
  6020			if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
  6021				x86_pmu.flags |= PMU_FL_TFA;
  6022				x86_pmu.get_event_constraints = tfa_get_event_constraints;
  6023				x86_pmu.enable_all = intel_tfa_pmu_enable_all;
  6024				x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
  6025			}
  6026	
  6027			pr_cont("Skylake events, ");
  6028			name = "skylake";
  6029			break;
  6030	
  6031		case INTEL_FAM6_ICELAKE_X:
  6032		case INTEL_FAM6_ICELAKE_D:
  6033			pmem = true;
  6034			fallthrough;
  6035		case INTEL_FAM6_ICELAKE_L:
  6036		case INTEL_FAM6_ICELAKE:
  6037		case INTEL_FAM6_TIGERLAKE_L:
  6038		case INTEL_FAM6_TIGERLAKE:
  6039		case INTEL_FAM6_ROCKETLAKE:
  6040			x86_pmu.late_ack = true;
  6041			memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
  6042			memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
  6043			hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
  6044			intel_pmu_lbr_init_skl();
  6045	
  6046			x86_pmu.event_constraints = intel_icl_event_constraints;
  6047			x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
  6048			x86_pmu.extra_regs = intel_icl_extra_regs;
  6049			x86_pmu.pebs_aliases = NULL;
  6050			x86_pmu.pebs_prec_dist = true;
  6051			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  6052			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  6053	
  6054			x86_pmu.hw_config = hsw_hw_config;
  6055			x86_pmu.get_event_constraints = icl_get_event_constraints;
  6056			extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
  6057				hsw_format_attr : nhm_format_attr;
  6058			extra_skl_attr = skl_format_attr;
  6059			mem_attr = icl_events_attrs;
  6060			td_attr = icl_td_events_attrs;
  6061			tsx_attr = icl_tsx_events_attrs;
  6062			x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
  6063			x86_pmu.lbr_pt_coexist = true;
  6064			intel_pmu_pebs_data_source_skl(pmem);
  6065			x86_pmu.num_topdown_events = 4;
  6066			x86_pmu.update_topdown_event = icl_update_topdown_event;
  6067			x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
  6068			pr_cont("Icelake events, ");
  6069			name = "icelake";
  6070			break;
  6071	
  6072		case INTEL_FAM6_SAPPHIRERAPIDS_X:
  6073			pmem = true;
  6074			x86_pmu.late_ack = true;
  6075			memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
  6076			memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
  6077	
  6078			x86_pmu.event_constraints = intel_spr_event_constraints;
  6079			x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
  6080			x86_pmu.extra_regs = intel_spr_extra_regs;
  6081			x86_pmu.limit_period = spr_limit_period;
  6082			x86_pmu.pebs_aliases = NULL;
  6083			x86_pmu.pebs_prec_dist = true;
  6084			x86_pmu.pebs_block = true;
  6085			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  6086			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  6087			x86_pmu.flags |= PMU_FL_PEBS_ALL;
  6088			x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
  6089			x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
  6090	
  6091			x86_pmu.hw_config = hsw_hw_config;
  6092			x86_pmu.get_event_constraints = spr_get_event_constraints;
  6093			extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
  6094				hsw_format_attr : nhm_format_attr;
  6095			extra_skl_attr = skl_format_attr;
  6096			mem_attr = spr_events_attrs;
  6097			td_attr = spr_td_events_attrs;
  6098			tsx_attr = spr_tsx_events_attrs;
  6099			x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
  6100			x86_pmu.lbr_pt_coexist = true;
  6101			intel_pmu_pebs_data_source_skl(pmem);
  6102			x86_pmu.num_topdown_events = 8;
  6103			x86_pmu.update_topdown_event = icl_update_topdown_event;
  6104			x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
  6105			pr_cont("Sapphire Rapids events, ");
  6106			name = "sapphire_rapids";
  6107			break;
  6108	
  6109		case INTEL_FAM6_ALDERLAKE:
> 6110		case INTEL_FAM6_ALDERLAKE_L:
  6111			/*
  6112			 * Alder Lake has 2 types of CPU, core and atom.
  6113			 *
  6114			 * Initialize the common PerfMon capabilities here.
  6115			 */
  6116			x86_pmu.late_ack = true;
  6117			x86_pmu.pebs_aliases = NULL;
  6118			x86_pmu.pebs_prec_dist = true;
  6119			x86_pmu.flags |= PMU_FL_HAS_RSP_1;
  6120			x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
  6121			x86_pmu.flags |= PMU_FL_PEBS_ALL;
  6122			x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
  6123			x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
  6124			x86_pmu.lbr_pt_coexist = true;
  6125			intel_pmu_pebs_data_source_skl(false);
  6126			x86_pmu.num_topdown_events = 8;
  6127			x86_pmu.update_topdown_event = adl_update_topdown_event;
  6128			x86_pmu.set_topdown_event_period = adl_set_topdown_event_period;
  6129	
  6130			x86_pmu.filter_match = intel_pmu_filter_match;
  6131			x86_pmu.get_event_constraints = adl_get_event_constraints;
  6132			x86_pmu.hw_config = adl_hw_config;
  6133			x86_pmu.limit_period = spr_limit_period;
  6134			/*
  6135			 * The rtm_abort_event is used to check whether to enable GPRs
  6136			 * for the RTM abort event. Atom doesn't have the RTM abort
  6137			 * event. There is no harmful to set it in the common
  6138			 * x86_pmu.rtm_abort_event.
  6139			 */
  6140			x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
  6141	
  6142			td_attr = adl_hybrid_events_attrs;
  6143			mem_attr = adl_hybrid_mem_attrs;
  6144			tsx_attr = adl_hybrid_tsx_attrs;
  6145			extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
  6146				adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
  6147	
  6148			/* Initialize big core specific PerfMon capabilities.*/
  6149			set_bit(X86_HYBRID_PMU_CORE_IDX, &x86_pmu.hybrid_pmu_bitmap);
  6150			pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
  6151			pmu->name = "cpu_core";
  6152			pmu->cpu_type = X86_HYBRID_CORE_CPU_TYPE;
  6153			pmu->num_counters = x86_pmu.num_counters + 2;
  6154			pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1;
  6155			pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
  6156			pmu->unconstrained = (struct event_constraint)
  6157						__EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
  6158								   0, pmu->num_counters, 0, 0);
  6159			pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
  6160			pmu->intel_cap.perf_metrics = 1;
  6161			pmu->intel_cap.pebs_output_pt_available = 0;
  6162	
  6163			memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
  6164			memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
  6165			pmu->event_constraints = intel_spr_event_constraints;
  6166			pmu->pebs_constraints = intel_spr_pebs_event_constraints;
  6167			pmu->extra_regs = intel_spr_extra_regs;
  6168	
  6169			/* Initialize Atom core specific PerfMon capabilities.*/
  6170			set_bit(X86_HYBRID_PMU_ATOM_IDX, &x86_pmu.hybrid_pmu_bitmap);
  6171			pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
  6172			pmu->name = "cpu_atom";
  6173			pmu->cpu_type = X86_HYBRID_ATOM_CPU_TYPE;
  6174			pmu->num_counters = x86_pmu.num_counters;
  6175			pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
  6176			pmu->max_pebs_events = x86_pmu.max_pebs_events;
  6177			pmu->unconstrained = (struct event_constraint)
  6178						__EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
  6179								   0, pmu->num_counters, 0, 0);
  6180			pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
  6181			pmu->intel_cap.perf_metrics = 0;
  6182			pmu->intel_cap.pebs_output_pt_available = 1;
  6183	
  6184			memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
  6185			memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
  6186			pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
  6187			pmu->event_constraints = intel_slm_event_constraints;
  6188			pmu->pebs_constraints = intel_grt_pebs_event_constraints;
  6189			pmu->extra_regs = intel_grt_extra_regs;
  6190			pr_cont("Alderlake Hybrid events, ");
  6191			name = "alderlake_hybrid";
  6192			break;
  6193	
  6194		default:
  6195			switch (x86_pmu.version) {
  6196			case 1:
  6197				x86_pmu.event_constraints = intel_v1_event_constraints;
  6198				pr_cont("generic architected perfmon v1, ");
  6199				name = "generic_arch_v1";
  6200				break;
  6201			default:
  6202				/*
  6203				 * default constraints for v2 and up
  6204				 */
  6205				x86_pmu.event_constraints = intel_gen_event_constraints;
  6206				pr_cont("generic architected perfmon, ");
  6207				name = "generic_arch_v2+";
  6208				break;
  6209			}
  6210		}
  6211	
  6212		snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
  6213	
  6214		if (!IS_X86_HYBRID) {
  6215			group_events_td.attrs  = td_attr;
  6216			group_events_mem.attrs = mem_attr;
  6217			group_events_tsx.attrs = tsx_attr;
  6218			group_format_extra.attrs = extra_attr;
  6219			group_format_extra_skl.attrs = extra_skl_attr;
  6220	
  6221			x86_pmu.attr_update = attr_update;
  6222		} else {
  6223			hybrid_group_events_td.attrs  = td_attr;
  6224			hybrid_group_events_mem.attrs = mem_attr;
  6225			hybrid_group_events_tsx.attrs = tsx_attr;
  6226			hybrid_group_format_extra.attrs = extra_attr;
  6227	
  6228			x86_pmu.attr_update = hybrid_attr_update;
  6229		}
  6230	
  6231		intel_pmu_check_num_counters(&x86_pmu.num_counters,
  6232					     &x86_pmu.num_counters_fixed,
  6233					     &x86_pmu.intel_ctrl,
  6234					     (u64)fixed_mask);
  6235	
  6236		/* AnyThread may be deprecated on arch perfmon v5 or later */
  6237		if (x86_pmu.intel_cap.anythread_deprecated)
  6238			x86_pmu.format_attrs = intel_arch_formats_attr;
  6239	
  6240		intel_pmu_check_event_constraints(x86_pmu.event_constraints,
  6241						  x86_pmu.num_counters,
  6242						  x86_pmu.num_counters_fixed,
  6243						  x86_pmu.intel_ctrl);
  6244		/*
  6245		 * Access LBR MSR may cause #GP under certain circumstances.
  6246		 * E.g. KVM doesn't support LBR MSR
  6247		 * Check all LBT MSR here.
  6248		 * Disable LBR access if any LBR MSRs can not be accessed.
  6249		 */
  6250		if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
  6251			x86_pmu.lbr_nr = 0;
  6252		for (i = 0; i < x86_pmu.lbr_nr; i++) {
  6253			if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
  6254			      check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
  6255				x86_pmu.lbr_nr = 0;
  6256		}
  6257	
  6258		if (x86_pmu.lbr_nr)
  6259			pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
  6260	
  6261		intel_pmu_check_extra_regs(x86_pmu.extra_regs);
  6262	
  6263		/* Support full width counters using alternative MSR range */
  6264		if (x86_pmu.intel_cap.full_width_write) {
  6265			x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
  6266			x86_pmu.perfctr = MSR_IA32_PMC0;
  6267			pr_cont("full-width counters, ");
  6268		}
  6269	
  6270		if (!IS_X86_HYBRID && x86_pmu.intel_cap.perf_metrics)
  6271			x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
  6272	
  6273		return 0;
  6274	}
  6275	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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