* [PATCH v2 0/4] arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS
@ 2021-02-09 12:47 Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config Dmitry Baryshkov
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Dmitry Baryshkov @ 2021-02-09 12:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Doug Anderson; +Cc: linux-arm-msm
GENI SPI controller shows several issues if it manages the CS on its own
(see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to
use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO.
Changes since v1:
- Split sm8250's spi pin config into mux/config parts, split away CS
handling from main SPI pinctrl nodes.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config
2021-02-09 12:47 [PATCH v2 0/4] arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS Dmitry Baryshkov
@ 2021-02-09 12:47 ` Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: further split of " Dmitry Baryshkov
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Dmitry Baryshkov @ 2021-02-09 12:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Doug Anderson; +Cc: linux-arm-msm
As discussed on linux-arm-msm list, start splitting sm8250 pinctrl
settings into generic and board-specific parts. The first part to
receive such treatment is the spi, so split spi pinconf to the board
device tree.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +
arch/arm64/boot/dts/qcom/sm8250.dtsi | 300 +++++------------------
2 files changed, 65 insertions(+), 240 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 2f0528d01299..787da8ccba54 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -815,6 +815,11 @@ &pm8150_rtc {
status = "okay";
};
+&qup_spi0_default {
+ drive-strength = <6>;
+ bias-disable;
+};
+
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..51d103671759 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2984,303 +2984,123 @@ config {
};
qup_spi0_default: qup-spi0-default {
- mux {
- pins = "gpio28", "gpio29",
- "gpio30", "gpio31";
- function = "qup0";
- };
-
- config {
- pins = "gpio28", "gpio29",
- "gpio30", "gpio31";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio28", "gpio29",
+ "gpio30", "gpio31";
+ function = "qup0";
};
qup_spi1_default: qup-spi1-default {
- mux {
- pins = "gpio4", "gpio5",
- "gpio6", "gpio7";
- function = "qup1";
- };
-
- config {
- pins = "gpio4", "gpio5",
- "gpio6", "gpio7";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio4", "gpio5",
+ "gpio6", "gpio7";
+ function = "qup1";
};
qup_spi2_default: qup-spi2-default {
- mux {
- pins = "gpio115", "gpio116",
- "gpio117", "gpio118";
- function = "qup2";
- };
-
- config {
- pins = "gpio115", "gpio116",
- "gpio117", "gpio118";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio115", "gpio116",
+ "gpio117", "gpio118";
+ function = "qup2";
};
qup_spi3_default: qup-spi3-default {
- mux {
- pins = "gpio119", "gpio120",
- "gpio121", "gpio122";
- function = "qup3";
- };
-
- config {
- pins = "gpio119", "gpio120",
- "gpio121", "gpio122";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio119", "gpio120",
+ "gpio121", "gpio122";
+ function = "qup3";
};
qup_spi4_default: qup-spi4-default {
- mux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "qup4";
- };
-
- config {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "qup4";
};
qup_spi5_default: qup-spi5-default {
- mux {
- pins = "gpio12", "gpio13",
- "gpio14", "gpio15";
- function = "qup5";
- };
-
- config {
- pins = "gpio12", "gpio13",
- "gpio14", "gpio15";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio12", "gpio13",
+ "gpio14", "gpio15";
+ function = "qup5";
};
qup_spi6_default: qup-spi6-default {
- mux {
- pins = "gpio16", "gpio17",
- "gpio18", "gpio19";
- function = "qup6";
- };
-
- config {
- pins = "gpio16", "gpio17",
- "gpio18", "gpio19";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio16", "gpio17",
+ "gpio18", "gpio19";
+ function = "qup6";
};
qup_spi7_default: qup-spi7-default {
- mux {
- pins = "gpio20", "gpio21",
- "gpio22", "gpio23";
- function = "qup7";
- };
-
- config {
- pins = "gpio20", "gpio21",
- "gpio22", "gpio23";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio20", "gpio21",
+ "gpio22", "gpio23";
+ function = "qup7";
};
qup_spi8_default: qup-spi8-default {
- mux {
- pins = "gpio24", "gpio25",
- "gpio26", "gpio27";
- function = "qup8";
- };
-
- config {
- pins = "gpio24", "gpio25",
- "gpio26", "gpio27";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio24", "gpio25",
+ "gpio26", "gpio27";
+ function = "qup8";
};
qup_spi9_default: qup-spi9-default {
- mux {
- pins = "gpio125", "gpio126",
- "gpio127", "gpio128";
- function = "qup9";
- };
-
- config {
- pins = "gpio125", "gpio126",
- "gpio127", "gpio128";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio125", "gpio126",
+ "gpio127", "gpio128";
+ function = "qup9";
};
qup_spi10_default: qup-spi10-default {
- mux {
- pins = "gpio129", "gpio130",
- "gpio131", "gpio132";
- function = "qup10";
- };
-
- config {
- pins = "gpio129", "gpio130",
- "gpio131", "gpio132";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio129", "gpio130",
+ "gpio131", "gpio132";
+ function = "qup10";
};
qup_spi11_default: qup-spi11-default {
- mux {
- pins = "gpio60", "gpio61",
- "gpio62", "gpio63";
- function = "qup11";
- };
-
- config {
- pins = "gpio60", "gpio61",
- "gpio62", "gpio63";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio60", "gpio61",
+ "gpio62", "gpio63";
+ function = "qup11";
};
qup_spi12_default: qup-spi12-default {
- mux {
- pins = "gpio32", "gpio33",
- "gpio34", "gpio35";
- function = "qup12";
- };
-
- config {
- pins = "gpio32", "gpio33",
- "gpio34", "gpio35";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio32", "gpio33",
+ "gpio34", "gpio35";
+ function = "qup12";
};
qup_spi13_default: qup-spi13-default {
- mux {
- pins = "gpio36", "gpio37",
- "gpio38", "gpio39";
- function = "qup13";
- };
-
- config {
- pins = "gpio36", "gpio37",
- "gpio38", "gpio39";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio36", "gpio37",
+ "gpio38", "gpio39";
+ function = "qup13";
};
qup_spi14_default: qup-spi14-default {
- mux {
- pins = "gpio40", "gpio41",
- "gpio42", "gpio43";
- function = "qup14";
- };
-
- config {
- pins = "gpio40", "gpio41",
- "gpio42", "gpio43";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio40", "gpio41",
+ "gpio42", "gpio43";
+ function = "qup14";
};
qup_spi15_default: qup-spi15-default {
- mux {
- pins = "gpio44", "gpio45",
- "gpio46", "gpio47";
- function = "qup15";
- };
-
- config {
- pins = "gpio44", "gpio45",
- "gpio46", "gpio47";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "qup15";
};
qup_spi16_default: qup-spi16-default {
- mux {
- pins = "gpio48", "gpio49",
- "gpio50", "gpio51";
- function = "qup16";
- };
-
- config {
- pins = "gpio48", "gpio49",
- "gpio50", "gpio51";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio48", "gpio49",
+ "gpio50", "gpio51";
+ function = "qup16";
};
qup_spi17_default: qup-spi17-default {
- mux {
- pins = "gpio52", "gpio53",
- "gpio54", "gpio55";
- function = "qup17";
- };
-
- config {
- pins = "gpio52", "gpio53",
- "gpio54", "gpio55";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio52", "gpio53",
+ "gpio54", "gpio55";
+ function = "qup17";
};
qup_spi18_default: qup-spi18-default {
- mux {
- pins = "gpio56", "gpio57",
- "gpio58", "gpio59";
- function = "qup18";
- };
-
- config {
- pins = "gpio56", "gpio57",
- "gpio58", "gpio59";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio56", "gpio57",
+ "gpio58", "gpio59";
+ function = "qup18";
};
qup_spi19_default: qup-spi19-default {
- mux {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- function = "qup19";
- };
-
- config {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- drive-strength = <6>;
- bias-disable;
- };
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "qup19";
};
qup_uart2_default: qup-uart2-default {
--
2.30.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] arm64: dts: qcom: sm8250: further split of spi pinctrl config
2021-02-09 12:47 [PATCH v2 0/4] arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config Dmitry Baryshkov
@ 2021-02-09 12:47 ` Dmitry Baryshkov
2021-02-09 17:56 ` Bjorn Andersson
2021-02-09 12:47 ` [PATCH v2 3/4] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS Dmitry Baryshkov
3 siblings, 1 reply; 6+ messages in thread
From: Dmitry Baryshkov @ 2021-02-09 12:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Doug Anderson; +Cc: linux-arm-msm
Split "default" device tree nodes into common "data-clk" nodes and "cs"
nodes which might differ from board to board depending on how the slave
chips are wired.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 200 ++++++++++++++++-------
2 files changed, 147 insertions(+), 61 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 787da8ccba54..dd0ec0676258 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -815,7 +815,12 @@ &pm8150_rtc {
status = "okay";
};
-&qup_spi0_default {
+&qup_spi0_cs {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&qup_spi0_data_clk {
drive-strength = <6>;
bias-disable;
};
@@ -957,6 +962,7 @@ codec {
/* CAN */
&spi0 {
status = "okay";
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
can@0 {
compatible = "microchip,mcp2518fd";
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 51d103671759..e43e1367ceb7 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -549,7 +549,6 @@ spi14: spi@880000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi14_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -577,7 +576,6 @@ spi15: spi@884000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi15_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -605,7 +603,6 @@ spi16: spi@888000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi16_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -633,7 +630,6 @@ spi17: spi@88c000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi17_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -674,7 +670,6 @@ spi18: spi@890000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi18_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -715,7 +710,6 @@ spi19: spi@894000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi19_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -756,7 +750,6 @@ spi0: spi@980000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -784,7 +777,6 @@ spi1: spi@984000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -812,7 +804,6 @@ spi2: spi@988000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -853,7 +844,6 @@ spi3: spi@98c000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -881,7 +871,6 @@ spi4: spi@990000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -909,7 +898,6 @@ spi5: spi@994000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -937,7 +925,6 @@ spi6: spi@998000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -978,7 +965,6 @@ spi7: spi@99c000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1019,7 +1005,6 @@ spi8: spi@a80000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1047,7 +1032,6 @@ spi9: spi@a84000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1075,7 +1059,6 @@ spi10: spi@a88000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1103,7 +1086,6 @@ spi11: spi@a8c000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1131,7 +1113,6 @@ spi12: spi@a90000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1172,7 +1153,6 @@ spi13: spi@a94000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -2983,123 +2963,223 @@ config {
};
};
- qup_spi0_default: qup-spi0-default {
+ qup_spi0_cs: qup-spi0-cs {
+ pins = "gpio31";
+ function = "qup0";
+ };
+
+ qup_spi1_cs: qup-spi1-cs {
+ pins = "gpio7";
+ function = "qup1";
+ };
+
+ qup_spi2_cs: qup-spi2-cs {
+ pins = "gpio118";
+ function = "qup2";
+ };
+
+ qup_spi3_cs: qup-spi3-cs {
+ pins = "gpio122";
+ function = "qup3";
+ };
+
+ qup_spi4_cs: qup-spi4-cs {
+ pins = "gpio11";
+ function = "qup4";
+ };
+
+ qup_spi5_cs: qup-spi5-cs {
+ pins = "gpio15";
+ function = "qup5";
+ };
+
+ qup_spi6_cs: qup-spi6-cs {
+ pins = "gpio19";
+ function = "qup6";
+ };
+
+ qup_spi7_cs: qup-spi7-cs {
+ pins = "gpio23";
+ function = "qup7";
+ };
+
+ qup_spi8_cs: qup-spi8-cs {
+ pins = "gpio27";
+ function = "qup8";
+ };
+
+ qup_spi9_cs: qup-spi9-cs {
+ pins = "gpio128";
+ function = "qup9";
+ };
+
+ qup_spi10_cs: qup-spi10-cs {
+ pins = "gpio132";
+ function = "qup10";
+ };
+
+ qup_spi11_cs: qup-spi11-cs {
+ pins = "gpio63";
+ function = "qup11";
+ };
+
+ qup_spi12_cs: qup-spi12-cs {
+ pins = "gpio35";
+ function = "qup12";
+ };
+
+ qup_spi13_cs: qup-spi13-cs {
+ pins = "gpio39";
+ function = "qup13";
+ };
+
+ qup_spi14_cs: qup-spi14-cs {
+ pins = "gpio43";
+ function = "qup14";
+ };
+
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio47";
+ function = "qup15";
+ };
+
+ qup_spi16_cs: qup-spi16-cs {
+ pins = "gpio51";
+ function = "qup16";
+ };
+
+ qup_spi17_cs: qup-spi17-cs {
+ pins = "gpio55";
+ function = "qup17";
+ };
+
+ qup_spi18_cs: qup-spi18-cs {
+ pins = "gpio59";
+ function = "qup18";
+ };
+
+ qup_spi19_cs: qup-spi19-cs {
+ pins = "gpio3";
+ function = "qup19";
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio28", "gpio29",
- "gpio30", "gpio31";
+ "gpio30";
function = "qup0";
};
- qup_spi1_default: qup-spi1-default {
+ qup_spi1_data_clk: qup-spi1-data-clk {
pins = "gpio4", "gpio5",
- "gpio6", "gpio7";
+ "gpio6";
function = "qup1";
};
- qup_spi2_default: qup-spi2-default {
+ qup_spi2_data_clk: qup-spi2-data-clk {
pins = "gpio115", "gpio116",
- "gpio117", "gpio118";
+ "gpio117";
function = "qup2";
};
- qup_spi3_default: qup-spi3-default {
+ qup_spi3_data_clk: qup-spi3-data-clk {
pins = "gpio119", "gpio120",
- "gpio121", "gpio122";
+ "gpio121";
function = "qup3";
};
- qup_spi4_default: qup-spi4-default {
+ qup_spi4_data_clk: qup-spi4-data-clk {
pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
+ "gpio10";
function = "qup4";
};
- qup_spi5_default: qup-spi5-default {
+ qup_spi5_data_clk: qup-spi5-data-clk {
pins = "gpio12", "gpio13",
- "gpio14", "gpio15";
+ "gpio14";
function = "qup5";
};
- qup_spi6_default: qup-spi6-default {
+ qup_spi6_data_clk: qup-spi6-data-clk {
pins = "gpio16", "gpio17",
- "gpio18", "gpio19";
+ "gpio18";
function = "qup6";
};
- qup_spi7_default: qup-spi7-default {
+ qup_spi7_data_clk: qup-spi7-data-clk {
pins = "gpio20", "gpio21",
- "gpio22", "gpio23";
+ "gpio22";
function = "qup7";
};
- qup_spi8_default: qup-spi8-default {
+ qup_spi8_data_clk: qup-spi8-data-clk {
pins = "gpio24", "gpio25",
- "gpio26", "gpio27";
+ "gpio26";
function = "qup8";
};
- qup_spi9_default: qup-spi9-default {
+ qup_spi9_data_clk: qup-spi9-data-clk {
pins = "gpio125", "gpio126",
- "gpio127", "gpio128";
+ "gpio127";
function = "qup9";
};
- qup_spi10_default: qup-spi10-default {
+ qup_spi10_data_clk: qup-spi10-data-clk {
pins = "gpio129", "gpio130",
- "gpio131", "gpio132";
+ "gpio131";
function = "qup10";
};
- qup_spi11_default: qup-spi11-default {
+ qup_spi11_data_clk: qup-spi11-data-clk {
pins = "gpio60", "gpio61",
- "gpio62", "gpio63";
+ "gpio62";
function = "qup11";
};
- qup_spi12_default: qup-spi12-default {
+ qup_spi12_data_clk: qup-spi12-data-clk {
pins = "gpio32", "gpio33",
- "gpio34", "gpio35";
+ "gpio34";
function = "qup12";
};
- qup_spi13_default: qup-spi13-default {
+ qup_spi13_data_clk: qup-spi13-data-clk {
pins = "gpio36", "gpio37",
- "gpio38", "gpio39";
+ "gpio38";
function = "qup13";
};
- qup_spi14_default: qup-spi14-default {
+ qup_spi14_data_clk: qup-spi14-data-clk {
pins = "gpio40", "gpio41",
- "gpio42", "gpio43";
+ "gpio42";
function = "qup14";
};
- qup_spi15_default: qup-spi15-default {
+ qup_spi15_data_clk: qup-spi15-data-clk {
pins = "gpio44", "gpio45",
- "gpio46", "gpio47";
+ "gpio46";
function = "qup15";
};
- qup_spi16_default: qup-spi16-default {
+ qup_spi16_data_clk: qup-spi16-data-clk {
pins = "gpio48", "gpio49",
- "gpio50", "gpio51";
+ "gpio50";
function = "qup16";
};
- qup_spi17_default: qup-spi17-default {
+ qup_spi17_data_clk: qup-spi17-data-clk {
pins = "gpio52", "gpio53",
- "gpio54", "gpio55";
+ "gpio54";
function = "qup17";
};
- qup_spi18_default: qup-spi18-default {
+ qup_spi18_data_clk: qup-spi18-data-clk {
pins = "gpio56", "gpio57",
- "gpio58", "gpio59";
+ "gpio58";
function = "qup18";
};
- qup_spi19_default: qup-spi19-default {
+ qup_spi19_data_clk: qup-spi19-data-clk {
pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
+ "gpio2";
function = "qup19";
};
--
2.30.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS
2021-02-09 12:47 [PATCH v2 0/4] arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: further split of " Dmitry Baryshkov
@ 2021-02-09 12:47 ` Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS Dmitry Baryshkov
3 siblings, 0 replies; 6+ messages in thread
From: Dmitry Baryshkov @ 2021-02-09 12:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Doug Anderson; +Cc: linux-arm-msm
GENI SPI controller shows several issues if it manages the CS on its own
(see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to
use GPIO for CS")) for the details. Provide pinctrl entries for SPI
controllers using the same CS pin but in GPIO mode.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 100 +++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e43e1367ceb7..0044911f7790 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3063,6 +3063,106 @@ qup_spi19_cs: qup-spi19-cs {
function = "qup19";
};
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio {
+ pins = "gpio31";
+ function = "gpio";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio {
+ pins = "gpio118";
+ function = "gpio";
+ };
+
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio {
+ pins = "gpio122";
+ function = "gpio";
+ };
+
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio {
+ pins = "gpio15";
+ function = "gpio";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio {
+ pins = "gpio23";
+ function = "gpio";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio {
+ pins = "gpio128";
+ function = "gpio";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio {
+ pins = "gpio132";
+ function = "gpio";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio {
+ pins = "gpio39";
+ function = "gpio";
+ };
+
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ qup_spi16_cs_gpio: qup-spi16-cs-gpio {
+ pins = "gpio51";
+ function = "gpio";
+ };
+
+ qup_spi17_cs_gpio: qup-spi17-cs-gpio {
+ pins = "gpio55";
+ function = "gpio";
+ };
+
+ qup_spi18_cs_gpio: qup-spi18-cs-gpio {
+ pins = "gpio59";
+ function = "gpio";
+ };
+
+ qup_spi19_cs_gpio: qup-spi19-cs-gpio {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio28", "gpio29",
"gpio30";
--
2.30.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS
2021-02-09 12:47 [PATCH v2 0/4] arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS Dmitry Baryshkov
` (2 preceding siblings ...)
2021-02-09 12:47 ` [PATCH v2 3/4] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS Dmitry Baryshkov
@ 2021-02-09 12:47 ` Dmitry Baryshkov
3 siblings, 0 replies; 6+ messages in thread
From: Dmitry Baryshkov @ 2021-02-09 12:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Doug Anderson; +Cc: linux-arm-msm
GENI SPI controller shows several issues if it manages the CS on its own
(see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to
use GPIO for CS")) for the details. Configure SPI0 CS pin as a GPIO.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index dd0ec0676258..4888ac47cc1d 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -815,7 +815,7 @@ &pm8150_rtc {
status = "okay";
};
-&qup_spi0_cs {
+&qup_spi0_cs_gpio {
drive-strength = <6>;
bias-disable;
};
@@ -962,7 +962,8 @@ codec {
/* CAN */
&spi0 {
status = "okay";
- pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>;
+ cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
can@0 {
compatible = "microchip,mcp2518fd";
--
2.30.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: qcom: sm8250: further split of spi pinctrl config
2021-02-09 12:47 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: further split of " Dmitry Baryshkov
@ 2021-02-09 17:56 ` Bjorn Andersson
0 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2021-02-09 17:56 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: Andy Gross, Doug Anderson, linux-arm-msm
On Tue 09 Feb 06:47 CST 2021, Dmitry Baryshkov wrote:
[..]
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 51d103671759..e43e1367ceb7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -549,7 +549,6 @@ spi14: spi@880000 {
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
> pinctrl-names = "default";
> - pinctrl-0 = <&qup_spi14_default>;
I think you should either drop the pinctrl-names as well, or you should
make this <&qup_spi14_default>, <&qup_spi14_cs>;
> interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
[..]
> - qup_spi0_default: qup-spi0-default {
> + qup_spi0_cs: qup-spi0-cs {
> + pins = "gpio31";
> + function = "qup0";
> + };
> +
> + qup_spi1_cs: qup-spi1-cs {
> + pins = "gpio7";
> + function = "qup1";
> + };
> +
> + qup_spi2_cs: qup-spi2-cs {
> + pins = "gpio118";
> + function = "qup2";
> + };
> +
> + qup_spi3_cs: qup-spi3-cs {
> + pins = "gpio122";
> + function = "qup3";
> + };
> +
> + qup_spi4_cs: qup-spi4-cs {
> + pins = "gpio11";
> + function = "qup4";
> + };
> +
> + qup_spi5_cs: qup-spi5-cs {
> + pins = "gpio15";
> + function = "qup5";
> + };
> +
> + qup_spi6_cs: qup-spi6-cs {
> + pins = "gpio19";
> + function = "qup6";
> + };
> +
> + qup_spi7_cs: qup-spi7-cs {
> + pins = "gpio23";
> + function = "qup7";
> + };
> +
> + qup_spi8_cs: qup-spi8-cs {
> + pins = "gpio27";
> + function = "qup8";
> + };
> +
> + qup_spi9_cs: qup-spi9-cs {
> + pins = "gpio128";
> + function = "qup9";
> + };
> +
> + qup_spi10_cs: qup-spi10-cs {
> + pins = "gpio132";
> + function = "qup10";
> + };
> +
> + qup_spi11_cs: qup-spi11-cs {
> + pins = "gpio63";
> + function = "qup11";
> + };
> +
> + qup_spi12_cs: qup-spi12-cs {
> + pins = "gpio35";
> + function = "qup12";
> + };
> +
> + qup_spi13_cs: qup-spi13-cs {
> + pins = "gpio39";
> + function = "qup13";
> + };
> +
> + qup_spi14_cs: qup-spi14-cs {
> + pins = "gpio43";
> + function = "qup14";
> + };
> +
> + qup_spi15_cs: qup-spi15-cs {
> + pins = "gpio47";
> + function = "qup15";
> + };
> +
> + qup_spi16_cs: qup-spi16-cs {
> + pins = "gpio51";
> + function = "qup16";
> + };
> +
> + qup_spi17_cs: qup-spi17-cs {
> + pins = "gpio55";
> + function = "qup17";
> + };
> +
> + qup_spi18_cs: qup-spi18-cs {
> + pins = "gpio59";
> + function = "qup18";
> + };
> +
> + qup_spi19_cs: qup-spi19-cs {
> + pins = "gpio3";
> + function = "qup19";
> + };
If you intermix these with qup-spiX-data-clk you'll maintain the
alphabetical sort order.
> +
> + qup_spi0_data_clk: qup-spi0-data-clk {
> pins = "gpio28", "gpio29",
> - "gpio30", "gpio31";
> + "gpio30";
> function = "qup0";
> };
Apart from that I think the series looks good.
Regards,
Bjorn
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-02-09 18:09 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-09 12:47 [PATCH v2 0/4] arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: further split of " Dmitry Baryshkov
2021-02-09 17:56 ` Bjorn Andersson
2021-02-09 12:47 ` [PATCH v2 3/4] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS Dmitry Baryshkov
2021-02-09 12:47 ` [PATCH v2 4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS Dmitry Baryshkov
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