* [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling @ 2021-02-10 10:22 Chris Wilson 2021-02-10 10:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address Chris Wilson ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Chris Wilson @ 2021-02-10 10:22 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson Periodically check, for example when idling and upon closing user contexts, whether or not some client has written into unallocated PTE in their ppGTT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 31 +------------- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++ drivers/gpu/drm/i915/gt/intel_gtt.c | 42 +++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + drivers/gpu/drm/i915/i915_scheduler.c | 33 +-------------- drivers/gpu/drm/i915/i915_utils.c | 29 +++++++++++++ drivers/gpu/drm/i915/i915_utils.h | 3 ++ 8 files changed, 98 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index df949320f2b5..b0c349a46e6a 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1737,7 +1737,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, return err; } -static int check_scratch_page(struct i915_gem_context *ctx, u32 *out) +static int check_ctx_scratch(struct i915_gem_context *ctx, u32 *out) { struct i915_address_space *vm; struct page *page; @@ -1770,6 +1770,17 @@ static int check_scratch_page(struct i915_gem_context *ctx, u32 *out) return err; } +static void reset_ctx_scratch(struct i915_gem_context *ctx, u32 value) +{ + struct i915_address_space *vm = ctx_vm(ctx); + struct page *page = __px_page(vm->scratch[0]); + u32 *vaddr; + + vaddr = kmap(page); + memset32(vaddr, value, PAGE_SIZE / sizeof(value)); + kunmap(page); +} + static int igt_vm_isolation(void *arg) { struct drm_i915_private *i915 = arg; @@ -1816,11 +1827,11 @@ static int igt_vm_isolation(void *arg) goto out_file; /* Read the initial state of the scratch page */ - err = check_scratch_page(ctx_a, &expected); + err = check_ctx_scratch(ctx_a, &expected); if (err) goto out_file; - err = check_scratch_page(ctx_b, &expected); + err = check_ctx_scratch(ctx_b, &expected); if (err) goto out_file; @@ -1876,6 +1887,8 @@ static int igt_vm_isolation(void *arg) count, num_engines); out_file: + /* As we deliberately write into scratch, cover up our tracks */ + reset_ctx_scratch(ctx_a, expected); if (igt_live_test_end(&t)) err = -EIO; fput(file); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 577ebd4a324f..8443794df3ee 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1265,35 +1265,6 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine) } } -static void hexdump(struct drm_printer *m, const void *buf, size_t len) -{ - const size_t rowsize = 8 * sizeof(u32); - const void *prev = NULL; - bool skip = false; - size_t pos; - - for (pos = 0; pos < len; pos += rowsize) { - char line[128]; - - if (prev && !memcmp(prev, buf + pos, rowsize)) { - if (!skip) { - drm_printf(m, "*\n"); - skip = true; - } - continue; - } - - WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, - rowsize, sizeof(u32), - line, sizeof(line), - false) >= sizeof(line)); - drm_printf(m, "[%04zx] %s\n", pos, line); - - prev = buf + pos; - skip = false; - } -} - static void intel_engine_print_registers(struct intel_engine_cs *engine, struct drm_printer *m) { @@ -1450,7 +1421,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, } drm_printf(m, "HWSP:\n"); - hexdump(m, engine->status_page.addr, PAGE_SIZE); + i915_hexdump(m, engine->status_page.addr, PAGE_SIZE); drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 0bd303d2823e..38375a006a99 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -11,6 +11,7 @@ #include "intel_context.h" #include "intel_engine_pm.h" #include "intel_gt.h" +#include "intel_gtt.h" #include "intel_gt_clock_utils.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -100,6 +101,9 @@ static int __gt_park(struct intel_wakeref *wf) runtime_end(gt); intel_gt_park_requests(gt); + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) + check_scratch_page(gt->vm); + i915_vma_parked(gt); i915_pmu_gt_parked(i915); intel_rps_park(>->rps); diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index d34770ae4c9a..5ac9eb4a3a92 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -158,10 +158,49 @@ static void poison_scratch_page(struct drm_i915_gem_object *scratch) vaddr = kmap(page); memset(vaddr, val, PAGE_SIZE); + set_page_dirty(page); /* keep the poisoned contents */ kunmap(page); } } +void check_scratch_page(const struct i915_address_space *vm) +{ + struct drm_i915_gem_object *scratch; + struct sgt_iter sgt; + struct page *page; + void *vaddr; + u8 val; + + scratch = vm->scratch[0]; + if (!scratch || !i915_gem_object_has_struct_page(scratch)) + return; + + val = 0; + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) + val = POISON_FREE; + + for_each_sgt_page(page, sgt, scratch->mm.pages) { + vaddr = kmap(page); + drm_clflush_virt_range(vaddr, PAGE_SIZE); + if (memchr_inv(vaddr, val, PAGE_SIZE)) { + struct drm_printer p = drm_err_printer(__func__); + + drm_err(&vm->i915->drm, + "%s scratch page overwitten!\n", + i915_is_ggtt(vm) ? "Global" : "Per-process"); + i915_hexdump(&p, vaddr, PAGE_SIZE); + vaddr = NULL; + } + kunmap(page); + if (!vaddr) + break; + } + + /* Restore the poison, so fresh errors will be detected */ + if (!vaddr) + poison_scratch_page(scratch); +} + int setup_scratch_page(struct i915_address_space *vm) { unsigned long size; @@ -229,6 +268,9 @@ void free_scratch(struct i915_address_space *vm) { int i; + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) + check_scratch_page(vm); + for (i = 0; i <= vm->top; i++) i915_gem_object_put(vm->scratch[i]); } diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 24b5808df16d..a5b312c6485a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -519,6 +519,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); } while (0) int setup_scratch_page(struct i915_address_space *vm); +void check_scratch_page(const struct i915_address_space *vm); void free_scratch(struct i915_address_space *vm); struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index a8fb787278e6..7241f85c9967 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -1095,35 +1095,6 @@ void i915_request_show_with_schedule(struct drm_printer *m, rcu_read_unlock(); } -static void hexdump(struct drm_printer *m, const void *buf, size_t len) -{ - const size_t rowsize = 8 * sizeof(u32); - const void *prev = NULL; - bool skip = false; - size_t pos; - - for (pos = 0; pos < len; pos += rowsize) { - char line[128]; - - if (prev && !memcmp(prev, buf + pos, rowsize)) { - if (!skip) { - drm_printf(m, "*\n"); - skip = true; - } - continue; - } - - WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, - rowsize, sizeof(u32), - line, sizeof(line), - false) >= sizeof(line)); - drm_printf(m, "[%04zx] %s\n", pos, line); - - prev = buf + pos; - skip = false; - } -} - static void print_request_ring(struct drm_printer *m, const struct i915_request *rq) { @@ -1153,7 +1124,7 @@ print_request_ring(struct drm_printer *m, const struct i915_request *rq) } memcpy(ring + len, vaddr + head, size - len); - hexdump(m, ring, size); + i915_hexdump(m, ring, size); kfree(ring); } } @@ -1195,7 +1166,7 @@ void i915_sched_show(struct drm_printer *m, if (rq->context->lrc_reg_state) { drm_printf(m, "Logical Ring Context:\n"); - hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); + i915_hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); } } diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c index 894de60833ec..432ad0926586 100644 --- a/drivers/gpu/drm/i915/i915_utils.c +++ b/drivers/gpu/drm/i915/i915_utils.c @@ -49,6 +49,35 @@ __i915_printk(struct drm_i915_private *dev_priv, const char *level, } } +void i915_hexdump(struct drm_printer *m, const void *buf, size_t len) +{ + const size_t rowsize = 8 * sizeof(u32); + const void *prev = NULL; + bool skip = false; + size_t pos; + + for (pos = 0; pos < len; pos += rowsize) { + char line[128]; + + if (prev && !memcmp(prev, buf + pos, rowsize)) { + if (!skip) { + drm_printf(m, "*\n"); + skip = true; + } + continue; + } + + WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, + rowsize, sizeof(u32), + line, sizeof(line), + false) >= sizeof(line)); + drm_printf(m, "[%04zx] %s\n", pos, line); + + prev = buf + pos; + skip = false; + } +} + void add_taint_for_CI(struct drm_i915_private *i915, unsigned int taint) { __i915_printk(i915, KERN_NOTICE, "CI tainted:%#x by %pS\n", diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h index 4618fe8aacb5..c82461d6ae71 100644 --- a/drivers/gpu/drm/i915/i915_utils.h +++ b/drivers/gpu/drm/i915/i915_utils.h @@ -32,6 +32,7 @@ #include <linux/workqueue.h> struct drm_i915_private; +struct drm_printer; struct timer_list; #define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs" @@ -82,6 +83,8 @@ bool i915_error_injected(void); __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \ fmt, ##__VA_ARGS__) +void i915_hexdump(struct drm_printer *m, const void *buf, size_t len); + #if defined(GCC_VERSION) && GCC_VERSION >= 70000 #define add_overflows_t(T, A, B) \ __builtin_add_overflow_p((A), (B), (T)0) -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address 2021-02-10 10:22 [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Chris Wilson @ 2021-02-10 10:22 ` Chris Wilson 2021-02-10 10:50 ` Mika Kuoppala 2021-02-10 10:49 ` [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Mika Kuoppala ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Chris Wilson @ 2021-02-10 10:22 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson The surface_state_base is an offset into the batch, so we need to pass the correct batch address for STATE_BASE_ADDRESS. Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> --- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index e403eb046a43..de575fdb033f 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch, /* general */ *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; /* surface */ - *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY; + *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY; /* dynamic */ *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; /* indirect */ -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address 2021-02-10 10:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address Chris Wilson @ 2021-02-10 10:50 ` Mika Kuoppala 2021-02-10 12:21 ` Chris Wilson 0 siblings, 1 reply; 9+ messages in thread From: Mika Kuoppala @ 2021-02-10 10:50 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: Chris Wilson Chris Wilson <chris@chris-wilson.co.uk> writes: > The surface_state_base is an offset into the batch, so we need to pass > the correct batch address for STATE_BASE_ADDRESS. > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> > Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > index e403eb046a43..de575fdb033f 100644 > --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > @@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch, > /* general */ > *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; > /* surface */ > - *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY; > + *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY; > /* dynamic */ > *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; > /* indirect */ > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address 2021-02-10 10:50 ` Mika Kuoppala @ 2021-02-10 12:21 ` Chris Wilson 0 siblings, 0 replies; 9+ messages in thread From: Chris Wilson @ 2021-02-10 12:21 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx Quoting Mika Kuoppala (2021-02-10 10:50:18) > Chris Wilson <chris@chris-wilson.co.uk> writes: > > > The surface_state_base is an offset into the batch, so we need to pass > > the correct batch address for STATE_BASE_ADDRESS. > > > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> > > Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> > > Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Compared against https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7571/index.html I think we've found our suspect. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling 2021-02-10 10:22 [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Chris Wilson 2021-02-10 10:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address Chris Wilson @ 2021-02-10 10:49 ` Mika Kuoppala 2021-02-10 11:09 ` Chris Wilson 2021-02-10 11:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] " Patchwork 2021-02-10 12:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 3 siblings, 1 reply; 9+ messages in thread From: Mika Kuoppala @ 2021-02-10 10:49 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: Chris Wilson Chris Wilson <chris@chris-wilson.co.uk> writes: > Periodically check, for example when idling and upon closing user > contexts, whether or not some client has written into unallocated PTE in > their ppGTT. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > .../drm/i915/gem/selftests/i915_gem_context.c | 19 +++++++-- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 31 +------------- > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++ > drivers/gpu/drm/i915/gt/intel_gtt.c | 42 +++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + > drivers/gpu/drm/i915/i915_scheduler.c | 33 +-------------- > drivers/gpu/drm/i915/i915_utils.c | 29 +++++++++++++ > drivers/gpu/drm/i915/i915_utils.h | 3 ++ > 8 files changed, 98 insertions(+), 64 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > index df949320f2b5..b0c349a46e6a 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > @@ -1737,7 +1737,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, > return err; > } > > -static int check_scratch_page(struct i915_gem_context *ctx, u32 *out) > +static int check_ctx_scratch(struct i915_gem_context *ctx, u32 *out) > { > struct i915_address_space *vm; > struct page *page; > @@ -1770,6 +1770,17 @@ static int check_scratch_page(struct i915_gem_context *ctx, u32 *out) > return err; > } > > +static void reset_ctx_scratch(struct i915_gem_context *ctx, u32 value) > +{ > + struct i915_address_space *vm = ctx_vm(ctx); > + struct page *page = __px_page(vm->scratch[0]); > + u32 *vaddr; > + > + vaddr = kmap(page); > + memset32(vaddr, value, PAGE_SIZE / sizeof(value)); > + kunmap(page); > +} > + > static int igt_vm_isolation(void *arg) > { > struct drm_i915_private *i915 = arg; > @@ -1816,11 +1827,11 @@ static int igt_vm_isolation(void *arg) > goto out_file; > > /* Read the initial state of the scratch page */ > - err = check_scratch_page(ctx_a, &expected); > + err = check_ctx_scratch(ctx_a, &expected); > if (err) > goto out_file; > > - err = check_scratch_page(ctx_b, &expected); > + err = check_ctx_scratch(ctx_b, &expected); > if (err) > goto out_file; > > @@ -1876,6 +1887,8 @@ static int igt_vm_isolation(void *arg) > count, num_engines); > > out_file: > + /* As we deliberately write into scratch, cover up our tracks */ > + reset_ctx_scratch(ctx_a, expected); > if (igt_live_test_end(&t)) > err = -EIO; > fput(file); > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 577ebd4a324f..8443794df3ee 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1265,35 +1265,6 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine) > } > } > > -static void hexdump(struct drm_printer *m, const void *buf, size_t len) > -{ > - const size_t rowsize = 8 * sizeof(u32); > - const void *prev = NULL; > - bool skip = false; > - size_t pos; > - > - for (pos = 0; pos < len; pos += rowsize) { > - char line[128]; > - > - if (prev && !memcmp(prev, buf + pos, rowsize)) { > - if (!skip) { > - drm_printf(m, "*\n"); > - skip = true; > - } > - continue; > - } > - > - WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, > - rowsize, sizeof(u32), > - line, sizeof(line), > - false) >= sizeof(line)); > - drm_printf(m, "[%04zx] %s\n", pos, line); > - > - prev = buf + pos; > - skip = false; > - } > -} > - > static void intel_engine_print_registers(struct intel_engine_cs *engine, > struct drm_printer *m) > { > @@ -1450,7 +1421,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, > } > > drm_printf(m, "HWSP:\n"); > - hexdump(m, engine->status_page.addr, PAGE_SIZE); > + i915_hexdump(m, engine->status_page.addr, PAGE_SIZE); > > drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine))); > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > index 0bd303d2823e..38375a006a99 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c > @@ -11,6 +11,7 @@ > #include "intel_context.h" > #include "intel_engine_pm.h" > #include "intel_gt.h" > +#include "intel_gtt.h" > #include "intel_gt_clock_utils.h" > #include "intel_gt_pm.h" > #include "intel_gt_requests.h" > @@ -100,6 +101,9 @@ static int __gt_park(struct intel_wakeref *wf) > runtime_end(gt); > intel_gt_park_requests(gt); > > + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) > + check_scratch_page(gt->vm); > + > i915_vma_parked(gt); > i915_pmu_gt_parked(i915); > intel_rps_park(>->rps); > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c > index d34770ae4c9a..5ac9eb4a3a92 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > @@ -158,10 +158,49 @@ static void poison_scratch_page(struct drm_i915_gem_object *scratch) > > vaddr = kmap(page); > memset(vaddr, val, PAGE_SIZE); > + set_page_dirty(page); /* keep the poisoned contents */ Should we use locked version in here? -Mika > kunmap(page); > } > } > > +void check_scratch_page(const struct i915_address_space *vm) > +{ > + struct drm_i915_gem_object *scratch; > + struct sgt_iter sgt; > + struct page *page; > + void *vaddr; > + u8 val; > + > + scratch = vm->scratch[0]; > + if (!scratch || !i915_gem_object_has_struct_page(scratch)) > + return; > + > + val = 0; > + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) > + val = POISON_FREE; > + > + for_each_sgt_page(page, sgt, scratch->mm.pages) { > + vaddr = kmap(page); > + drm_clflush_virt_range(vaddr, PAGE_SIZE); > + if (memchr_inv(vaddr, val, PAGE_SIZE)) { > + struct drm_printer p = drm_err_printer(__func__); > + > + drm_err(&vm->i915->drm, > + "%s scratch page overwitten!\n", > + i915_is_ggtt(vm) ? "Global" : "Per-process"); > + i915_hexdump(&p, vaddr, PAGE_SIZE); > + vaddr = NULL; > + } > + kunmap(page); > + if (!vaddr) > + break; > + } > + > + /* Restore the poison, so fresh errors will be detected */ > + if (!vaddr) > + poison_scratch_page(scratch); > +} > + > int setup_scratch_page(struct i915_address_space *vm) > { > unsigned long size; > @@ -229,6 +268,9 @@ void free_scratch(struct i915_address_space *vm) > { > int i; > > + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) > + check_scratch_page(vm); > + > for (i = 0; i <= vm->top; i++) > i915_gem_object_put(vm->scratch[i]); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index 24b5808df16d..a5b312c6485a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -519,6 +519,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); > } while (0) > > int setup_scratch_page(struct i915_address_space *vm); > +void check_scratch_page(const struct i915_address_space *vm); > void free_scratch(struct i915_address_space *vm); > > struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); > diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c > index a8fb787278e6..7241f85c9967 100644 > --- a/drivers/gpu/drm/i915/i915_scheduler.c > +++ b/drivers/gpu/drm/i915/i915_scheduler.c > @@ -1095,35 +1095,6 @@ void i915_request_show_with_schedule(struct drm_printer *m, > rcu_read_unlock(); > } > > -static void hexdump(struct drm_printer *m, const void *buf, size_t len) > -{ > - const size_t rowsize = 8 * sizeof(u32); > - const void *prev = NULL; > - bool skip = false; > - size_t pos; > - > - for (pos = 0; pos < len; pos += rowsize) { > - char line[128]; > - > - if (prev && !memcmp(prev, buf + pos, rowsize)) { > - if (!skip) { > - drm_printf(m, "*\n"); > - skip = true; > - } > - continue; > - } > - > - WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, > - rowsize, sizeof(u32), > - line, sizeof(line), > - false) >= sizeof(line)); > - drm_printf(m, "[%04zx] %s\n", pos, line); > - > - prev = buf + pos; > - skip = false; > - } > -} > - > static void > print_request_ring(struct drm_printer *m, const struct i915_request *rq) > { > @@ -1153,7 +1124,7 @@ print_request_ring(struct drm_printer *m, const struct i915_request *rq) > } > memcpy(ring + len, vaddr + head, size - len); > > - hexdump(m, ring, size); > + i915_hexdump(m, ring, size); > kfree(ring); > } > } > @@ -1195,7 +1166,7 @@ void i915_sched_show(struct drm_printer *m, > > if (rq->context->lrc_reg_state) { > drm_printf(m, "Logical Ring Context:\n"); > - hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); > + i915_hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE); > } > } > > diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c > index 894de60833ec..432ad0926586 100644 > --- a/drivers/gpu/drm/i915/i915_utils.c > +++ b/drivers/gpu/drm/i915/i915_utils.c > @@ -49,6 +49,35 @@ __i915_printk(struct drm_i915_private *dev_priv, const char *level, > } > } > > +void i915_hexdump(struct drm_printer *m, const void *buf, size_t len) > +{ > + const size_t rowsize = 8 * sizeof(u32); > + const void *prev = NULL; > + bool skip = false; > + size_t pos; > + > + for (pos = 0; pos < len; pos += rowsize) { > + char line[128]; > + > + if (prev && !memcmp(prev, buf + pos, rowsize)) { > + if (!skip) { > + drm_printf(m, "*\n"); > + skip = true; > + } > + continue; > + } > + > + WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos, > + rowsize, sizeof(u32), > + line, sizeof(line), > + false) >= sizeof(line)); > + drm_printf(m, "[%04zx] %s\n", pos, line); > + > + prev = buf + pos; > + skip = false; > + } > +} > + > void add_taint_for_CI(struct drm_i915_private *i915, unsigned int taint) > { > __i915_printk(i915, KERN_NOTICE, "CI tainted:%#x by %pS\n", > diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h > index 4618fe8aacb5..c82461d6ae71 100644 > --- a/drivers/gpu/drm/i915/i915_utils.h > +++ b/drivers/gpu/drm/i915/i915_utils.h > @@ -32,6 +32,7 @@ > #include <linux/workqueue.h> > > struct drm_i915_private; > +struct drm_printer; > struct timer_list; > > #define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs" > @@ -82,6 +83,8 @@ bool i915_error_injected(void); > __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \ > fmt, ##__VA_ARGS__) > > +void i915_hexdump(struct drm_printer *m, const void *buf, size_t len); > + > #if defined(GCC_VERSION) && GCC_VERSION >= 70000 > #define add_overflows_t(T, A, B) \ > __builtin_add_overflow_p((A), (B), (T)0) > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling 2021-02-10 10:49 ` [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Mika Kuoppala @ 2021-02-10 11:09 ` Chris Wilson 2021-02-10 11:51 ` Mika Kuoppala 0 siblings, 1 reply; 9+ messages in thread From: Chris Wilson @ 2021-02-10 11:09 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx Quoting Mika Kuoppala (2021-02-10 10:49:55) > Chris Wilson <chris@chris-wilson.co.uk> writes: > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c > > index d34770ae4c9a..5ac9eb4a3a92 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > > @@ -158,10 +158,49 @@ static void poison_scratch_page(struct drm_i915_gem_object *scratch) > > > > vaddr = kmap(page); > > memset(vaddr, val, PAGE_SIZE); > > + set_page_dirty(page); /* keep the poisoned contents */ > > Should we use locked version in here? We don't hold the page-lock here, so no. If this is not an anonymous page, something is very wrong :p -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling 2021-02-10 11:09 ` Chris Wilson @ 2021-02-10 11:51 ` Mika Kuoppala 0 siblings, 0 replies; 9+ messages in thread From: Mika Kuoppala @ 2021-02-10 11:51 UTC (permalink / raw) To: Chris Wilson, intel-gfx Chris Wilson <chris@chris-wilson.co.uk> writes: > Quoting Mika Kuoppala (2021-02-10 10:49:55) >> Chris Wilson <chris@chris-wilson.co.uk> writes: >> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c >> > index d34770ae4c9a..5ac9eb4a3a92 100644 >> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c >> > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c >> > @@ -158,10 +158,49 @@ static void poison_scratch_page(struct drm_i915_gem_object *scratch) >> > >> > vaddr = kmap(page); >> > memset(vaddr, val, PAGE_SIZE); >> > + set_page_dirty(page); /* keep the poisoned contents */ >> >> Should we use locked version in here? > > We don't hold the page-lock here, so no. If this is not an anonymous > page, something is very wrong :p Cleared confusion in irc. We dont hold the lock and set_page_dirty dont take it. But this is anonymous page and we are sole user during poisoning. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Check for scratch page scribbling 2021-02-10 10:22 [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Chris Wilson 2021-02-10 10:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address Chris Wilson 2021-02-10 10:49 ` [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Mika Kuoppala @ 2021-02-10 11:47 ` Patchwork 2021-02-10 12:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 3 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-02-10 11:47 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915: Check for scratch page scribbling URL : https://patchwork.freedesktop.org/series/86940/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Check for scratch page scribbling 2021-02-10 10:22 [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Chris Wilson ` (2 preceding siblings ...) 2021-02-10 11:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] " Patchwork @ 2021-02-10 12:16 ` Patchwork 3 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-02-10 12:16 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 8850 bytes --] == Series Details == Series: series starting with [1/2] drm/i915: Check for scratch page scribbling URL : https://patchwork.freedesktop.org/series/86940/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9757 -> Patchwork_19651 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_19651 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19651, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_19651: ### IGT changes ### #### Possible regressions #### * igt@core_hotunplug@unbind-rebind: - fi-skl-guc: [PASS][1] -> [DMESG-WARN][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html * igt@i915_selftest@live@gem: - fi-kbl-guc: [PASS][3] -> [DMESG-WARN][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-kbl-guc/igt@i915_selftest@live@gem.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-kbl-guc/igt@i915_selftest@live@gem.html * igt@i915_selftest@live@gem_contexts: - fi-byt-j1900: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-byt-j1900/igt@i915_selftest@live@gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-byt-j1900/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@mman: - fi-kbl-r: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-kbl-r/igt@i915_selftest@live@mman.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-kbl-r/igt@i915_selftest@live@mman.html - fi-skl-6700k2: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-skl-6700k2/igt@i915_selftest@live@mman.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-skl-6700k2/igt@i915_selftest@live@mman.html - fi-ivb-3770: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-ivb-3770/igt@i915_selftest@live@mman.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-ivb-3770/igt@i915_selftest@live@mman.html - fi-kbl-x1275: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-kbl-x1275/igt@i915_selftest@live@mman.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-kbl-x1275/igt@i915_selftest@live@mman.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-hsw-4770: [PASS][15] -> [DMESG-WARN][16] +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_exec_suspend@basic-s0: - {fi-hsw-gt1}: [PASS][17] -> [DMESG-WARN][18] +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-hsw-gt1/igt@gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-hsw-gt1/igt@gem_exec_suspend@basic-s0.html Known issues ------------ Here are the changes found in Patchwork_19651 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@query-info: - fi-tgl-y: NOTRUN -> [SKIP][19] ([fdo#109315] / [i915#2575]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-tgl-y/igt@amdgpu/amd_basic@query-info.html * igt@fbdev@write: - fi-tgl-y: [PASS][20] -> [DMESG-WARN][21] ([i915#402]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-tgl-y/igt@fbdev@write.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-tgl-y/igt@fbdev@write.html * igt@i915_selftest@live@gem_contexts: - fi-ivb-3770: [PASS][22] -> [INCOMPLETE][23] ([i915#2782]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-ivb-3770/igt@i915_selftest@live@gem_contexts.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-ivb-3770/igt@i915_selftest@live@gem_contexts.html - fi-hsw-4770: [PASS][24] -> [INCOMPLETE][25] ([i915#2782]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-hsw-4770/igt@i915_selftest@live@gem_contexts.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-hsw-4770/igt@i915_selftest@live@gem_contexts.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [PASS][26] -> [DMESG-WARN][27] ([i915#2203] / [i915#2868]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html * igt@runner@aborted: - fi-hsw-4770: NOTRUN -> [FAIL][28] ([i915#1436] / [i915#2505]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-hsw-4770/igt@runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][29] ([i915#2426]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-ivb-3770/igt@runner@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][30] ([i915#2426] / [i915#2505]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-byt-j1900/igt@runner@aborted.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][31] ([i915#2411] / [i915#402]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html * igt@gem_flink_basic@bad-flink: - fi-tgl-y: [DMESG-WARN][33] ([i915#402]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-tgl-y/igt@gem_flink_basic@bad-flink.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-tgl-y/igt@gem_flink_basic@bad-flink.html * igt@i915_selftest@live@client: - fi-glk-dsi: [DMESG-FAIL][35] ([i915#3047]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9757/fi-glk-dsi/igt@i915_selftest@live@client.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/fi-glk-dsi/igt@i915_selftest@live@client.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868 [i915#3047]: https://gitlab.freedesktop.org/drm/intel/issues/3047 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 40) ------------------------------ Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes ------------- * Linux: CI_DRM_9757 -> Patchwork_19651 CI-20190529: 20190529 CI_DRM_9757: fbcc37cd0591950c13a233a364342d873539d12f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6000: 72fcf1364781a401374dcff43b00db8e722cd47b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19651: ae0a84f417288c2813502c3d838cc59c649c5fd9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ae0a84f41728 drm/i915/gt: Correct surface base address 212e4368a0c0 drm/i915: Check for scratch page scribbling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19651/index.html [-- Attachment #1.2: Type: text/html, Size: 10278 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-02-10 12:21 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-02-10 10:22 [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Chris Wilson 2021-02-10 10:22 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Correct surface base address Chris Wilson 2021-02-10 10:50 ` Mika Kuoppala 2021-02-10 12:21 ` Chris Wilson 2021-02-10 10:49 ` [Intel-gfx] [PATCH 1/2] drm/i915: Check for scratch page scribbling Mika Kuoppala 2021-02-10 11:09 ` Chris Wilson 2021-02-10 11:51 ` Mika Kuoppala 2021-02-10 11:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] " Patchwork 2021-02-10 12:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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