[PATCH v6 0/4] Add SPMI support for Mediatek MT6873/8192 SoC IC

[PATCH v6 0/4] Add SPMI support for Mediatek MT6873/8192 SoC IC

[Hsin-Hsiung Wang]

This series adds support for new SoC MT6873/8192 to the spmi driver.
This series is based on Weiyi's patches[1].

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1608642587-15634-7-git-send-email-weiyi.lu@mediatek.com/

changes since v5:
- fix the yaml error.
- refine the spmi-mtk-pmif driver for better code quality.
- fix the build error about MT8192.dtsi

Hsin-Hsiung Wang (4):
  dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'
  dt-bindings: spmi: document binding for the Mediatek SPMI controller
  spmi: mediatek: Add support for MT6873/8192
  arm64: dts: mt8192: add spmi node

 .../bindings/spmi/mtk,spmi-mtk-pmif.yaml      |  74 +++
 .../devicetree/bindings/spmi/spmi.yaml        |   2 +-
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |  17 +
 drivers/spmi/Kconfig                          |   9 +
 drivers/spmi/Makefile                         |   2 +
 drivers/spmi/spmi-mtk-pmif.c                  | 488 ++++++++++++++++++
 6 files changed, 591 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
 create mode 100644 drivers/spmi/spmi-mtk-pmif.c

-- 
2.18.0

[PATCH v6 0/4] Add SPMI support for Mediatek MT6873/8192 SoC IC

[Hsin-Hsiung Wang]

This series adds support for new SoC MT6873/8192 to the spmi driver.
This series is based on Weiyi's patches[1].

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1608642587-15634-7-git-send-email-weiyi.lu@mediatek.com/

changes since v5:
- fix the yaml error.
- refine the spmi-mtk-pmif driver for better code quality.
- fix the build error about MT8192.dtsi

Hsin-Hsiung Wang (4):
  dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'
  dt-bindings: spmi: document binding for the Mediatek SPMI controller
  spmi: mediatek: Add support for MT6873/8192
  arm64: dts: mt8192: add spmi node

 .../bindings/spmi/mtk,spmi-mtk-pmif.yaml      |  74 +++
 .../devicetree/bindings/spmi/spmi.yaml        |   2 +-
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |  17 +
 drivers/spmi/Kconfig                          |   9 +
 drivers/spmi/Makefile                         |   2 +
 drivers/spmi/spmi-mtk-pmif.c                  | 488 ++++++++++++++++++
 6 files changed, 591 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
 create mode 100644 drivers/spmi/spmi-mtk-pmif.c

-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 0/4] Add SPMI support for Mediatek MT6873/8192 SoC IC

[Hsin-Hsiung Wang]

This series adds support for new SoC MT6873/8192 to the spmi driver.
This series is based on Weiyi's patches[1].

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1608642587-15634-7-git-send-email-weiyi.lu@mediatek.com/

changes since v5:
- fix the yaml error.
- refine the spmi-mtk-pmif driver for better code quality.
- fix the build error about MT8192.dtsi

Hsin-Hsiung Wang (4):
  dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'
  dt-bindings: spmi: document binding for the Mediatek SPMI controller
  spmi: mediatek: Add support for MT6873/8192
  arm64: dts: mt8192: add spmi node

 .../bindings/spmi/mtk,spmi-mtk-pmif.yaml      |  74 +++
 .../devicetree/bindings/spmi/spmi.yaml        |   2 +-
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |  17 +
 drivers/spmi/Kconfig                          |   9 +
 drivers/spmi/Makefile                         |   2 +
 drivers/spmi/spmi-mtk-pmif.c                  | 488 ++++++++++++++++++
 6 files changed, 591 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
 create mode 100644 drivers/spmi/spmi-mtk-pmif.c

-- 
2.18.0
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[PATCH v6 1/4] dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'

[Hsin-Hsiung Wang]

The constraint of 'maxItem: 1' might be larger than 1, so we modify it
to 'minItem: 1'.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- update the constraint of minItem to 1.
---
 Documentation/devicetree/bindings/spmi/spmi.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml
index 173940930719..12dbf6567d16 100644
--- a/Documentation/devicetree/bindings/spmi/spmi.yaml
+++ b/Documentation/devicetree/bindings/spmi/spmi.yaml
@@ -25,7 +25,7 @@ properties:
     pattern: "^spmi@.*"
 
   reg:
-    maxItems: 1
+    minItems: 1
 
   "#address-cells":
     const: 2
-- 
2.18.0

[PATCH v6 1/4] dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'

[Hsin-Hsiung Wang]

The constraint of 'maxItem: 1' might be larger than 1, so we modify it
to 'minItem: 1'.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- update the constraint of minItem to 1.
---
 Documentation/devicetree/bindings/spmi/spmi.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml
index 173940930719..12dbf6567d16 100644
--- a/Documentation/devicetree/bindings/spmi/spmi.yaml
+++ b/Documentation/devicetree/bindings/spmi/spmi.yaml
@@ -25,7 +25,7 @@ properties:
     pattern: "^spmi@.*"
 
   reg:
-    maxItems: 1
+    minItems: 1
 
   "#address-cells":
     const: 2
-- 
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 1/4] dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'

[Hsin-Hsiung Wang]

The constraint of 'maxItem: 1' might be larger than 1, so we modify it
to 'minItem: 1'.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- update the constraint of minItem to 1.
---
 Documentation/devicetree/bindings/spmi/spmi.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml
index 173940930719..12dbf6567d16 100644
--- a/Documentation/devicetree/bindings/spmi/spmi.yaml
+++ b/Documentation/devicetree/bindings/spmi/spmi.yaml
@@ -25,7 +25,7 @@ properties:
     pattern: "^spmi@.*"
 
   reg:
-    maxItems: 1
+    minItems: 1
 
   "#address-cells":
     const: 2
-- 
2.18.0
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[PATCH v6 2/4] dt-bindings: spmi: document binding for the Mediatek SPMI controller

[Hsin-Hsiung Wang]

This adds documentation for the SPMI controller found on Mediatek SoCs.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
changes since v5: no changes
---
 .../bindings/spmi/mtk,spmi-mtk-pmif.yaml      | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml

diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
new file mode 100644
index 000000000000..a43b0302d503
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek SPMI Controller Device Tree Bindings
+
+maintainers:
+  - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
+
+description: |+
+  On MediaTek SoCs the PMIC is connected via SPMI and the controller allows
+  for multiple SoCs to control a single SPMI master.
+
+allOf:
+  - $ref: "spmi.yaml"
+
+properties:
+  compatible:
+    const: mediatek,mt6873-spmi
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: pmif
+      - const: spmimst
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: pmif_sys_ck
+      - const: pmif_tmr_ck
+      - const: spmimst_clk_mux
+
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-parents:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8192-clk.h>
+
+    spmi: spmi@10027000 {
+        compatible = "mediatek,mt6873-spmi";
+        reg = <0 0x10027000 0 0x000e00>,
+              <0 0x10029000 0 0x000100>;
+        reg-names = "pmif", "spmimst";
+        clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+                 <&infracfg CLK_INFRA_PMIC_TMR>,
+                 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+        clock-names = "pmif_sys_ck",
+                      "pmif_tmr_ck",
+                      "spmimst_clk_mux";
+        assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+    };
+...
-- 
2.18.0

[PATCH v6 2/4] dt-bindings: spmi: document binding for the Mediatek SPMI controller

[Hsin-Hsiung Wang]

This adds documentation for the SPMI controller found on Mediatek SoCs.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
changes since v5: no changes
---
 .../bindings/spmi/mtk,spmi-mtk-pmif.yaml      | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml

diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
new file mode 100644
index 000000000000..a43b0302d503
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek SPMI Controller Device Tree Bindings
+
+maintainers:
+  - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
+
+description: |+
+  On MediaTek SoCs the PMIC is connected via SPMI and the controller allows
+  for multiple SoCs to control a single SPMI master.
+
+allOf:
+  - $ref: "spmi.yaml"
+
+properties:
+  compatible:
+    const: mediatek,mt6873-spmi
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: pmif
+      - const: spmimst
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: pmif_sys_ck
+      - const: pmif_tmr_ck
+      - const: spmimst_clk_mux
+
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-parents:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8192-clk.h>
+
+    spmi: spmi@10027000 {
+        compatible = "mediatek,mt6873-spmi";
+        reg = <0 0x10027000 0 0x000e00>,
+              <0 0x10029000 0 0x000100>;
+        reg-names = "pmif", "spmimst";
+        clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+                 <&infracfg CLK_INFRA_PMIC_TMR>,
+                 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+        clock-names = "pmif_sys_ck",
+                      "pmif_tmr_ck",
+                      "spmimst_clk_mux";
+        assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+    };
+...
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 2/4] dt-bindings: spmi: document binding for the Mediatek SPMI controller

[Hsin-Hsiung Wang]

This adds documentation for the SPMI controller found on Mediatek SoCs.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
changes since v5: no changes
---
 .../bindings/spmi/mtk,spmi-mtk-pmif.yaml      | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml

diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
new file mode 100644
index 000000000000..a43b0302d503
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek SPMI Controller Device Tree Bindings
+
+maintainers:
+  - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
+
+description: |+
+  On MediaTek SoCs the PMIC is connected via SPMI and the controller allows
+  for multiple SoCs to control a single SPMI master.
+
+allOf:
+  - $ref: "spmi.yaml"
+
+properties:
+  compatible:
+    const: mediatek,mt6873-spmi
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: pmif
+      - const: spmimst
+
+  clocks:
+    minItems: 3
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: pmif_sys_ck
+      - const: pmif_tmr_ck
+      - const: spmimst_clk_mux
+
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-parents:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8192-clk.h>
+
+    spmi: spmi@10027000 {
+        compatible = "mediatek,mt6873-spmi";
+        reg = <0 0x10027000 0 0x000e00>,
+              <0 0x10029000 0 0x000100>;
+        reg-names = "pmif", "spmimst";
+        clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+                 <&infracfg CLK_INFRA_PMIC_TMR>,
+                 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+        clock-names = "pmif_sys_ck",
+                      "pmif_tmr_ck",
+                      "spmimst_clk_mux";
+        assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+    };
+...
-- 
2.18.0
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[PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Hsin-Hsiung Wang]

Add spmi support for MT6873/8192.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- add a newline at end of Makefile.
- refine the spmi-mtk-pmif driver for better code quality. 
---
 drivers/spmi/Kconfig         |   9 +
 drivers/spmi/Makefile        |   2 +
 drivers/spmi/spmi-mtk-pmif.c | 488 +++++++++++++++++++++++++++++++++++
 3 files changed, 499 insertions(+)
 create mode 100644 drivers/spmi/spmi-mtk-pmif.c

diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index a53bad541f1a..418848840999 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
 	  This is required for communicating with Qualcomm PMICs and
 	  other devices that have the SPMI interface.
 
+config SPMI_MTK_PMIF
+	tristate "Mediatek SPMI Controller (PMIC Arbiter)"
+	help
+	  If you say yes to this option, support will be included for the
+	  built-in SPMI PMIC Arbiter interface on Mediatek family
+	  processors.
+
+	  This is required for communicating with Mediatek PMICs and
+	  other devices that have the SPMI interface.
 endif
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 55a94cadeffe..76fb3b3ab510 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -5,3 +5,5 @@
 obj-$(CONFIG_SPMI)	+= spmi.o
 
 obj-$(CONFIG_SPMI_MSM_PMIC_ARB)	+= spmi-pmic-arb.o
+obj-$(CONFIG_SPMI_MTK_PMIF)	+= spmi-mtk-pmif.o
+
diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
new file mode 100644
index 000000000000..4ac4643f89f3
--- /dev/null
+++ b/drivers/spmi/spmi-mtk-pmif.c
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2021 MediaTek Inc.
+
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/spmi.h>
+
+#define SWINF_IDLE	0x00
+#define SWINF_WFVLDCLR	0x06
+
+#define GET_SWINF(x)	(((x) >> 1) & 0x7)
+
+#define PMIF_CMD_REG_0		0
+#define PMIF_CMD_REG		1
+#define PMIF_CMD_EXT_REG	2
+#define PMIF_CMD_EXT_REG_LONG	3
+
+#define PMIF_DELAY_US   10
+#define PMIF_TIMEOUT_US (10 * 1000)
+
+#define PMIF_CHAN_OFFSET 0x5
+
+#define PMIF_MAX_CLKS	3
+
+#define SPMI_OP_ST_BUSY 1
+
+struct ch_reg {
+	u32 ch_sta;
+	u32 wdata;
+	u32 rdata;
+	u32 ch_send;
+	u32 ch_rdy;
+};
+
+struct pmif_data {
+	const u32	*regs;
+	const u32	*spmimst_regs;
+	u32	soc_chan;
+};
+
+struct pmif {
+	void __iomem	*base;
+	void __iomem	*spmimst_base;
+	raw_spinlock_t	lock;
+	struct ch_reg	chan;
+	struct clk_bulk_data clks[PMIF_MAX_CLKS];
+	u32 nclks;
+	const struct pmif_data *data;
+};
+
+static const char * const pmif_clock_names[] = {
+	"pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
+};
+
+enum pmif_regs {
+	PMIF_INIT_DONE,
+	PMIF_INF_EN,
+	PMIF_ARB_EN,
+	PMIF_CMDISSUE_EN,
+	PMIF_TIMER_CTRL,
+	PMIF_SPI_MODE_CTRL,
+	PMIF_IRQ_EVENT_EN_0,
+	PMIF_IRQ_FLAG_0,
+	PMIF_IRQ_CLR_0,
+	PMIF_IRQ_EVENT_EN_1,
+	PMIF_IRQ_FLAG_1,
+	PMIF_IRQ_CLR_1,
+	PMIF_IRQ_EVENT_EN_2,
+	PMIF_IRQ_FLAG_2,
+	PMIF_IRQ_CLR_2,
+	PMIF_IRQ_EVENT_EN_3,
+	PMIF_IRQ_FLAG_3,
+	PMIF_IRQ_CLR_3,
+	PMIF_IRQ_EVENT_EN_4,
+	PMIF_IRQ_FLAG_4,
+	PMIF_IRQ_CLR_4,
+	PMIF_WDT_EVENT_EN_0,
+	PMIF_WDT_FLAG_0,
+	PMIF_WDT_EVENT_EN_1,
+	PMIF_WDT_FLAG_1,
+	PMIF_SWINF_0_STA,
+	PMIF_SWINF_0_WDATA_31_0,
+	PMIF_SWINF_0_RDATA_31_0,
+	PMIF_SWINF_0_ACC,
+	PMIF_SWINF_0_VLD_CLR,
+	PMIF_SWINF_1_STA,
+	PMIF_SWINF_1_WDATA_31_0,
+	PMIF_SWINF_1_RDATA_31_0,
+	PMIF_SWINF_1_ACC,
+	PMIF_SWINF_1_VLD_CLR,
+	PMIF_SWINF_2_STA,
+	PMIF_SWINF_2_WDATA_31_0,
+	PMIF_SWINF_2_RDATA_31_0,
+	PMIF_SWINF_2_ACC,
+	PMIF_SWINF_2_VLD_CLR,
+	PMIF_SWINF_3_STA,
+	PMIF_SWINF_3_WDATA_31_0,
+	PMIF_SWINF_3_RDATA_31_0,
+	PMIF_SWINF_3_ACC,
+	PMIF_SWINF_3_VLD_CLR,
+};
+
+static const u32 mt6873_regs[] = {
+	[PMIF_INIT_DONE] =	0x0000,
+	[PMIF_INF_EN] =		0x0024,
+	[PMIF_ARB_EN] =		0x0150,
+	[PMIF_CMDISSUE_EN] =	0x03B4,
+	[PMIF_TIMER_CTRL] =	0x03E0,
+	[PMIF_SPI_MODE_CTRL] =	0x0400,
+	[PMIF_IRQ_EVENT_EN_0] =	0x0418,
+	[PMIF_IRQ_FLAG_0] =	0x0420,
+	[PMIF_IRQ_CLR_0] =	0x0424,
+	[PMIF_IRQ_EVENT_EN_1] =	0x0428,
+	[PMIF_IRQ_FLAG_1] =	0x0430,
+	[PMIF_IRQ_CLR_1] =	0x0434,
+	[PMIF_IRQ_EVENT_EN_2] =	0x0438,
+	[PMIF_IRQ_FLAG_2] =	0x0440,
+	[PMIF_IRQ_CLR_2] =	0x0444,
+	[PMIF_IRQ_EVENT_EN_3] =	0x0448,
+	[PMIF_IRQ_FLAG_3] =	0x0450,
+	[PMIF_IRQ_CLR_3] =	0x0454,
+	[PMIF_IRQ_EVENT_EN_4] =	0x0458,
+	[PMIF_IRQ_FLAG_4] =	0x0460,
+	[PMIF_IRQ_CLR_4] =	0x0464,
+	[PMIF_WDT_EVENT_EN_0] =	0x046C,
+	[PMIF_WDT_FLAG_0] =	0x0470,
+	[PMIF_WDT_EVENT_EN_1] =	0x0474,
+	[PMIF_WDT_FLAG_1] =	0x0478,
+	[PMIF_SWINF_0_ACC] =	0x0C00,
+	[PMIF_SWINF_0_WDATA_31_0] =	0x0C04,
+	[PMIF_SWINF_0_RDATA_31_0] =	0x0C14,
+	[PMIF_SWINF_0_VLD_CLR] =	0x0C24,
+	[PMIF_SWINF_0_STA] =	0x0C28,
+	[PMIF_SWINF_1_ACC] =	0x0C40,
+	[PMIF_SWINF_1_WDATA_31_0] =	0x0C44,
+	[PMIF_SWINF_1_RDATA_31_0] =	0x0C54,
+	[PMIF_SWINF_1_VLD_CLR] =	0x0C64,
+	[PMIF_SWINF_1_STA] =	0x0C68,
+	[PMIF_SWINF_2_ACC] =	0x0C80,
+	[PMIF_SWINF_2_WDATA_31_0] =	0x0C84,
+	[PMIF_SWINF_2_RDATA_31_0] =	0x0C94,
+	[PMIF_SWINF_2_VLD_CLR] =	0x0CA4,
+	[PMIF_SWINF_2_STA] =	0x0CA8,
+	[PMIF_SWINF_3_ACC] =	0x0CC0,
+	[PMIF_SWINF_3_WDATA_31_0] =	0x0CC4,
+	[PMIF_SWINF_3_RDATA_31_0] =	0x0CD4,
+	[PMIF_SWINF_3_VLD_CLR] =	0x0CE4,
+	[PMIF_SWINF_3_STA] =	0x0CE8,
+};
+
+enum spmi_regs {
+	SPMI_OP_ST_CTRL,
+	SPMI_GRP_ID_EN,
+	SPMI_OP_ST_STA,
+	SPMI_MST_SAMPL,
+	SPMI_MST_REQ_EN,
+	SPMI_REC_CTRL,
+	SPMI_REC0,
+	SPMI_REC1,
+	SPMI_REC2,
+	SPMI_REC3,
+	SPMI_REC4,
+	SPMI_MST_DBG,
+};
+
+static const u32 mt6873_spmi_regs[] = {
+	[SPMI_OP_ST_CTRL] =	0x0000,
+	[SPMI_GRP_ID_EN] =	0x0004,
+	[SPMI_OP_ST_STA] =	0x0008,
+	[SPMI_MST_SAMPL] =	0x000c,
+	[SPMI_MST_REQ_EN] =	0x0010,
+	[SPMI_REC_CTRL] =	0x0040,
+	[SPMI_REC0] =		0x0044,
+	[SPMI_REC1] =		0x0048,
+	[SPMI_REC2] =		0x004c,
+	[SPMI_REC3] =		0x0050,
+	[SPMI_REC4] =		0x0054,
+	[SPMI_MST_DBG] =	0x00fc,
+};
+
+static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
+{
+	return readl(arb->base + arb->data->regs[reg]);
+}
+
+static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
+{
+	writel(val, arb->base + arb->data->regs[reg]);
+}
+
+static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
+{
+	writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
+}
+
+static bool pmif_is_fsm_vldclr(struct pmif *arb)
+{
+	u32 reg_rdata;
+
+	reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
+	return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
+}
+
+static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	u32 rdata, cmd;
+	int ret;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	/* Check the opcode */
+	if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
+		return -EINVAL;
+
+	cmd = opc - SPMI_CMD_RESET;
+
+	mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
+	ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
+					rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0)
+		dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
+
+	return ret;
+}
+
+static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+			      u16 addr, u8 *buf, size_t len)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	struct ch_reg *inf_reg;
+	int ret;
+	u32 data, cmd;
+	unsigned long flags;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	if (len > 4) {
+		dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
+		return -EINVAL;
+	}
+
+	if (opc >= 0x60 && opc <= 0x7f)
+		opc = PMIF_CMD_REG;
+	else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&arb->lock, flags);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	inf_reg = &arb->chan;
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_IDLE,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		/* set channel ready if the data has transferred */
+		if (pmif_is_fsm_vldclr(arb))
+			pmif_writel(arb, 1, inf_reg->ch_rdy);
+		dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
+		goto out;
+	}
+
+	/* Send the command. */
+	cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
+	pmif_writel(arb, cmd, inf_reg->ch_send);
+
+	/*
+	 * Wait for Software Interface FSM state to be WFVLDCLR,
+	 * read the data and clear the valid flag.
+	 */
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_WFVLDCLR,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
+		goto out;
+	}
+
+	data = pmif_readl(arb, inf_reg->rdata);
+	memcpy(buf, &data, len);
+	pmif_writel(arb, 1, inf_reg->ch_rdy);
+
+out:
+	raw_spin_unlock_irqrestore(&arb->lock, flags);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+			       u16 addr, const u8 *buf, size_t len)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	struct ch_reg *inf_reg;
+	int ret;
+	u32 data, cmd;
+	unsigned long flags;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	if (len > 4) {
+		dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
+		return -EINVAL;
+	}
+
+	/* Check the opcode */
+	if (opc >= 0x40 && opc <= 0x5F)
+		opc = PMIF_CMD_REG;
+	else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else if (opc >= 0x80)
+		opc = PMIF_CMD_REG_0;
+	else
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&arb->lock, flags);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	inf_reg = &arb->chan;
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_IDLE,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		/* set channel ready if the data has transferred */
+		if (pmif_is_fsm_vldclr(arb))
+			pmif_writel(arb, 1, inf_reg->ch_rdy);
+		dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
+		goto out;
+	}
+
+	/* Set the write data. */
+	memcpy(&data, buf, len);
+	pmif_writel(arb, data, inf_reg->wdata);
+
+	/* Send the command. */
+	cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
+	pmif_writel(arb, cmd, inf_reg->ch_send);
+
+out:
+	raw_spin_unlock_irqrestore(&arb->lock, flags);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static const struct pmif_data mt6873_pmif_arb = {
+	.regs = mt6873_regs,
+	.spmimst_regs = mt6873_spmi_regs,
+	.soc_chan = 2,
+};
+
+static int mtk_spmi_probe(struct platform_device *pdev)
+{
+	struct pmif *arb;
+	struct spmi_controller *ctrl;
+	int err, i;
+	u32 chan_offset;
+
+	ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb));
+	if (!ctrl)
+		return -ENOMEM;
+
+	arb = spmi_controller_get_drvdata(ctrl);
+	arb->data = of_device_get_match_data(&pdev->dev);
+	if (!arb->data) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "Cannot get drv_data\n");
+		goto err_put_ctrl;
+	}
+
+	arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif");
+	if (IS_ERR(arb->base)) {
+		err = PTR_ERR(arb->base);
+		dev_err(&pdev->dev, "pmif failed to get the remappped memory\n");
+		goto err_put_ctrl;
+	}
+
+	arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst");
+	if (IS_ERR(arb->spmimst_base)) {
+		err = PTR_ERR(arb->spmimst_base);
+		dev_err(&pdev->dev, "spmimst failed to get the remappped memory\n");
+		goto err_put_ctrl;
+	}
+
+	arb->nclks = ARRAY_SIZE(pmif_clock_names);
+	if (arb->nclks > PMIF_MAX_CLKS) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "exceed the max clock numbers\n");
+		goto err_put_ctrl;
+	}
+
+	for (i = 0; i < arb->nclks; i++)
+		arb->clks[i].id = pmif_clock_names[i];
+
+	err = devm_clk_bulk_get(&pdev->dev, arb->nclks, arb->clks);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to get clocks: %d\n", err);
+		goto err_put_ctrl;
+	}
+
+	err = clk_bulk_prepare_enable(arb->nclks, arb->clks);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err);
+		goto err_put_ctrl;
+	}
+
+	ctrl->cmd = pmif_arb_cmd;
+	ctrl->read_cmd = pmif_spmi_read_cmd;
+	ctrl->write_cmd = pmif_spmi_write_cmd;
+
+	chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan;
+	arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset;
+	arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset;
+	arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset;
+	arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset;
+	arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset;
+
+	raw_spin_lock_init(&arb->lock);
+
+	platform_set_drvdata(pdev, ctrl);
+
+	err = spmi_controller_add(ctrl);
+	if (err)
+		goto err_domain_remove;
+
+	return 0;
+
+err_domain_remove:
+	clk_bulk_disable_unprepare(arb->nclks, arb->clks);
+err_put_ctrl:
+	spmi_controller_put(ctrl);
+	return err;
+}
+
+static int mtk_spmi_remove(struct platform_device *pdev)
+{
+	struct spmi_controller *ctrl = platform_get_drvdata(pdev);
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+
+	clk_bulk_disable_unprepare(arb->nclks, arb->clks);
+	spmi_controller_remove(ctrl);
+	spmi_controller_put(ctrl);
+	return 0;
+}
+
+static const struct of_device_id mtk_spmi_match_table[] = {
+	{
+		.compatible = "mediatek,mt6873-spmi",
+		.data = &mt6873_pmif_arb,
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, mtk_spmi_match_table);
+
+static struct platform_driver mtk_spmi_driver = {
+	.driver		= {
+		.name	= "spmi-mtk",
+		.of_match_table = of_match_ptr(mtk_spmi_match_table),
+	},
+	.probe		= mtk_spmi_probe,
+	.remove		= mtk_spmi_remove,
+};
+module_platform_driver(mtk_spmi_driver);
+
+MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek SPMI Driver");
+MODULE_LICENSE("GPL");
-- 
2.18.0

[PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Hsin-Hsiung Wang]

Add spmi support for MT6873/8192.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- add a newline at end of Makefile.
- refine the spmi-mtk-pmif driver for better code quality. 
---
 drivers/spmi/Kconfig         |   9 +
 drivers/spmi/Makefile        |   2 +
 drivers/spmi/spmi-mtk-pmif.c | 488 +++++++++++++++++++++++++++++++++++
 3 files changed, 499 insertions(+)
 create mode 100644 drivers/spmi/spmi-mtk-pmif.c

diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index a53bad541f1a..418848840999 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
 	  This is required for communicating with Qualcomm PMICs and
 	  other devices that have the SPMI interface.
 
+config SPMI_MTK_PMIF
+	tristate "Mediatek SPMI Controller (PMIC Arbiter)"
+	help
+	  If you say yes to this option, support will be included for the
+	  built-in SPMI PMIC Arbiter interface on Mediatek family
+	  processors.
+
+	  This is required for communicating with Mediatek PMICs and
+	  other devices that have the SPMI interface.
 endif
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 55a94cadeffe..76fb3b3ab510 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -5,3 +5,5 @@
 obj-$(CONFIG_SPMI)	+= spmi.o
 
 obj-$(CONFIG_SPMI_MSM_PMIC_ARB)	+= spmi-pmic-arb.o
+obj-$(CONFIG_SPMI_MTK_PMIF)	+= spmi-mtk-pmif.o
+
diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
new file mode 100644
index 000000000000..4ac4643f89f3
--- /dev/null
+++ b/drivers/spmi/spmi-mtk-pmif.c
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2021 MediaTek Inc.
+
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/spmi.h>
+
+#define SWINF_IDLE	0x00
+#define SWINF_WFVLDCLR	0x06
+
+#define GET_SWINF(x)	(((x) >> 1) & 0x7)
+
+#define PMIF_CMD_REG_0		0
+#define PMIF_CMD_REG		1
+#define PMIF_CMD_EXT_REG	2
+#define PMIF_CMD_EXT_REG_LONG	3
+
+#define PMIF_DELAY_US   10
+#define PMIF_TIMEOUT_US (10 * 1000)
+
+#define PMIF_CHAN_OFFSET 0x5
+
+#define PMIF_MAX_CLKS	3
+
+#define SPMI_OP_ST_BUSY 1
+
+struct ch_reg {
+	u32 ch_sta;
+	u32 wdata;
+	u32 rdata;
+	u32 ch_send;
+	u32 ch_rdy;
+};
+
+struct pmif_data {
+	const u32	*regs;
+	const u32	*spmimst_regs;
+	u32	soc_chan;
+};
+
+struct pmif {
+	void __iomem	*base;
+	void __iomem	*spmimst_base;
+	raw_spinlock_t	lock;
+	struct ch_reg	chan;
+	struct clk_bulk_data clks[PMIF_MAX_CLKS];
+	u32 nclks;
+	const struct pmif_data *data;
+};
+
+static const char * const pmif_clock_names[] = {
+	"pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
+};
+
+enum pmif_regs {
+	PMIF_INIT_DONE,
+	PMIF_INF_EN,
+	PMIF_ARB_EN,
+	PMIF_CMDISSUE_EN,
+	PMIF_TIMER_CTRL,
+	PMIF_SPI_MODE_CTRL,
+	PMIF_IRQ_EVENT_EN_0,
+	PMIF_IRQ_FLAG_0,
+	PMIF_IRQ_CLR_0,
+	PMIF_IRQ_EVENT_EN_1,
+	PMIF_IRQ_FLAG_1,
+	PMIF_IRQ_CLR_1,
+	PMIF_IRQ_EVENT_EN_2,
+	PMIF_IRQ_FLAG_2,
+	PMIF_IRQ_CLR_2,
+	PMIF_IRQ_EVENT_EN_3,
+	PMIF_IRQ_FLAG_3,
+	PMIF_IRQ_CLR_3,
+	PMIF_IRQ_EVENT_EN_4,
+	PMIF_IRQ_FLAG_4,
+	PMIF_IRQ_CLR_4,
+	PMIF_WDT_EVENT_EN_0,
+	PMIF_WDT_FLAG_0,
+	PMIF_WDT_EVENT_EN_1,
+	PMIF_WDT_FLAG_1,
+	PMIF_SWINF_0_STA,
+	PMIF_SWINF_0_WDATA_31_0,
+	PMIF_SWINF_0_RDATA_31_0,
+	PMIF_SWINF_0_ACC,
+	PMIF_SWINF_0_VLD_CLR,
+	PMIF_SWINF_1_STA,
+	PMIF_SWINF_1_WDATA_31_0,
+	PMIF_SWINF_1_RDATA_31_0,
+	PMIF_SWINF_1_ACC,
+	PMIF_SWINF_1_VLD_CLR,
+	PMIF_SWINF_2_STA,
+	PMIF_SWINF_2_WDATA_31_0,
+	PMIF_SWINF_2_RDATA_31_0,
+	PMIF_SWINF_2_ACC,
+	PMIF_SWINF_2_VLD_CLR,
+	PMIF_SWINF_3_STA,
+	PMIF_SWINF_3_WDATA_31_0,
+	PMIF_SWINF_3_RDATA_31_0,
+	PMIF_SWINF_3_ACC,
+	PMIF_SWINF_3_VLD_CLR,
+};
+
+static const u32 mt6873_regs[] = {
+	[PMIF_INIT_DONE] =	0x0000,
+	[PMIF_INF_EN] =		0x0024,
+	[PMIF_ARB_EN] =		0x0150,
+	[PMIF_CMDISSUE_EN] =	0x03B4,
+	[PMIF_TIMER_CTRL] =	0x03E0,
+	[PMIF_SPI_MODE_CTRL] =	0x0400,
+	[PMIF_IRQ_EVENT_EN_0] =	0x0418,
+	[PMIF_IRQ_FLAG_0] =	0x0420,
+	[PMIF_IRQ_CLR_0] =	0x0424,
+	[PMIF_IRQ_EVENT_EN_1] =	0x0428,
+	[PMIF_IRQ_FLAG_1] =	0x0430,
+	[PMIF_IRQ_CLR_1] =	0x0434,
+	[PMIF_IRQ_EVENT_EN_2] =	0x0438,
+	[PMIF_IRQ_FLAG_2] =	0x0440,
+	[PMIF_IRQ_CLR_2] =	0x0444,
+	[PMIF_IRQ_EVENT_EN_3] =	0x0448,
+	[PMIF_IRQ_FLAG_3] =	0x0450,
+	[PMIF_IRQ_CLR_3] =	0x0454,
+	[PMIF_IRQ_EVENT_EN_4] =	0x0458,
+	[PMIF_IRQ_FLAG_4] =	0x0460,
+	[PMIF_IRQ_CLR_4] =	0x0464,
+	[PMIF_WDT_EVENT_EN_0] =	0x046C,
+	[PMIF_WDT_FLAG_0] =	0x0470,
+	[PMIF_WDT_EVENT_EN_1] =	0x0474,
+	[PMIF_WDT_FLAG_1] =	0x0478,
+	[PMIF_SWINF_0_ACC] =	0x0C00,
+	[PMIF_SWINF_0_WDATA_31_0] =	0x0C04,
+	[PMIF_SWINF_0_RDATA_31_0] =	0x0C14,
+	[PMIF_SWINF_0_VLD_CLR] =	0x0C24,
+	[PMIF_SWINF_0_STA] =	0x0C28,
+	[PMIF_SWINF_1_ACC] =	0x0C40,
+	[PMIF_SWINF_1_WDATA_31_0] =	0x0C44,
+	[PMIF_SWINF_1_RDATA_31_0] =	0x0C54,
+	[PMIF_SWINF_1_VLD_CLR] =	0x0C64,
+	[PMIF_SWINF_1_STA] =	0x0C68,
+	[PMIF_SWINF_2_ACC] =	0x0C80,
+	[PMIF_SWINF_2_WDATA_31_0] =	0x0C84,
+	[PMIF_SWINF_2_RDATA_31_0] =	0x0C94,
+	[PMIF_SWINF_2_VLD_CLR] =	0x0CA4,
+	[PMIF_SWINF_2_STA] =	0x0CA8,
+	[PMIF_SWINF_3_ACC] =	0x0CC0,
+	[PMIF_SWINF_3_WDATA_31_0] =	0x0CC4,
+	[PMIF_SWINF_3_RDATA_31_0] =	0x0CD4,
+	[PMIF_SWINF_3_VLD_CLR] =	0x0CE4,
+	[PMIF_SWINF_3_STA] =	0x0CE8,
+};
+
+enum spmi_regs {
+	SPMI_OP_ST_CTRL,
+	SPMI_GRP_ID_EN,
+	SPMI_OP_ST_STA,
+	SPMI_MST_SAMPL,
+	SPMI_MST_REQ_EN,
+	SPMI_REC_CTRL,
+	SPMI_REC0,
+	SPMI_REC1,
+	SPMI_REC2,
+	SPMI_REC3,
+	SPMI_REC4,
+	SPMI_MST_DBG,
+};
+
+static const u32 mt6873_spmi_regs[] = {
+	[SPMI_OP_ST_CTRL] =	0x0000,
+	[SPMI_GRP_ID_EN] =	0x0004,
+	[SPMI_OP_ST_STA] =	0x0008,
+	[SPMI_MST_SAMPL] =	0x000c,
+	[SPMI_MST_REQ_EN] =	0x0010,
+	[SPMI_REC_CTRL] =	0x0040,
+	[SPMI_REC0] =		0x0044,
+	[SPMI_REC1] =		0x0048,
+	[SPMI_REC2] =		0x004c,
+	[SPMI_REC3] =		0x0050,
+	[SPMI_REC4] =		0x0054,
+	[SPMI_MST_DBG] =	0x00fc,
+};
+
+static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
+{
+	return readl(arb->base + arb->data->regs[reg]);
+}
+
+static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
+{
+	writel(val, arb->base + arb->data->regs[reg]);
+}
+
+static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
+{
+	writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
+}
+
+static bool pmif_is_fsm_vldclr(struct pmif *arb)
+{
+	u32 reg_rdata;
+
+	reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
+	return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
+}
+
+static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	u32 rdata, cmd;
+	int ret;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	/* Check the opcode */
+	if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
+		return -EINVAL;
+
+	cmd = opc - SPMI_CMD_RESET;
+
+	mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
+	ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
+					rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0)
+		dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
+
+	return ret;
+}
+
+static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+			      u16 addr, u8 *buf, size_t len)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	struct ch_reg *inf_reg;
+	int ret;
+	u32 data, cmd;
+	unsigned long flags;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	if (len > 4) {
+		dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
+		return -EINVAL;
+	}
+
+	if (opc >= 0x60 && opc <= 0x7f)
+		opc = PMIF_CMD_REG;
+	else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&arb->lock, flags);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	inf_reg = &arb->chan;
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_IDLE,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		/* set channel ready if the data has transferred */
+		if (pmif_is_fsm_vldclr(arb))
+			pmif_writel(arb, 1, inf_reg->ch_rdy);
+		dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
+		goto out;
+	}
+
+	/* Send the command. */
+	cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
+	pmif_writel(arb, cmd, inf_reg->ch_send);
+
+	/*
+	 * Wait for Software Interface FSM state to be WFVLDCLR,
+	 * read the data and clear the valid flag.
+	 */
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_WFVLDCLR,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
+		goto out;
+	}
+
+	data = pmif_readl(arb, inf_reg->rdata);
+	memcpy(buf, &data, len);
+	pmif_writel(arb, 1, inf_reg->ch_rdy);
+
+out:
+	raw_spin_unlock_irqrestore(&arb->lock, flags);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+			       u16 addr, const u8 *buf, size_t len)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	struct ch_reg *inf_reg;
+	int ret;
+	u32 data, cmd;
+	unsigned long flags;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	if (len > 4) {
+		dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
+		return -EINVAL;
+	}
+
+	/* Check the opcode */
+	if (opc >= 0x40 && opc <= 0x5F)
+		opc = PMIF_CMD_REG;
+	else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else if (opc >= 0x80)
+		opc = PMIF_CMD_REG_0;
+	else
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&arb->lock, flags);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	inf_reg = &arb->chan;
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_IDLE,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		/* set channel ready if the data has transferred */
+		if (pmif_is_fsm_vldclr(arb))
+			pmif_writel(arb, 1, inf_reg->ch_rdy);
+		dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
+		goto out;
+	}
+
+	/* Set the write data. */
+	memcpy(&data, buf, len);
+	pmif_writel(arb, data, inf_reg->wdata);
+
+	/* Send the command. */
+	cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
+	pmif_writel(arb, cmd, inf_reg->ch_send);
+
+out:
+	raw_spin_unlock_irqrestore(&arb->lock, flags);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static const struct pmif_data mt6873_pmif_arb = {
+	.regs = mt6873_regs,
+	.spmimst_regs = mt6873_spmi_regs,
+	.soc_chan = 2,
+};
+
+static int mtk_spmi_probe(struct platform_device *pdev)
+{
+	struct pmif *arb;
+	struct spmi_controller *ctrl;
+	int err, i;
+	u32 chan_offset;
+
+	ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb));
+	if (!ctrl)
+		return -ENOMEM;
+
+	arb = spmi_controller_get_drvdata(ctrl);
+	arb->data = of_device_get_match_data(&pdev->dev);
+	if (!arb->data) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "Cannot get drv_data\n");
+		goto err_put_ctrl;
+	}
+
+	arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif");
+	if (IS_ERR(arb->base)) {
+		err = PTR_ERR(arb->base);
+		dev_err(&pdev->dev, "pmif failed to get the remappped memory\n");
+		goto err_put_ctrl;
+	}
+
+	arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst");
+	if (IS_ERR(arb->spmimst_base)) {
+		err = PTR_ERR(arb->spmimst_base);
+		dev_err(&pdev->dev, "spmimst failed to get the remappped memory\n");
+		goto err_put_ctrl;
+	}
+
+	arb->nclks = ARRAY_SIZE(pmif_clock_names);
+	if (arb->nclks > PMIF_MAX_CLKS) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "exceed the max clock numbers\n");
+		goto err_put_ctrl;
+	}
+
+	for (i = 0; i < arb->nclks; i++)
+		arb->clks[i].id = pmif_clock_names[i];
+
+	err = devm_clk_bulk_get(&pdev->dev, arb->nclks, arb->clks);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to get clocks: %d\n", err);
+		goto err_put_ctrl;
+	}
+
+	err = clk_bulk_prepare_enable(arb->nclks, arb->clks);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err);
+		goto err_put_ctrl;
+	}
+
+	ctrl->cmd = pmif_arb_cmd;
+	ctrl->read_cmd = pmif_spmi_read_cmd;
+	ctrl->write_cmd = pmif_spmi_write_cmd;
+
+	chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan;
+	arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset;
+	arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset;
+	arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset;
+	arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset;
+	arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset;
+
+	raw_spin_lock_init(&arb->lock);
+
+	platform_set_drvdata(pdev, ctrl);
+
+	err = spmi_controller_add(ctrl);
+	if (err)
+		goto err_domain_remove;
+
+	return 0;
+
+err_domain_remove:
+	clk_bulk_disable_unprepare(arb->nclks, arb->clks);
+err_put_ctrl:
+	spmi_controller_put(ctrl);
+	return err;
+}
+
+static int mtk_spmi_remove(struct platform_device *pdev)
+{
+	struct spmi_controller *ctrl = platform_get_drvdata(pdev);
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+
+	clk_bulk_disable_unprepare(arb->nclks, arb->clks);
+	spmi_controller_remove(ctrl);
+	spmi_controller_put(ctrl);
+	return 0;
+}
+
+static const struct of_device_id mtk_spmi_match_table[] = {
+	{
+		.compatible = "mediatek,mt6873-spmi",
+		.data = &mt6873_pmif_arb,
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, mtk_spmi_match_table);
+
+static struct platform_driver mtk_spmi_driver = {
+	.driver		= {
+		.name	= "spmi-mtk",
+		.of_match_table = of_match_ptr(mtk_spmi_match_table),
+	},
+	.probe		= mtk_spmi_probe,
+	.remove		= mtk_spmi_remove,
+};
+module_platform_driver(mtk_spmi_driver);
+
+MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek SPMI Driver");
+MODULE_LICENSE("GPL");
-- 
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
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[PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Hsin-Hsiung Wang]

Add spmi support for MT6873/8192.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- add a newline at end of Makefile.
- refine the spmi-mtk-pmif driver for better code quality. 
---
 drivers/spmi/Kconfig         |   9 +
 drivers/spmi/Makefile        |   2 +
 drivers/spmi/spmi-mtk-pmif.c | 488 +++++++++++++++++++++++++++++++++++
 3 files changed, 499 insertions(+)
 create mode 100644 drivers/spmi/spmi-mtk-pmif.c

diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index a53bad541f1a..418848840999 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
 	  This is required for communicating with Qualcomm PMICs and
 	  other devices that have the SPMI interface.
 
+config SPMI_MTK_PMIF
+	tristate "Mediatek SPMI Controller (PMIC Arbiter)"
+	help
+	  If you say yes to this option, support will be included for the
+	  built-in SPMI PMIC Arbiter interface on Mediatek family
+	  processors.
+
+	  This is required for communicating with Mediatek PMICs and
+	  other devices that have the SPMI interface.
 endif
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 55a94cadeffe..76fb3b3ab510 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -5,3 +5,5 @@
 obj-$(CONFIG_SPMI)	+= spmi.o
 
 obj-$(CONFIG_SPMI_MSM_PMIC_ARB)	+= spmi-pmic-arb.o
+obj-$(CONFIG_SPMI_MTK_PMIF)	+= spmi-mtk-pmif.o
+
diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
new file mode 100644
index 000000000000..4ac4643f89f3
--- /dev/null
+++ b/drivers/spmi/spmi-mtk-pmif.c
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2021 MediaTek Inc.
+
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/spmi.h>
+
+#define SWINF_IDLE	0x00
+#define SWINF_WFVLDCLR	0x06
+
+#define GET_SWINF(x)	(((x) >> 1) & 0x7)
+
+#define PMIF_CMD_REG_0		0
+#define PMIF_CMD_REG		1
+#define PMIF_CMD_EXT_REG	2
+#define PMIF_CMD_EXT_REG_LONG	3
+
+#define PMIF_DELAY_US   10
+#define PMIF_TIMEOUT_US (10 * 1000)
+
+#define PMIF_CHAN_OFFSET 0x5
+
+#define PMIF_MAX_CLKS	3
+
+#define SPMI_OP_ST_BUSY 1
+
+struct ch_reg {
+	u32 ch_sta;
+	u32 wdata;
+	u32 rdata;
+	u32 ch_send;
+	u32 ch_rdy;
+};
+
+struct pmif_data {
+	const u32	*regs;
+	const u32	*spmimst_regs;
+	u32	soc_chan;
+};
+
+struct pmif {
+	void __iomem	*base;
+	void __iomem	*spmimst_base;
+	raw_spinlock_t	lock;
+	struct ch_reg	chan;
+	struct clk_bulk_data clks[PMIF_MAX_CLKS];
+	u32 nclks;
+	const struct pmif_data *data;
+};
+
+static const char * const pmif_clock_names[] = {
+	"pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
+};
+
+enum pmif_regs {
+	PMIF_INIT_DONE,
+	PMIF_INF_EN,
+	PMIF_ARB_EN,
+	PMIF_CMDISSUE_EN,
+	PMIF_TIMER_CTRL,
+	PMIF_SPI_MODE_CTRL,
+	PMIF_IRQ_EVENT_EN_0,
+	PMIF_IRQ_FLAG_0,
+	PMIF_IRQ_CLR_0,
+	PMIF_IRQ_EVENT_EN_1,
+	PMIF_IRQ_FLAG_1,
+	PMIF_IRQ_CLR_1,
+	PMIF_IRQ_EVENT_EN_2,
+	PMIF_IRQ_FLAG_2,
+	PMIF_IRQ_CLR_2,
+	PMIF_IRQ_EVENT_EN_3,
+	PMIF_IRQ_FLAG_3,
+	PMIF_IRQ_CLR_3,
+	PMIF_IRQ_EVENT_EN_4,
+	PMIF_IRQ_FLAG_4,
+	PMIF_IRQ_CLR_4,
+	PMIF_WDT_EVENT_EN_0,
+	PMIF_WDT_FLAG_0,
+	PMIF_WDT_EVENT_EN_1,
+	PMIF_WDT_FLAG_1,
+	PMIF_SWINF_0_STA,
+	PMIF_SWINF_0_WDATA_31_0,
+	PMIF_SWINF_0_RDATA_31_0,
+	PMIF_SWINF_0_ACC,
+	PMIF_SWINF_0_VLD_CLR,
+	PMIF_SWINF_1_STA,
+	PMIF_SWINF_1_WDATA_31_0,
+	PMIF_SWINF_1_RDATA_31_0,
+	PMIF_SWINF_1_ACC,
+	PMIF_SWINF_1_VLD_CLR,
+	PMIF_SWINF_2_STA,
+	PMIF_SWINF_2_WDATA_31_0,
+	PMIF_SWINF_2_RDATA_31_0,
+	PMIF_SWINF_2_ACC,
+	PMIF_SWINF_2_VLD_CLR,
+	PMIF_SWINF_3_STA,
+	PMIF_SWINF_3_WDATA_31_0,
+	PMIF_SWINF_3_RDATA_31_0,
+	PMIF_SWINF_3_ACC,
+	PMIF_SWINF_3_VLD_CLR,
+};
+
+static const u32 mt6873_regs[] = {
+	[PMIF_INIT_DONE] =	0x0000,
+	[PMIF_INF_EN] =		0x0024,
+	[PMIF_ARB_EN] =		0x0150,
+	[PMIF_CMDISSUE_EN] =	0x03B4,
+	[PMIF_TIMER_CTRL] =	0x03E0,
+	[PMIF_SPI_MODE_CTRL] =	0x0400,
+	[PMIF_IRQ_EVENT_EN_0] =	0x0418,
+	[PMIF_IRQ_FLAG_0] =	0x0420,
+	[PMIF_IRQ_CLR_0] =	0x0424,
+	[PMIF_IRQ_EVENT_EN_1] =	0x0428,
+	[PMIF_IRQ_FLAG_1] =	0x0430,
+	[PMIF_IRQ_CLR_1] =	0x0434,
+	[PMIF_IRQ_EVENT_EN_2] =	0x0438,
+	[PMIF_IRQ_FLAG_2] =	0x0440,
+	[PMIF_IRQ_CLR_2] =	0x0444,
+	[PMIF_IRQ_EVENT_EN_3] =	0x0448,
+	[PMIF_IRQ_FLAG_3] =	0x0450,
+	[PMIF_IRQ_CLR_3] =	0x0454,
+	[PMIF_IRQ_EVENT_EN_4] =	0x0458,
+	[PMIF_IRQ_FLAG_4] =	0x0460,
+	[PMIF_IRQ_CLR_4] =	0x0464,
+	[PMIF_WDT_EVENT_EN_0] =	0x046C,
+	[PMIF_WDT_FLAG_0] =	0x0470,
+	[PMIF_WDT_EVENT_EN_1] =	0x0474,
+	[PMIF_WDT_FLAG_1] =	0x0478,
+	[PMIF_SWINF_0_ACC] =	0x0C00,
+	[PMIF_SWINF_0_WDATA_31_0] =	0x0C04,
+	[PMIF_SWINF_0_RDATA_31_0] =	0x0C14,
+	[PMIF_SWINF_0_VLD_CLR] =	0x0C24,
+	[PMIF_SWINF_0_STA] =	0x0C28,
+	[PMIF_SWINF_1_ACC] =	0x0C40,
+	[PMIF_SWINF_1_WDATA_31_0] =	0x0C44,
+	[PMIF_SWINF_1_RDATA_31_0] =	0x0C54,
+	[PMIF_SWINF_1_VLD_CLR] =	0x0C64,
+	[PMIF_SWINF_1_STA] =	0x0C68,
+	[PMIF_SWINF_2_ACC] =	0x0C80,
+	[PMIF_SWINF_2_WDATA_31_0] =	0x0C84,
+	[PMIF_SWINF_2_RDATA_31_0] =	0x0C94,
+	[PMIF_SWINF_2_VLD_CLR] =	0x0CA4,
+	[PMIF_SWINF_2_STA] =	0x0CA8,
+	[PMIF_SWINF_3_ACC] =	0x0CC0,
+	[PMIF_SWINF_3_WDATA_31_0] =	0x0CC4,
+	[PMIF_SWINF_3_RDATA_31_0] =	0x0CD4,
+	[PMIF_SWINF_3_VLD_CLR] =	0x0CE4,
+	[PMIF_SWINF_3_STA] =	0x0CE8,
+};
+
+enum spmi_regs {
+	SPMI_OP_ST_CTRL,
+	SPMI_GRP_ID_EN,
+	SPMI_OP_ST_STA,
+	SPMI_MST_SAMPL,
+	SPMI_MST_REQ_EN,
+	SPMI_REC_CTRL,
+	SPMI_REC0,
+	SPMI_REC1,
+	SPMI_REC2,
+	SPMI_REC3,
+	SPMI_REC4,
+	SPMI_MST_DBG,
+};
+
+static const u32 mt6873_spmi_regs[] = {
+	[SPMI_OP_ST_CTRL] =	0x0000,
+	[SPMI_GRP_ID_EN] =	0x0004,
+	[SPMI_OP_ST_STA] =	0x0008,
+	[SPMI_MST_SAMPL] =	0x000c,
+	[SPMI_MST_REQ_EN] =	0x0010,
+	[SPMI_REC_CTRL] =	0x0040,
+	[SPMI_REC0] =		0x0044,
+	[SPMI_REC1] =		0x0048,
+	[SPMI_REC2] =		0x004c,
+	[SPMI_REC3] =		0x0050,
+	[SPMI_REC4] =		0x0054,
+	[SPMI_MST_DBG] =	0x00fc,
+};
+
+static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
+{
+	return readl(arb->base + arb->data->regs[reg]);
+}
+
+static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
+{
+	writel(val, arb->base + arb->data->regs[reg]);
+}
+
+static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
+{
+	writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
+}
+
+static bool pmif_is_fsm_vldclr(struct pmif *arb)
+{
+	u32 reg_rdata;
+
+	reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
+	return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
+}
+
+static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	u32 rdata, cmd;
+	int ret;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	/* Check the opcode */
+	if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
+		return -EINVAL;
+
+	cmd = opc - SPMI_CMD_RESET;
+
+	mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
+	ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
+					rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0)
+		dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
+
+	return ret;
+}
+
+static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+			      u16 addr, u8 *buf, size_t len)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	struct ch_reg *inf_reg;
+	int ret;
+	u32 data, cmd;
+	unsigned long flags;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	if (len > 4) {
+		dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
+		return -EINVAL;
+	}
+
+	if (opc >= 0x60 && opc <= 0x7f)
+		opc = PMIF_CMD_REG;
+	else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&arb->lock, flags);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	inf_reg = &arb->chan;
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_IDLE,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		/* set channel ready if the data has transferred */
+		if (pmif_is_fsm_vldclr(arb))
+			pmif_writel(arb, 1, inf_reg->ch_rdy);
+		dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
+		goto out;
+	}
+
+	/* Send the command. */
+	cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
+	pmif_writel(arb, cmd, inf_reg->ch_send);
+
+	/*
+	 * Wait for Software Interface FSM state to be WFVLDCLR,
+	 * read the data and clear the valid flag.
+	 */
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_WFVLDCLR,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
+		goto out;
+	}
+
+	data = pmif_readl(arb, inf_reg->rdata);
+	memcpy(buf, &data, len);
+	pmif_writel(arb, 1, inf_reg->ch_rdy);
+
+out:
+	raw_spin_unlock_irqrestore(&arb->lock, flags);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
+			       u16 addr, const u8 *buf, size_t len)
+{
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+	struct ch_reg *inf_reg;
+	int ret;
+	u32 data, cmd;
+	unsigned long flags;
+
+	/* Check for argument validation. */
+	if (sid & ~0xf) {
+		dev_err(&ctrl->dev, "exceed the max slv id\n");
+		return -EINVAL;
+	}
+
+	if (len > 4) {
+		dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
+		return -EINVAL;
+	}
+
+	/* Check the opcode */
+	if (opc >= 0x40 && opc <= 0x5F)
+		opc = PMIF_CMD_REG;
+	else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
+		opc = PMIF_CMD_EXT_REG_LONG;
+	else if (opc >= 0x80)
+		opc = PMIF_CMD_REG_0;
+	else
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&arb->lock, flags);
+
+	/* Wait for Software Interface FSM state to be IDLE. */
+	inf_reg = &arb->chan;
+	ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
+					data, GET_SWINF(data) == SWINF_IDLE,
+					PMIF_DELAY_US, PMIF_TIMEOUT_US);
+	if (ret < 0) {
+		/* set channel ready if the data has transferred */
+		if (pmif_is_fsm_vldclr(arb))
+			pmif_writel(arb, 1, inf_reg->ch_rdy);
+		dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
+		goto out;
+	}
+
+	/* Set the write data. */
+	memcpy(&data, buf, len);
+	pmif_writel(arb, data, inf_reg->wdata);
+
+	/* Send the command. */
+	cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
+	pmif_writel(arb, cmd, inf_reg->ch_send);
+
+out:
+	raw_spin_unlock_irqrestore(&arb->lock, flags);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static const struct pmif_data mt6873_pmif_arb = {
+	.regs = mt6873_regs,
+	.spmimst_regs = mt6873_spmi_regs,
+	.soc_chan = 2,
+};
+
+static int mtk_spmi_probe(struct platform_device *pdev)
+{
+	struct pmif *arb;
+	struct spmi_controller *ctrl;
+	int err, i;
+	u32 chan_offset;
+
+	ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb));
+	if (!ctrl)
+		return -ENOMEM;
+
+	arb = spmi_controller_get_drvdata(ctrl);
+	arb->data = of_device_get_match_data(&pdev->dev);
+	if (!arb->data) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "Cannot get drv_data\n");
+		goto err_put_ctrl;
+	}
+
+	arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif");
+	if (IS_ERR(arb->base)) {
+		err = PTR_ERR(arb->base);
+		dev_err(&pdev->dev, "pmif failed to get the remappped memory\n");
+		goto err_put_ctrl;
+	}
+
+	arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst");
+	if (IS_ERR(arb->spmimst_base)) {
+		err = PTR_ERR(arb->spmimst_base);
+		dev_err(&pdev->dev, "spmimst failed to get the remappped memory\n");
+		goto err_put_ctrl;
+	}
+
+	arb->nclks = ARRAY_SIZE(pmif_clock_names);
+	if (arb->nclks > PMIF_MAX_CLKS) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "exceed the max clock numbers\n");
+		goto err_put_ctrl;
+	}
+
+	for (i = 0; i < arb->nclks; i++)
+		arb->clks[i].id = pmif_clock_names[i];
+
+	err = devm_clk_bulk_get(&pdev->dev, arb->nclks, arb->clks);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to get clocks: %d\n", err);
+		goto err_put_ctrl;
+	}
+
+	err = clk_bulk_prepare_enable(arb->nclks, arb->clks);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err);
+		goto err_put_ctrl;
+	}
+
+	ctrl->cmd = pmif_arb_cmd;
+	ctrl->read_cmd = pmif_spmi_read_cmd;
+	ctrl->write_cmd = pmif_spmi_write_cmd;
+
+	chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan;
+	arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset;
+	arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset;
+	arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset;
+	arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset;
+	arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset;
+
+	raw_spin_lock_init(&arb->lock);
+
+	platform_set_drvdata(pdev, ctrl);
+
+	err = spmi_controller_add(ctrl);
+	if (err)
+		goto err_domain_remove;
+
+	return 0;
+
+err_domain_remove:
+	clk_bulk_disable_unprepare(arb->nclks, arb->clks);
+err_put_ctrl:
+	spmi_controller_put(ctrl);
+	return err;
+}
+
+static int mtk_spmi_remove(struct platform_device *pdev)
+{
+	struct spmi_controller *ctrl = platform_get_drvdata(pdev);
+	struct pmif *arb = spmi_controller_get_drvdata(ctrl);
+
+	clk_bulk_disable_unprepare(arb->nclks, arb->clks);
+	spmi_controller_remove(ctrl);
+	spmi_controller_put(ctrl);
+	return 0;
+}
+
+static const struct of_device_id mtk_spmi_match_table[] = {
+	{
+		.compatible = "mediatek,mt6873-spmi",
+		.data = &mt6873_pmif_arb,
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, mtk_spmi_match_table);
+
+static struct platform_driver mtk_spmi_driver = {
+	.driver		= {
+		.name	= "spmi-mtk",
+		.of_match_table = of_match_ptr(mtk_spmi_match_table),
+	},
+	.probe		= mtk_spmi_probe,
+	.remove		= mtk_spmi_remove,
+};
+module_platform_driver(mtk_spmi_driver);
+
+MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek SPMI Driver");
+MODULE_LICENSE("GPL");
-- 
2.18.0
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[PATCH v6 4/4] arm64: dts: mt8192: add spmi node

[Hsin-Hsiung Wang]

Add spmi node to SOC MT8192.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- fix the build error of MT8192.dtsi.
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024de122..5e002512441f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -247,6 +247,23 @@
 			clock-names = "clk13m";
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt6873-spmi";
+			reg = <0 0x10027000 0 0x000e00>,
+			      <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+			clock-names = "pmif_sys_ck",
+				      "pmif_tmr_ck",
+				      "spmimst_clk_mux";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
 		uart0: serial@11002000 {
 			compatible = "mediatek,mt8192-uart",
 				     "mediatek,mt6577-uart";
-- 
2.18.0

[PATCH v6 4/4] arm64: dts: mt8192: add spmi node

[Hsin-Hsiung Wang]

Add spmi node to SOC MT8192.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- fix the build error of MT8192.dtsi.
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024de122..5e002512441f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -247,6 +247,23 @@
 			clock-names = "clk13m";
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt6873-spmi";
+			reg = <0 0x10027000 0 0x000e00>,
+			      <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+			clock-names = "pmif_sys_ck",
+				      "pmif_tmr_ck",
+				      "spmimst_clk_mux";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
 		uart0: serial@11002000 {
 			compatible = "mediatek,mt8192-uart",
 				     "mediatek,mt6577-uart";
-- 
2.18.0
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[PATCH v6 4/4] arm64: dts: mt8192: add spmi node

[Hsin-Hsiung Wang]

Add spmi node to SOC MT8192.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
---
changes since v5:
- fix the build error of MT8192.dtsi.
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024de122..5e002512441f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -247,6 +247,23 @@
 			clock-names = "clk13m";
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt6873-spmi";
+			reg = <0 0x10027000 0 0x000e00>,
+			      <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+			clock-names = "pmif_sys_ck",
+				      "pmif_tmr_ck",
+				      "spmimst_clk_mux";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
 		uart0: serial@11002000 {
 			compatible = "mediatek,mt8192-uart",
 				     "mediatek,mt6577-uart";
-- 
2.18.0
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Re: [PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Stephen Boyd]

Quoting Hsin-Hsiung Wang (2021-02-06 21:19:13)
> diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
> index a53bad541f1a..418848840999 100644
> --- a/drivers/spmi/Kconfig
> +++ b/drivers/spmi/Kconfig
> @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
>           This is required for communicating with Qualcomm PMICs and
>           other devices that have the SPMI interface.
>  
> +config SPMI_MTK_PMIF
> +       tristate "Mediatek SPMI Controller (PMIC Arbiter)"
> +       help
> +         If you say yes to this option, support will be included for the
> +         built-in SPMI PMIC Arbiter interface on Mediatek family
> +         processors.
> +
> +         This is required for communicating with Mediatek PMICs and
> +         other devices that have the SPMI interface.

Preferably add another newline here to unstick the 'endif'

>  endif
> diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
> new file mode 100644
> index 000000000000..4ac4643f89f3
> --- /dev/null
> +++ b/drivers/spmi/spmi-mtk-pmif.c
> @@ -0,0 +1,488 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +
> +#include <linux/clk.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/spmi.h>
> +
> +#define SWINF_IDLE     0x00
> +#define SWINF_WFVLDCLR 0x06
> +
> +#define GET_SWINF(x)   (((x) >> 1) & 0x7)
> +
> +#define PMIF_CMD_REG_0         0
> +#define PMIF_CMD_REG           1
> +#define PMIF_CMD_EXT_REG       2
> +#define PMIF_CMD_EXT_REG_LONG  3
> +
> +#define PMIF_DELAY_US   10
> +#define PMIF_TIMEOUT_US (10 * 1000)
> +
> +#define PMIF_CHAN_OFFSET 0x5
> +
> +#define PMIF_MAX_CLKS  3
> +
> +#define SPMI_OP_ST_BUSY 1
> +
> +struct ch_reg {
> +       u32 ch_sta;
> +       u32 wdata;
> +       u32 rdata;
> +       u32 ch_send;
> +       u32 ch_rdy;
> +};
> +
> +struct pmif_data {
> +       const u32       *regs;
> +       const u32       *spmimst_regs;
> +       u32     soc_chan;

Is this used?

> +};
> +
> +struct pmif {
> +       void __iomem    *base;
> +       void __iomem    *spmimst_base;
> +       raw_spinlock_t  lock;

Why is the spinlock raw? Is it used in hard irq handling?

> +       struct ch_reg   chan;
> +       struct clk_bulk_data clks[PMIF_MAX_CLKS];
> +       u32 nclks;
> +       const struct pmif_data *data;
> +};
> +
> +static const char * const pmif_clock_names[] = {
> +       "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
> +};
> +
> +enum pmif_regs {
> +       PMIF_INIT_DONE,
> +       PMIF_INF_EN,
> +       PMIF_ARB_EN,
> +       PMIF_CMDISSUE_EN,
> +       PMIF_TIMER_CTRL,
> +       PMIF_SPI_MODE_CTRL,
> +       PMIF_IRQ_EVENT_EN_0,
> +       PMIF_IRQ_FLAG_0,
> +       PMIF_IRQ_CLR_0,
> +       PMIF_IRQ_EVENT_EN_1,
> +       PMIF_IRQ_FLAG_1,
> +       PMIF_IRQ_CLR_1,
> +       PMIF_IRQ_EVENT_EN_2,
> +       PMIF_IRQ_FLAG_2,
> +       PMIF_IRQ_CLR_2,
> +       PMIF_IRQ_EVENT_EN_3,
> +       PMIF_IRQ_FLAG_3,
> +       PMIF_IRQ_CLR_3,
> +       PMIF_IRQ_EVENT_EN_4,
> +       PMIF_IRQ_FLAG_4,
> +       PMIF_IRQ_CLR_4,
> +       PMIF_WDT_EVENT_EN_0,
> +       PMIF_WDT_FLAG_0,
> +       PMIF_WDT_EVENT_EN_1,
> +       PMIF_WDT_FLAG_1,
> +       PMIF_SWINF_0_STA,
> +       PMIF_SWINF_0_WDATA_31_0,
> +       PMIF_SWINF_0_RDATA_31_0,
> +       PMIF_SWINF_0_ACC,
> +       PMIF_SWINF_0_VLD_CLR,
> +       PMIF_SWINF_1_STA,
> +       PMIF_SWINF_1_WDATA_31_0,
> +       PMIF_SWINF_1_RDATA_31_0,
> +       PMIF_SWINF_1_ACC,
> +       PMIF_SWINF_1_VLD_CLR,
> +       PMIF_SWINF_2_STA,
> +       PMIF_SWINF_2_WDATA_31_0,
> +       PMIF_SWINF_2_RDATA_31_0,
> +       PMIF_SWINF_2_ACC,
> +       PMIF_SWINF_2_VLD_CLR,
> +       PMIF_SWINF_3_STA,
> +       PMIF_SWINF_3_WDATA_31_0,
> +       PMIF_SWINF_3_RDATA_31_0,
> +       PMIF_SWINF_3_ACC,
> +       PMIF_SWINF_3_VLD_CLR,
> +};
> +
> +static const u32 mt6873_regs[] = {
> +       [PMIF_INIT_DONE] =      0x0000,
> +       [PMIF_INF_EN] =         0x0024,
> +       [PMIF_ARB_EN] =         0x0150,
> +       [PMIF_CMDISSUE_EN] =    0x03B4,
> +       [PMIF_TIMER_CTRL] =     0x03E0,
> +       [PMIF_SPI_MODE_CTRL] =  0x0400,
> +       [PMIF_IRQ_EVENT_EN_0] = 0x0418,
> +       [PMIF_IRQ_FLAG_0] =     0x0420,
> +       [PMIF_IRQ_CLR_0] =      0x0424,
> +       [PMIF_IRQ_EVENT_EN_1] = 0x0428,
> +       [PMIF_IRQ_FLAG_1] =     0x0430,
> +       [PMIF_IRQ_CLR_1] =      0x0434,
> +       [PMIF_IRQ_EVENT_EN_2] = 0x0438,
> +       [PMIF_IRQ_FLAG_2] =     0x0440,
> +       [PMIF_IRQ_CLR_2] =      0x0444,
> +       [PMIF_IRQ_EVENT_EN_3] = 0x0448,
> +       [PMIF_IRQ_FLAG_3] =     0x0450,
> +       [PMIF_IRQ_CLR_3] =      0x0454,
> +       [PMIF_IRQ_EVENT_EN_4] = 0x0458,
> +       [PMIF_IRQ_FLAG_4] =     0x0460,
> +       [PMIF_IRQ_CLR_4] =      0x0464,
> +       [PMIF_WDT_EVENT_EN_0] = 0x046C,
> +       [PMIF_WDT_FLAG_0] =     0x0470,
> +       [PMIF_WDT_EVENT_EN_1] = 0x0474,
> +       [PMIF_WDT_FLAG_1] =     0x0478,
> +       [PMIF_SWINF_0_ACC] =    0x0C00,
> +       [PMIF_SWINF_0_WDATA_31_0] =     0x0C04,
> +       [PMIF_SWINF_0_RDATA_31_0] =     0x0C14,
> +       [PMIF_SWINF_0_VLD_CLR] =        0x0C24,
> +       [PMIF_SWINF_0_STA] =    0x0C28,
> +       [PMIF_SWINF_1_ACC] =    0x0C40,
> +       [PMIF_SWINF_1_WDATA_31_0] =     0x0C44,
> +       [PMIF_SWINF_1_RDATA_31_0] =     0x0C54,
> +       [PMIF_SWINF_1_VLD_CLR] =        0x0C64,
> +       [PMIF_SWINF_1_STA] =    0x0C68,
> +       [PMIF_SWINF_2_ACC] =    0x0C80,
> +       [PMIF_SWINF_2_WDATA_31_0] =     0x0C84,
> +       [PMIF_SWINF_2_RDATA_31_0] =     0x0C94,
> +       [PMIF_SWINF_2_VLD_CLR] =        0x0CA4,
> +       [PMIF_SWINF_2_STA] =    0x0CA8,
> +       [PMIF_SWINF_3_ACC] =    0x0CC0,
> +       [PMIF_SWINF_3_WDATA_31_0] =     0x0CC4,
> +       [PMIF_SWINF_3_RDATA_31_0] =     0x0CD4,
> +       [PMIF_SWINF_3_VLD_CLR] =        0x0CE4,
> +       [PMIF_SWINF_3_STA] =    0x0CE8,
> +};
> +
> +enum spmi_regs {
> +       SPMI_OP_ST_CTRL,
> +       SPMI_GRP_ID_EN,
> +       SPMI_OP_ST_STA,
> +       SPMI_MST_SAMPL,
> +       SPMI_MST_REQ_EN,
> +       SPMI_REC_CTRL,
> +       SPMI_REC0,
> +       SPMI_REC1,
> +       SPMI_REC2,
> +       SPMI_REC3,
> +       SPMI_REC4,
> +       SPMI_MST_DBG,
> +};
> +
> +static const u32 mt6873_spmi_regs[] = {

There's only one of these so far. Is there going to be a different
register layout in the future? If we can avoid the indirection it would
be ideal.

> +       [SPMI_OP_ST_CTRL] =     0x0000,
> +       [SPMI_GRP_ID_EN] =      0x0004,
> +       [SPMI_OP_ST_STA] =      0x0008,
> +       [SPMI_MST_SAMPL] =      0x000c,
> +       [SPMI_MST_REQ_EN] =     0x0010,
> +       [SPMI_REC_CTRL] =       0x0040,
> +       [SPMI_REC0] =           0x0044,
> +       [SPMI_REC1] =           0x0048,
> +       [SPMI_REC2] =           0x004c,
> +       [SPMI_REC3] =           0x0050,
> +       [SPMI_REC4] =           0x0054,
> +       [SPMI_MST_DBG] =        0x00fc,
> +};
> +
> +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
> +{
> +       return readl(arb->base + arb->data->regs[reg]);
> +}
> +
> +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
> +{
> +       writel(val, arb->base + arb->data->regs[reg]);
> +}
> +
> +static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
> +{
> +       writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
> +}
> +
> +static bool pmif_is_fsm_vldclr(struct pmif *arb)
> +{
> +       u32 reg_rdata;
> +
> +       reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
> +       return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
> +}
> +
> +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       u32 rdata, cmd;
> +       int ret;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> +               return -EINVAL;
> +       }
> +
> +       /* Check the opcode */
> +       if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
> +               return -EINVAL;
> +
> +       cmd = opc - SPMI_CMD_RESET;
> +
> +       mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
> +       ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
> +                                       rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0)
> +               dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
> +
> +       return ret;
> +}
> +
> +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> +                             u16 addr, u8 *buf, size_t len)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       struct ch_reg *inf_reg;
> +       int ret;
> +       u32 data, cmd;
> +       unsigned long flags;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> +               return -EINVAL;
> +       }
> +
> +       if (len > 4) {
> +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> +               return -EINVAL;
> +       }
> +
> +       if (opc >= 0x60 && opc <= 0x7f)
> +               opc = PMIF_CMD_REG;
> +       else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
> +               opc = PMIF_CMD_EXT_REG_LONG;
> +       else
> +               return -EINVAL;
> +
> +       raw_spin_lock_irqsave(&arb->lock, flags);
> +
> +       /* Wait for Software Interface FSM state to be IDLE. */
> +       inf_reg = &arb->chan;
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_IDLE,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               /* set channel ready if the data has transferred */
> +               if (pmif_is_fsm_vldclr(arb))
> +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> +               goto out;
> +       }
> +
> +       /* Send the command. */
> +       cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
> +       pmif_writel(arb, cmd, inf_reg->ch_send);
> +
> +       /*
> +        * Wait for Software Interface FSM state to be WFVLDCLR,
> +        * read the data and clear the valid flag.
> +        */
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_WFVLDCLR,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
> +               goto out;
> +       }
> +
> +       data = pmif_readl(arb, inf_reg->rdata);
> +       memcpy(buf, &data, len);
> +       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +
> +out:
> +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> +       if (ret < 0)
> +               return ret;
> +
> +       return 0;
> +}
> +
> +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> +                              u16 addr, const u8 *buf, size_t len)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       struct ch_reg *inf_reg;
> +       int ret;
> +       u32 data, cmd;
> +       unsigned long flags;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");

Feels like something we should push up into the core framework instead
of having each driver figure out.

> +               return -EINVAL;
> +       }
> +
> +       if (len > 4) {
> +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);

Feels like something we should push up into the core framework instead
of having each driver figure out.

> +               return -EINVAL;
> +       }
> +
> +       /* Check the opcode */
> +       if (opc >= 0x40 && opc <= 0x5F)
> +               opc = PMIF_CMD_REG;
> +       else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
> +               opc = PMIF_CMD_EXT_REG_LONG;
> +       else if (opc >= 0x80)
> +               opc = PMIF_CMD_REG_0;
> +       else
> +               return -EINVAL;
> +
> +       raw_spin_lock_irqsave(&arb->lock, flags);
> +
> +       /* Wait for Software Interface FSM state to be IDLE. */
> +       inf_reg = &arb->chan;
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_IDLE,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               /* set channel ready if the data has transferred */
> +               if (pmif_is_fsm_vldclr(arb))
> +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> +               goto out;
> +       }
> +
> +       /* Set the write data. */
> +       memcpy(&data, buf, len);
> +       pmif_writel(arb, data, inf_reg->wdata);
> +
> +       /* Send the command. */
> +       cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
> +       pmif_writel(arb, cmd, inf_reg->ch_send);

What is BIT 29? Is that special somehow?

> +
> +out:
> +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> +       if (ret < 0)
> +               return ret;
> +
> +       return 0;
> +}
> +

Re: [PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Stephen Boyd]

Quoting Hsin-Hsiung Wang (2021-02-06 21:19:13)
> diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
> index a53bad541f1a..418848840999 100644
> --- a/drivers/spmi/Kconfig
> +++ b/drivers/spmi/Kconfig
> @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
>           This is required for communicating with Qualcomm PMICs and
>           other devices that have the SPMI interface.
>  
> +config SPMI_MTK_PMIF
> +       tristate "Mediatek SPMI Controller (PMIC Arbiter)"
> +       help
> +         If you say yes to this option, support will be included for the
> +         built-in SPMI PMIC Arbiter interface on Mediatek family
> +         processors.
> +
> +         This is required for communicating with Mediatek PMICs and
> +         other devices that have the SPMI interface.

Preferably add another newline here to unstick the 'endif'

>  endif
> diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
> new file mode 100644
> index 000000000000..4ac4643f89f3
> --- /dev/null
> +++ b/drivers/spmi/spmi-mtk-pmif.c
> @@ -0,0 +1,488 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +
> +#include <linux/clk.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/spmi.h>
> +
> +#define SWINF_IDLE     0x00
> +#define SWINF_WFVLDCLR 0x06
> +
> +#define GET_SWINF(x)   (((x) >> 1) & 0x7)
> +
> +#define PMIF_CMD_REG_0         0
> +#define PMIF_CMD_REG           1
> +#define PMIF_CMD_EXT_REG       2
> +#define PMIF_CMD_EXT_REG_LONG  3
> +
> +#define PMIF_DELAY_US   10
> +#define PMIF_TIMEOUT_US (10 * 1000)
> +
> +#define PMIF_CHAN_OFFSET 0x5
> +
> +#define PMIF_MAX_CLKS  3
> +
> +#define SPMI_OP_ST_BUSY 1
> +
> +struct ch_reg {
> +       u32 ch_sta;
> +       u32 wdata;
> +       u32 rdata;
> +       u32 ch_send;
> +       u32 ch_rdy;
> +};
> +
> +struct pmif_data {
> +       const u32       *regs;
> +       const u32       *spmimst_regs;
> +       u32     soc_chan;

Is this used?

> +};
> +
> +struct pmif {
> +       void __iomem    *base;
> +       void __iomem    *spmimst_base;
> +       raw_spinlock_t  lock;

Why is the spinlock raw? Is it used in hard irq handling?

> +       struct ch_reg   chan;
> +       struct clk_bulk_data clks[PMIF_MAX_CLKS];
> +       u32 nclks;
> +       const struct pmif_data *data;
> +};
> +
> +static const char * const pmif_clock_names[] = {
> +       "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
> +};
> +
> +enum pmif_regs {
> +       PMIF_INIT_DONE,
> +       PMIF_INF_EN,
> +       PMIF_ARB_EN,
> +       PMIF_CMDISSUE_EN,
> +       PMIF_TIMER_CTRL,
> +       PMIF_SPI_MODE_CTRL,
> +       PMIF_IRQ_EVENT_EN_0,
> +       PMIF_IRQ_FLAG_0,
> +       PMIF_IRQ_CLR_0,
> +       PMIF_IRQ_EVENT_EN_1,
> +       PMIF_IRQ_FLAG_1,
> +       PMIF_IRQ_CLR_1,
> +       PMIF_IRQ_EVENT_EN_2,
> +       PMIF_IRQ_FLAG_2,
> +       PMIF_IRQ_CLR_2,
> +       PMIF_IRQ_EVENT_EN_3,
> +       PMIF_IRQ_FLAG_3,
> +       PMIF_IRQ_CLR_3,
> +       PMIF_IRQ_EVENT_EN_4,
> +       PMIF_IRQ_FLAG_4,
> +       PMIF_IRQ_CLR_4,
> +       PMIF_WDT_EVENT_EN_0,
> +       PMIF_WDT_FLAG_0,
> +       PMIF_WDT_EVENT_EN_1,
> +       PMIF_WDT_FLAG_1,
> +       PMIF_SWINF_0_STA,
> +       PMIF_SWINF_0_WDATA_31_0,
> +       PMIF_SWINF_0_RDATA_31_0,
> +       PMIF_SWINF_0_ACC,
> +       PMIF_SWINF_0_VLD_CLR,
> +       PMIF_SWINF_1_STA,
> +       PMIF_SWINF_1_WDATA_31_0,
> +       PMIF_SWINF_1_RDATA_31_0,
> +       PMIF_SWINF_1_ACC,
> +       PMIF_SWINF_1_VLD_CLR,
> +       PMIF_SWINF_2_STA,
> +       PMIF_SWINF_2_WDATA_31_0,
> +       PMIF_SWINF_2_RDATA_31_0,
> +       PMIF_SWINF_2_ACC,
> +       PMIF_SWINF_2_VLD_CLR,
> +       PMIF_SWINF_3_STA,
> +       PMIF_SWINF_3_WDATA_31_0,
> +       PMIF_SWINF_3_RDATA_31_0,
> +       PMIF_SWINF_3_ACC,
> +       PMIF_SWINF_3_VLD_CLR,
> +};
> +
> +static const u32 mt6873_regs[] = {
> +       [PMIF_INIT_DONE] =      0x0000,
> +       [PMIF_INF_EN] =         0x0024,
> +       [PMIF_ARB_EN] =         0x0150,
> +       [PMIF_CMDISSUE_EN] =    0x03B4,
> +       [PMIF_TIMER_CTRL] =     0x03E0,
> +       [PMIF_SPI_MODE_CTRL] =  0x0400,
> +       [PMIF_IRQ_EVENT_EN_0] = 0x0418,
> +       [PMIF_IRQ_FLAG_0] =     0x0420,
> +       [PMIF_IRQ_CLR_0] =      0x0424,
> +       [PMIF_IRQ_EVENT_EN_1] = 0x0428,
> +       [PMIF_IRQ_FLAG_1] =     0x0430,
> +       [PMIF_IRQ_CLR_1] =      0x0434,
> +       [PMIF_IRQ_EVENT_EN_2] = 0x0438,
> +       [PMIF_IRQ_FLAG_2] =     0x0440,
> +       [PMIF_IRQ_CLR_2] =      0x0444,
> +       [PMIF_IRQ_EVENT_EN_3] = 0x0448,
> +       [PMIF_IRQ_FLAG_3] =     0x0450,
> +       [PMIF_IRQ_CLR_3] =      0x0454,
> +       [PMIF_IRQ_EVENT_EN_4] = 0x0458,
> +       [PMIF_IRQ_FLAG_4] =     0x0460,
> +       [PMIF_IRQ_CLR_4] =      0x0464,
> +       [PMIF_WDT_EVENT_EN_0] = 0x046C,
> +       [PMIF_WDT_FLAG_0] =     0x0470,
> +       [PMIF_WDT_EVENT_EN_1] = 0x0474,
> +       [PMIF_WDT_FLAG_1] =     0x0478,
> +       [PMIF_SWINF_0_ACC] =    0x0C00,
> +       [PMIF_SWINF_0_WDATA_31_0] =     0x0C04,
> +       [PMIF_SWINF_0_RDATA_31_0] =     0x0C14,
> +       [PMIF_SWINF_0_VLD_CLR] =        0x0C24,
> +       [PMIF_SWINF_0_STA] =    0x0C28,
> +       [PMIF_SWINF_1_ACC] =    0x0C40,
> +       [PMIF_SWINF_1_WDATA_31_0] =     0x0C44,
> +       [PMIF_SWINF_1_RDATA_31_0] =     0x0C54,
> +       [PMIF_SWINF_1_VLD_CLR] =        0x0C64,
> +       [PMIF_SWINF_1_STA] =    0x0C68,
> +       [PMIF_SWINF_2_ACC] =    0x0C80,
> +       [PMIF_SWINF_2_WDATA_31_0] =     0x0C84,
> +       [PMIF_SWINF_2_RDATA_31_0] =     0x0C94,
> +       [PMIF_SWINF_2_VLD_CLR] =        0x0CA4,
> +       [PMIF_SWINF_2_STA] =    0x0CA8,
> +       [PMIF_SWINF_3_ACC] =    0x0CC0,
> +       [PMIF_SWINF_3_WDATA_31_0] =     0x0CC4,
> +       [PMIF_SWINF_3_RDATA_31_0] =     0x0CD4,
> +       [PMIF_SWINF_3_VLD_CLR] =        0x0CE4,
> +       [PMIF_SWINF_3_STA] =    0x0CE8,
> +};
> +
> +enum spmi_regs {
> +       SPMI_OP_ST_CTRL,
> +       SPMI_GRP_ID_EN,
> +       SPMI_OP_ST_STA,
> +       SPMI_MST_SAMPL,
> +       SPMI_MST_REQ_EN,
> +       SPMI_REC_CTRL,
> +       SPMI_REC0,
> +       SPMI_REC1,
> +       SPMI_REC2,
> +       SPMI_REC3,
> +       SPMI_REC4,
> +       SPMI_MST_DBG,
> +};
> +
> +static const u32 mt6873_spmi_regs[] = {

There's only one of these so far. Is there going to be a different
register layout in the future? If we can avoid the indirection it would
be ideal.

> +       [SPMI_OP_ST_CTRL] =     0x0000,
> +       [SPMI_GRP_ID_EN] =      0x0004,
> +       [SPMI_OP_ST_STA] =      0x0008,
> +       [SPMI_MST_SAMPL] =      0x000c,
> +       [SPMI_MST_REQ_EN] =     0x0010,
> +       [SPMI_REC_CTRL] =       0x0040,
> +       [SPMI_REC0] =           0x0044,
> +       [SPMI_REC1] =           0x0048,
> +       [SPMI_REC2] =           0x004c,
> +       [SPMI_REC3] =           0x0050,
> +       [SPMI_REC4] =           0x0054,
> +       [SPMI_MST_DBG] =        0x00fc,
> +};
> +
> +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
> +{
> +       return readl(arb->base + arb->data->regs[reg]);
> +}
> +
> +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
> +{
> +       writel(val, arb->base + arb->data->regs[reg]);
> +}
> +
> +static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
> +{
> +       writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
> +}
> +
> +static bool pmif_is_fsm_vldclr(struct pmif *arb)
> +{
> +       u32 reg_rdata;
> +
> +       reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
> +       return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
> +}
> +
> +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       u32 rdata, cmd;
> +       int ret;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> +               return -EINVAL;
> +       }
> +
> +       /* Check the opcode */
> +       if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
> +               return -EINVAL;
> +
> +       cmd = opc - SPMI_CMD_RESET;
> +
> +       mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
> +       ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
> +                                       rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0)
> +               dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
> +
> +       return ret;
> +}
> +
> +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> +                             u16 addr, u8 *buf, size_t len)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       struct ch_reg *inf_reg;
> +       int ret;
> +       u32 data, cmd;
> +       unsigned long flags;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> +               return -EINVAL;
> +       }
> +
> +       if (len > 4) {
> +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> +               return -EINVAL;
> +       }
> +
> +       if (opc >= 0x60 && opc <= 0x7f)
> +               opc = PMIF_CMD_REG;
> +       else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
> +               opc = PMIF_CMD_EXT_REG_LONG;
> +       else
> +               return -EINVAL;
> +
> +       raw_spin_lock_irqsave(&arb->lock, flags);
> +
> +       /* Wait for Software Interface FSM state to be IDLE. */
> +       inf_reg = &arb->chan;
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_IDLE,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               /* set channel ready if the data has transferred */
> +               if (pmif_is_fsm_vldclr(arb))
> +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> +               goto out;
> +       }
> +
> +       /* Send the command. */
> +       cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
> +       pmif_writel(arb, cmd, inf_reg->ch_send);
> +
> +       /*
> +        * Wait for Software Interface FSM state to be WFVLDCLR,
> +        * read the data and clear the valid flag.
> +        */
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_WFVLDCLR,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
> +               goto out;
> +       }
> +
> +       data = pmif_readl(arb, inf_reg->rdata);
> +       memcpy(buf, &data, len);
> +       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +
> +out:
> +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> +       if (ret < 0)
> +               return ret;
> +
> +       return 0;
> +}
> +
> +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> +                              u16 addr, const u8 *buf, size_t len)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       struct ch_reg *inf_reg;
> +       int ret;
> +       u32 data, cmd;
> +       unsigned long flags;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");

Feels like something we should push up into the core framework instead
of having each driver figure out.

> +               return -EINVAL;
> +       }
> +
> +       if (len > 4) {
> +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);

Feels like something we should push up into the core framework instead
of having each driver figure out.

> +               return -EINVAL;
> +       }
> +
> +       /* Check the opcode */
> +       if (opc >= 0x40 && opc <= 0x5F)
> +               opc = PMIF_CMD_REG;
> +       else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
> +               opc = PMIF_CMD_EXT_REG_LONG;
> +       else if (opc >= 0x80)
> +               opc = PMIF_CMD_REG_0;
> +       else
> +               return -EINVAL;
> +
> +       raw_spin_lock_irqsave(&arb->lock, flags);
> +
> +       /* Wait for Software Interface FSM state to be IDLE. */
> +       inf_reg = &arb->chan;
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_IDLE,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               /* set channel ready if the data has transferred */
> +               if (pmif_is_fsm_vldclr(arb))
> +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> +               goto out;
> +       }
> +
> +       /* Set the write data. */
> +       memcpy(&data, buf, len);
> +       pmif_writel(arb, data, inf_reg->wdata);
> +
> +       /* Send the command. */
> +       cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
> +       pmif_writel(arb, cmd, inf_reg->ch_send);

What is BIT 29? Is that special somehow?

> +
> +out:
> +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> +       if (ret < 0)
> +               return ret;
> +
> +       return 0;
> +}
> +

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Re: [PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Stephen Boyd]

Quoting Hsin-Hsiung Wang (2021-02-06 21:19:13)
> diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
> index a53bad541f1a..418848840999 100644
> --- a/drivers/spmi/Kconfig
> +++ b/drivers/spmi/Kconfig
> @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
>           This is required for communicating with Qualcomm PMICs and
>           other devices that have the SPMI interface.
>  
> +config SPMI_MTK_PMIF
> +       tristate "Mediatek SPMI Controller (PMIC Arbiter)"
> +       help
> +         If you say yes to this option, support will be included for the
> +         built-in SPMI PMIC Arbiter interface on Mediatek family
> +         processors.
> +
> +         This is required for communicating with Mediatek PMICs and
> +         other devices that have the SPMI interface.

Preferably add another newline here to unstick the 'endif'

>  endif
> diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
> new file mode 100644
> index 000000000000..4ac4643f89f3
> --- /dev/null
> +++ b/drivers/spmi/spmi-mtk-pmif.c
> @@ -0,0 +1,488 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +
> +#include <linux/clk.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/spmi.h>
> +
> +#define SWINF_IDLE     0x00
> +#define SWINF_WFVLDCLR 0x06
> +
> +#define GET_SWINF(x)   (((x) >> 1) & 0x7)
> +
> +#define PMIF_CMD_REG_0         0
> +#define PMIF_CMD_REG           1
> +#define PMIF_CMD_EXT_REG       2
> +#define PMIF_CMD_EXT_REG_LONG  3
> +
> +#define PMIF_DELAY_US   10
> +#define PMIF_TIMEOUT_US (10 * 1000)
> +
> +#define PMIF_CHAN_OFFSET 0x5
> +
> +#define PMIF_MAX_CLKS  3
> +
> +#define SPMI_OP_ST_BUSY 1
> +
> +struct ch_reg {
> +       u32 ch_sta;
> +       u32 wdata;
> +       u32 rdata;
> +       u32 ch_send;
> +       u32 ch_rdy;
> +};
> +
> +struct pmif_data {
> +       const u32       *regs;
> +       const u32       *spmimst_regs;
> +       u32     soc_chan;

Is this used?

> +};
> +
> +struct pmif {
> +       void __iomem    *base;
> +       void __iomem    *spmimst_base;
> +       raw_spinlock_t  lock;

Why is the spinlock raw? Is it used in hard irq handling?

> +       struct ch_reg   chan;
> +       struct clk_bulk_data clks[PMIF_MAX_CLKS];
> +       u32 nclks;
> +       const struct pmif_data *data;
> +};
> +
> +static const char * const pmif_clock_names[] = {
> +       "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
> +};
> +
> +enum pmif_regs {
> +       PMIF_INIT_DONE,
> +       PMIF_INF_EN,
> +       PMIF_ARB_EN,
> +       PMIF_CMDISSUE_EN,
> +       PMIF_TIMER_CTRL,
> +       PMIF_SPI_MODE_CTRL,
> +       PMIF_IRQ_EVENT_EN_0,
> +       PMIF_IRQ_FLAG_0,
> +       PMIF_IRQ_CLR_0,
> +       PMIF_IRQ_EVENT_EN_1,
> +       PMIF_IRQ_FLAG_1,
> +       PMIF_IRQ_CLR_1,
> +       PMIF_IRQ_EVENT_EN_2,
> +       PMIF_IRQ_FLAG_2,
> +       PMIF_IRQ_CLR_2,
> +       PMIF_IRQ_EVENT_EN_3,
> +       PMIF_IRQ_FLAG_3,
> +       PMIF_IRQ_CLR_3,
> +       PMIF_IRQ_EVENT_EN_4,
> +       PMIF_IRQ_FLAG_4,
> +       PMIF_IRQ_CLR_4,
> +       PMIF_WDT_EVENT_EN_0,
> +       PMIF_WDT_FLAG_0,
> +       PMIF_WDT_EVENT_EN_1,
> +       PMIF_WDT_FLAG_1,
> +       PMIF_SWINF_0_STA,
> +       PMIF_SWINF_0_WDATA_31_0,
> +       PMIF_SWINF_0_RDATA_31_0,
> +       PMIF_SWINF_0_ACC,
> +       PMIF_SWINF_0_VLD_CLR,
> +       PMIF_SWINF_1_STA,
> +       PMIF_SWINF_1_WDATA_31_0,
> +       PMIF_SWINF_1_RDATA_31_0,
> +       PMIF_SWINF_1_ACC,
> +       PMIF_SWINF_1_VLD_CLR,
> +       PMIF_SWINF_2_STA,
> +       PMIF_SWINF_2_WDATA_31_0,
> +       PMIF_SWINF_2_RDATA_31_0,
> +       PMIF_SWINF_2_ACC,
> +       PMIF_SWINF_2_VLD_CLR,
> +       PMIF_SWINF_3_STA,
> +       PMIF_SWINF_3_WDATA_31_0,
> +       PMIF_SWINF_3_RDATA_31_0,
> +       PMIF_SWINF_3_ACC,
> +       PMIF_SWINF_3_VLD_CLR,
> +};
> +
> +static const u32 mt6873_regs[] = {
> +       [PMIF_INIT_DONE] =      0x0000,
> +       [PMIF_INF_EN] =         0x0024,
> +       [PMIF_ARB_EN] =         0x0150,
> +       [PMIF_CMDISSUE_EN] =    0x03B4,
> +       [PMIF_TIMER_CTRL] =     0x03E0,
> +       [PMIF_SPI_MODE_CTRL] =  0x0400,
> +       [PMIF_IRQ_EVENT_EN_0] = 0x0418,
> +       [PMIF_IRQ_FLAG_0] =     0x0420,
> +       [PMIF_IRQ_CLR_0] =      0x0424,
> +       [PMIF_IRQ_EVENT_EN_1] = 0x0428,
> +       [PMIF_IRQ_FLAG_1] =     0x0430,
> +       [PMIF_IRQ_CLR_1] =      0x0434,
> +       [PMIF_IRQ_EVENT_EN_2] = 0x0438,
> +       [PMIF_IRQ_FLAG_2] =     0x0440,
> +       [PMIF_IRQ_CLR_2] =      0x0444,
> +       [PMIF_IRQ_EVENT_EN_3] = 0x0448,
> +       [PMIF_IRQ_FLAG_3] =     0x0450,
> +       [PMIF_IRQ_CLR_3] =      0x0454,
> +       [PMIF_IRQ_EVENT_EN_4] = 0x0458,
> +       [PMIF_IRQ_FLAG_4] =     0x0460,
> +       [PMIF_IRQ_CLR_4] =      0x0464,
> +       [PMIF_WDT_EVENT_EN_0] = 0x046C,
> +       [PMIF_WDT_FLAG_0] =     0x0470,
> +       [PMIF_WDT_EVENT_EN_1] = 0x0474,
> +       [PMIF_WDT_FLAG_1] =     0x0478,
> +       [PMIF_SWINF_0_ACC] =    0x0C00,
> +       [PMIF_SWINF_0_WDATA_31_0] =     0x0C04,
> +       [PMIF_SWINF_0_RDATA_31_0] =     0x0C14,
> +       [PMIF_SWINF_0_VLD_CLR] =        0x0C24,
> +       [PMIF_SWINF_0_STA] =    0x0C28,
> +       [PMIF_SWINF_1_ACC] =    0x0C40,
> +       [PMIF_SWINF_1_WDATA_31_0] =     0x0C44,
> +       [PMIF_SWINF_1_RDATA_31_0] =     0x0C54,
> +       [PMIF_SWINF_1_VLD_CLR] =        0x0C64,
> +       [PMIF_SWINF_1_STA] =    0x0C68,
> +       [PMIF_SWINF_2_ACC] =    0x0C80,
> +       [PMIF_SWINF_2_WDATA_31_0] =     0x0C84,
> +       [PMIF_SWINF_2_RDATA_31_0] =     0x0C94,
> +       [PMIF_SWINF_2_VLD_CLR] =        0x0CA4,
> +       [PMIF_SWINF_2_STA] =    0x0CA8,
> +       [PMIF_SWINF_3_ACC] =    0x0CC0,
> +       [PMIF_SWINF_3_WDATA_31_0] =     0x0CC4,
> +       [PMIF_SWINF_3_RDATA_31_0] =     0x0CD4,
> +       [PMIF_SWINF_3_VLD_CLR] =        0x0CE4,
> +       [PMIF_SWINF_3_STA] =    0x0CE8,
> +};
> +
> +enum spmi_regs {
> +       SPMI_OP_ST_CTRL,
> +       SPMI_GRP_ID_EN,
> +       SPMI_OP_ST_STA,
> +       SPMI_MST_SAMPL,
> +       SPMI_MST_REQ_EN,
> +       SPMI_REC_CTRL,
> +       SPMI_REC0,
> +       SPMI_REC1,
> +       SPMI_REC2,
> +       SPMI_REC3,
> +       SPMI_REC4,
> +       SPMI_MST_DBG,
> +};
> +
> +static const u32 mt6873_spmi_regs[] = {

There's only one of these so far. Is there going to be a different
register layout in the future? If we can avoid the indirection it would
be ideal.

> +       [SPMI_OP_ST_CTRL] =     0x0000,
> +       [SPMI_GRP_ID_EN] =      0x0004,
> +       [SPMI_OP_ST_STA] =      0x0008,
> +       [SPMI_MST_SAMPL] =      0x000c,
> +       [SPMI_MST_REQ_EN] =     0x0010,
> +       [SPMI_REC_CTRL] =       0x0040,
> +       [SPMI_REC0] =           0x0044,
> +       [SPMI_REC1] =           0x0048,
> +       [SPMI_REC2] =           0x004c,
> +       [SPMI_REC3] =           0x0050,
> +       [SPMI_REC4] =           0x0054,
> +       [SPMI_MST_DBG] =        0x00fc,
> +};
> +
> +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
> +{
> +       return readl(arb->base + arb->data->regs[reg]);
> +}
> +
> +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
> +{
> +       writel(val, arb->base + arb->data->regs[reg]);
> +}
> +
> +static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
> +{
> +       writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
> +}
> +
> +static bool pmif_is_fsm_vldclr(struct pmif *arb)
> +{
> +       u32 reg_rdata;
> +
> +       reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
> +       return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
> +}
> +
> +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       u32 rdata, cmd;
> +       int ret;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> +               return -EINVAL;
> +       }
> +
> +       /* Check the opcode */
> +       if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
> +               return -EINVAL;
> +
> +       cmd = opc - SPMI_CMD_RESET;
> +
> +       mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
> +       ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
> +                                       rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0)
> +               dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
> +
> +       return ret;
> +}
> +
> +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> +                             u16 addr, u8 *buf, size_t len)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       struct ch_reg *inf_reg;
> +       int ret;
> +       u32 data, cmd;
> +       unsigned long flags;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> +               return -EINVAL;
> +       }
> +
> +       if (len > 4) {
> +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> +               return -EINVAL;
> +       }
> +
> +       if (opc >= 0x60 && opc <= 0x7f)
> +               opc = PMIF_CMD_REG;
> +       else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
> +               opc = PMIF_CMD_EXT_REG_LONG;
> +       else
> +               return -EINVAL;
> +
> +       raw_spin_lock_irqsave(&arb->lock, flags);
> +
> +       /* Wait for Software Interface FSM state to be IDLE. */
> +       inf_reg = &arb->chan;
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_IDLE,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               /* set channel ready if the data has transferred */
> +               if (pmif_is_fsm_vldclr(arb))
> +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> +               goto out;
> +       }
> +
> +       /* Send the command. */
> +       cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
> +       pmif_writel(arb, cmd, inf_reg->ch_send);
> +
> +       /*
> +        * Wait for Software Interface FSM state to be WFVLDCLR,
> +        * read the data and clear the valid flag.
> +        */
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_WFVLDCLR,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
> +               goto out;
> +       }
> +
> +       data = pmif_readl(arb, inf_reg->rdata);
> +       memcpy(buf, &data, len);
> +       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +
> +out:
> +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> +       if (ret < 0)
> +               return ret;
> +
> +       return 0;
> +}
> +
> +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> +                              u16 addr, const u8 *buf, size_t len)
> +{
> +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> +       struct ch_reg *inf_reg;
> +       int ret;
> +       u32 data, cmd;
> +       unsigned long flags;
> +
> +       /* Check for argument validation. */
> +       if (sid & ~0xf) {
> +               dev_err(&ctrl->dev, "exceed the max slv id\n");

Feels like something we should push up into the core framework instead
of having each driver figure out.

> +               return -EINVAL;
> +       }
> +
> +       if (len > 4) {
> +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);

Feels like something we should push up into the core framework instead
of having each driver figure out.

> +               return -EINVAL;
> +       }
> +
> +       /* Check the opcode */
> +       if (opc >= 0x40 && opc <= 0x5F)
> +               opc = PMIF_CMD_REG;
> +       else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
> +               opc = PMIF_CMD_EXT_REG_LONG;
> +       else if (opc >= 0x80)
> +               opc = PMIF_CMD_REG_0;
> +       else
> +               return -EINVAL;
> +
> +       raw_spin_lock_irqsave(&arb->lock, flags);
> +
> +       /* Wait for Software Interface FSM state to be IDLE. */
> +       inf_reg = &arb->chan;
> +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> +                                       data, GET_SWINF(data) == SWINF_IDLE,
> +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> +       if (ret < 0) {
> +               /* set channel ready if the data has transferred */
> +               if (pmif_is_fsm_vldclr(arb))
> +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> +               goto out;
> +       }
> +
> +       /* Set the write data. */
> +       memcpy(&data, buf, len);
> +       pmif_writel(arb, data, inf_reg->wdata);
> +
> +       /* Send the command. */
> +       cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
> +       pmif_writel(arb, cmd, inf_reg->ch_send);

What is BIT 29? Is that special somehow?

> +
> +out:
> +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> +       if (ret < 0)
> +               return ret;
> +
> +       return 0;
> +}
> +

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Re: [PATCH v6 1/4] dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'

[Rob Herring]

On Sun, 07 Feb 2021 13:19:11 +0800, Hsin-Hsiung Wang wrote:
> The constraint of 'maxItem: 1' might be larger than 1, so we modify it
> to 'minItem: 1'.
> 
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> changes since v5:
> - update the constraint of minItem to 1.
> ---
>  Documentation/devicetree/bindings/spmi/spmi.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v6 1/4] dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'

[Rob Herring]

On Sun, 07 Feb 2021 13:19:11 +0800, Hsin-Hsiung Wang wrote:
> The constraint of 'maxItem: 1' might be larger than 1, so we modify it
> to 'minItem: 1'.
> 
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> changes since v5:
> - update the constraint of minItem to 1.
> ---
>  Documentation/devicetree/bindings/spmi/spmi.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v6 1/4] dt-bindings: spmi: modify the constraint 'maxItems' to 'minItems'

[Rob Herring]

On Sun, 07 Feb 2021 13:19:11 +0800, Hsin-Hsiung Wang wrote:
> The constraint of 'maxItem: 1' might be larger than 1, so we modify it
> to 'minItem: 1'.
> 
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
> changes since v5:
> - update the constraint of minItem to 1.
> ---
>  Documentation/devicetree/bindings/spmi/spmi.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v6 4/4] arm64: dts: mt8192: add spmi node

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1743 bytes --]

Hi Hsin-Hsiung,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.11 next-20210215]
[cannot apply to mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r016-20210215 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/19ac525591748a952c6e6f536a12aeb6dd28193a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
        git checkout 19ac525591748a952c6e6f536a12aeb6dd28193a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/mediatek/mt8192.dtsi:255.24-25 syntax error
>> FATAL ERROR: Unable to parse input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 29563 bytes --]

Re: [PATCH v6 4/4] arm64: dts: mt8192: add spmi node

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1743 bytes --]

Hi Hsin-Hsiung,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.11 next-20210215]
[cannot apply to mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r016-20210215 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/19ac525591748a952c6e6f536a12aeb6dd28193a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
        git checkout 19ac525591748a952c6e6f536a12aeb6dd28193a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/mediatek/mt8192.dtsi:255.24-25 syntax error
>> FATAL ERROR: Unable to parse input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 29563 bytes --]

[-- Attachment #3: Type: text/plain, Size: 170 bytes --]

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v6 4/4] arm64: dts: mt8192: add spmi node

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1743 bytes --]

Hi Hsin-Hsiung,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.11 next-20210215]
[cannot apply to mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r016-20210215 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/19ac525591748a952c6e6f536a12aeb6dd28193a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
        git checkout 19ac525591748a952c6e6f536a12aeb6dd28193a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/mediatek/mt8192.dtsi:255.24-25 syntax error
>> FATAL ERROR: Unable to parse input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 29563 bytes --]

[-- Attachment #3: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v6 4/4] arm64: dts: mt8192: add spmi node

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1781 bytes --]

Hi Hsin-Hsiung,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.11 next-20210215]
[cannot apply to mediatek/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r016-20210215 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/19ac525591748a952c6e6f536a12aeb6dd28193a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Hsin-Hsiung-Wang/Add-SPMI-support-for-Mediatek-MT6873-8192-SoC-IC/20210207-132428
        git checkout 19ac525591748a952c6e6f536a12aeb6dd28193a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/mediatek/mt8192.dtsi:255.24-25 syntax error
>> FATAL ERROR: Unable to parse input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 29563 bytes --]

Re: [PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Hsin-hsiung Wang]

Hi,

On Mon, 2021-02-08 at 14:21 -0800, Stephen Boyd wrote:
> Quoting Hsin-Hsiung Wang (2021-02-06 21:19:13)
> > diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
> > index a53bad541f1a..418848840999 100644
> > --- a/drivers/spmi/Kconfig
> > +++ b/drivers/spmi/Kconfig
> > @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
> >           This is required for communicating with Qualcomm PMICs and
> >           other devices that have the SPMI interface.
> >  
> > +config SPMI_MTK_PMIF
> > +       tristate "Mediatek SPMI Controller (PMIC Arbiter)"
> > +       help
> > +         If you say yes to this option, support will be included for the
> > +         built-in SPMI PMIC Arbiter interface on Mediatek family
> > +         processors.
> > +
> > +         This is required for communicating with Mediatek PMICs and
> > +         other devices that have the SPMI interface.
> 
> Preferably add another newline here to unstick the 'endif'
> 

Thanks. I will update it in the next patch.

> >  endif
> > diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
> > new file mode 100644
> > index 000000000000..4ac4643f89f3
> > --- /dev/null
> > +++ b/drivers/spmi/spmi-mtk-pmif.c
> > @@ -0,0 +1,488 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2021 MediaTek Inc.
> > +
> > +#include <linux/clk.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/spmi.h>
> > +
> > +#define SWINF_IDLE     0x00
> > +#define SWINF_WFVLDCLR 0x06
> > +
> > +#define GET_SWINF(x)   (((x) >> 1) & 0x7)
> > +
> > +#define PMIF_CMD_REG_0         0
> > +#define PMIF_CMD_REG           1
> > +#define PMIF_CMD_EXT_REG       2
> > +#define PMIF_CMD_EXT_REG_LONG  3
> > +
> > +#define PMIF_DELAY_US   10
> > +#define PMIF_TIMEOUT_US (10 * 1000)
> > +
> > +#define PMIF_CHAN_OFFSET 0x5
> > +
> > +#define PMIF_MAX_CLKS  3
> > +
> > +#define SPMI_OP_ST_BUSY 1
> > +
> > +struct ch_reg {
> > +       u32 ch_sta;
> > +       u32 wdata;
> > +       u32 rdata;
> > +       u32 ch_send;
> > +       u32 ch_rdy;
> > +};
> > +
> > +struct pmif_data {
> > +       const u32       *regs;
> > +       const u32       *spmimst_regs;
> > +       u32     soc_chan;
> 
> Is this used?
> 

Yes.

> > +};
> > +
> > +struct pmif {
> > +       void __iomem    *base;
> > +       void __iomem    *spmimst_base;
> > +       raw_spinlock_t  lock;
> 
> Why is the spinlock raw? Is it used in hard irq handling?
> 

Thanks for the comment. After reviewing the code, I will remove it and
update it in the next patch.

> > +       struct ch_reg   chan;
> > +       struct clk_bulk_data clks[PMIF_MAX_CLKS];
> > +       u32 nclks;
> > +       const struct pmif_data *data;
> > +};
> > +
> > +static const char * const pmif_clock_names[] = {
> > +       "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
> > +};
> > +
> > +enum pmif_regs {
> > +       PMIF_INIT_DONE,
> > +       PMIF_INF_EN,
> > +       PMIF_ARB_EN,
> > +       PMIF_CMDISSUE_EN,
> > +       PMIF_TIMER_CTRL,
> > +       PMIF_SPI_MODE_CTRL,
> > +       PMIF_IRQ_EVENT_EN_0,
> > +       PMIF_IRQ_FLAG_0,
> > +       PMIF_IRQ_CLR_0,
> > +       PMIF_IRQ_EVENT_EN_1,
> > +       PMIF_IRQ_FLAG_1,
> > +       PMIF_IRQ_CLR_1,
> > +       PMIF_IRQ_EVENT_EN_2,
> > +       PMIF_IRQ_FLAG_2,
> > +       PMIF_IRQ_CLR_2,
> > +       PMIF_IRQ_EVENT_EN_3,
> > +       PMIF_IRQ_FLAG_3,
> > +       PMIF_IRQ_CLR_3,
> > +       PMIF_IRQ_EVENT_EN_4,
> > +       PMIF_IRQ_FLAG_4,
> > +       PMIF_IRQ_CLR_4,
> > +       PMIF_WDT_EVENT_EN_0,
> > +       PMIF_WDT_FLAG_0,
> > +       PMIF_WDT_EVENT_EN_1,
> > +       PMIF_WDT_FLAG_1,
> > +       PMIF_SWINF_0_STA,
> > +       PMIF_SWINF_0_WDATA_31_0,
> > +       PMIF_SWINF_0_RDATA_31_0,
> > +       PMIF_SWINF_0_ACC,
> > +       PMIF_SWINF_0_VLD_CLR,
> > +       PMIF_SWINF_1_STA,
> > +       PMIF_SWINF_1_WDATA_31_0,
> > +       PMIF_SWINF_1_RDATA_31_0,
> > +       PMIF_SWINF_1_ACC,
> > +       PMIF_SWINF_1_VLD_CLR,
> > +       PMIF_SWINF_2_STA,
> > +       PMIF_SWINF_2_WDATA_31_0,
> > +       PMIF_SWINF_2_RDATA_31_0,
> > +       PMIF_SWINF_2_ACC,
> > +       PMIF_SWINF_2_VLD_CLR,
> > +       PMIF_SWINF_3_STA,
> > +       PMIF_SWINF_3_WDATA_31_0,
> > +       PMIF_SWINF_3_RDATA_31_0,
> > +       PMIF_SWINF_3_ACC,
> > +       PMIF_SWINF_3_VLD_CLR,
> > +};
> > +
> > +static const u32 mt6873_regs[] = {
> > +       [PMIF_INIT_DONE] =      0x0000,
> > +       [PMIF_INF_EN] =         0x0024,
> > +       [PMIF_ARB_EN] =         0x0150,
> > +       [PMIF_CMDISSUE_EN] =    0x03B4,
> > +       [PMIF_TIMER_CTRL] =     0x03E0,
> > +       [PMIF_SPI_MODE_CTRL] =  0x0400,
> > +       [PMIF_IRQ_EVENT_EN_0] = 0x0418,
> > +       [PMIF_IRQ_FLAG_0] =     0x0420,
> > +       [PMIF_IRQ_CLR_0] =      0x0424,
> > +       [PMIF_IRQ_EVENT_EN_1] = 0x0428,
> > +       [PMIF_IRQ_FLAG_1] =     0x0430,
> > +       [PMIF_IRQ_CLR_1] =      0x0434,
> > +       [PMIF_IRQ_EVENT_EN_2] = 0x0438,
> > +       [PMIF_IRQ_FLAG_2] =     0x0440,
> > +       [PMIF_IRQ_CLR_2] =      0x0444,
> > +       [PMIF_IRQ_EVENT_EN_3] = 0x0448,
> > +       [PMIF_IRQ_FLAG_3] =     0x0450,
> > +       [PMIF_IRQ_CLR_3] =      0x0454,
> > +       [PMIF_IRQ_EVENT_EN_4] = 0x0458,
> > +       [PMIF_IRQ_FLAG_4] =     0x0460,
> > +       [PMIF_IRQ_CLR_4] =      0x0464,
> > +       [PMIF_WDT_EVENT_EN_0] = 0x046C,
> > +       [PMIF_WDT_FLAG_0] =     0x0470,
> > +       [PMIF_WDT_EVENT_EN_1] = 0x0474,
> > +       [PMIF_WDT_FLAG_1] =     0x0478,
> > +       [PMIF_SWINF_0_ACC] =    0x0C00,
> > +       [PMIF_SWINF_0_WDATA_31_0] =     0x0C04,
> > +       [PMIF_SWINF_0_RDATA_31_0] =     0x0C14,
> > +       [PMIF_SWINF_0_VLD_CLR] =        0x0C24,
> > +       [PMIF_SWINF_0_STA] =    0x0C28,
> > +       [PMIF_SWINF_1_ACC] =    0x0C40,
> > +       [PMIF_SWINF_1_WDATA_31_0] =     0x0C44,
> > +       [PMIF_SWINF_1_RDATA_31_0] =     0x0C54,
> > +       [PMIF_SWINF_1_VLD_CLR] =        0x0C64,
> > +       [PMIF_SWINF_1_STA] =    0x0C68,
> > +       [PMIF_SWINF_2_ACC] =    0x0C80,
> > +       [PMIF_SWINF_2_WDATA_31_0] =     0x0C84,
> > +       [PMIF_SWINF_2_RDATA_31_0] =     0x0C94,
> > +       [PMIF_SWINF_2_VLD_CLR] =        0x0CA4,
> > +       [PMIF_SWINF_2_STA] =    0x0CA8,
> > +       [PMIF_SWINF_3_ACC] =    0x0CC0,
> > +       [PMIF_SWINF_3_WDATA_31_0] =     0x0CC4,
> > +       [PMIF_SWINF_3_RDATA_31_0] =     0x0CD4,
> > +       [PMIF_SWINF_3_VLD_CLR] =        0x0CE4,
> > +       [PMIF_SWINF_3_STA] =    0x0CE8,
> > +};
> > +
> > +enum spmi_regs {
> > +       SPMI_OP_ST_CTRL,
> > +       SPMI_GRP_ID_EN,
> > +       SPMI_OP_ST_STA,
> > +       SPMI_MST_SAMPL,
> > +       SPMI_MST_REQ_EN,
> > +       SPMI_REC_CTRL,
> > +       SPMI_REC0,
> > +       SPMI_REC1,
> > +       SPMI_REC2,
> > +       SPMI_REC3,
> > +       SPMI_REC4,
> > +       SPMI_MST_DBG,
> > +};
> > +
> > +static const u32 mt6873_spmi_regs[] = {
> 
> There's only one of these so far. Is there going to be a different
> register layout in the future? If we can avoid the indirection it would
> be ideal.
> 

Yes, we have other chips with different registers for spmi driver in the
feature.

> > +       [SPMI_OP_ST_CTRL] =     0x0000,
> > +       [SPMI_GRP_ID_EN] =      0x0004,
> > +       [SPMI_OP_ST_STA] =      0x0008,
> > +       [SPMI_MST_SAMPL] =      0x000c,
> > +       [SPMI_MST_REQ_EN] =     0x0010,
> > +       [SPMI_REC_CTRL] =       0x0040,
> > +       [SPMI_REC0] =           0x0044,
> > +       [SPMI_REC1] =           0x0048,
> > +       [SPMI_REC2] =           0x004c,
> > +       [SPMI_REC3] =           0x0050,
> > +       [SPMI_REC4] =           0x0054,
> > +       [SPMI_MST_DBG] =        0x00fc,
> > +};
> > +
> > +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
> > +{
> > +       return readl(arb->base + arb->data->regs[reg]);
> > +}
> > +
> > +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
> > +{
> > +       writel(val, arb->base + arb->data->regs[reg]);
> > +}
> > +
> > +static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
> > +{
> > +       writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
> > +}
> > +
> > +static bool pmif_is_fsm_vldclr(struct pmif *arb)
> > +{
> > +       u32 reg_rdata;
> > +
> > +       reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
> > +       return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
> > +}
> > +
> > +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       u32 rdata, cmd;
> > +       int ret;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> > +               return -EINVAL;
> > +       }
> > +
> > +       /* Check the opcode */
> > +       if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
> > +               return -EINVAL;
> > +
> > +       cmd = opc - SPMI_CMD_RESET;
> > +
> > +       mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
> > +       ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
> > +                                       rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0)
> > +               dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
> > +
> > +       return ret;
> > +}
> > +
> > +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> > +                             u16 addr, u8 *buf, size_t len)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       struct ch_reg *inf_reg;
> > +       int ret;
> > +       u32 data, cmd;
> > +       unsigned long flags;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> > +               return -EINVAL;
> > +       }
> > +
> > +       if (len > 4) {
> > +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> > +               return -EINVAL;
> > +       }
> > +
> > +       if (opc >= 0x60 && opc <= 0x7f)
> > +               opc = PMIF_CMD_REG;
> > +       else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
> > +               opc = PMIF_CMD_EXT_REG_LONG;
> > +       else
> > +               return -EINVAL;
> > +
> > +       raw_spin_lock_irqsave(&arb->lock, flags);
> > +
> > +       /* Wait for Software Interface FSM state to be IDLE. */
> > +       inf_reg = &arb->chan;
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_IDLE,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               /* set channel ready if the data has transferred */
> > +               if (pmif_is_fsm_vldclr(arb))
> > +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> > +               goto out;
> > +       }
> > +
> > +       /* Send the command. */
> > +       cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
> > +       pmif_writel(arb, cmd, inf_reg->ch_send);
> > +
> > +       /*
> > +        * Wait for Software Interface FSM state to be WFVLDCLR,
> > +        * read the data and clear the valid flag.
> > +        */
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_WFVLDCLR,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
> > +               goto out;
> > +       }
> > +
> > +       data = pmif_readl(arb, inf_reg->rdata);
> > +       memcpy(buf, &data, len);
> > +       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +
> > +out:
> > +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +
> > +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> > +                              u16 addr, const u8 *buf, size_t len)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       struct ch_reg *inf_reg;
> > +       int ret;
> > +       u32 data, cmd;
> > +       unsigned long flags;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> 
> Feels like something we should push up into the core framework instead
> of having each driver figure out.
> 

Thanks for the review.
After checking the framework, it already has the same check, so I will remove it in the next patch.

> > +               return -EINVAL;
> > +       }
> > +
> > +       if (len > 4) {
> > +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> 
> Feels like something we should push up into the core framework instead
> of having each driver figure out.
> 

Thanks for the comment, it's our hw design, not for common driver. 

> > +               return -EINVAL;
> > +       }
> > +
> > +       /* Check the opcode */
> > +       if (opc >= 0x40 && opc <= 0x5F)
> > +               opc = PMIF_CMD_REG;
> > +       else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
> > +               opc = PMIF_CMD_EXT_REG_LONG;
> > +       else if (opc >= 0x80)
> > +               opc = PMIF_CMD_REG_0;
> > +       else
> > +               return -EINVAL;
> > +
> > +       raw_spin_lock_irqsave(&arb->lock, flags);
> > +
> > +       /* Wait for Software Interface FSM state to be IDLE. */
> > +       inf_reg = &arb->chan;
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_IDLE,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               /* set channel ready if the data has transferred */
> > +               if (pmif_is_fsm_vldclr(arb))
> > +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> > +               goto out;
> > +       }
> > +
> > +       /* Set the write data. */
> > +       memcpy(&data, buf, len);
> > +       pmif_writel(arb, data, inf_reg->wdata);
> > +
> > +       /* Send the command. */
> > +       cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
> > +       pmif_writel(arb, cmd, inf_reg->ch_send);
> 
> What is BIT 29? Is that special somehow?
> 

Bit 29 means write or read cmd.
1 for write and 0 for read. 

> > +
> > +out:
> > +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +

Re: [PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Hsin-hsiung Wang]

Hi,

On Mon, 2021-02-08 at 14:21 -0800, Stephen Boyd wrote:
> Quoting Hsin-Hsiung Wang (2021-02-06 21:19:13)
> > diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
> > index a53bad541f1a..418848840999 100644
> > --- a/drivers/spmi/Kconfig
> > +++ b/drivers/spmi/Kconfig
> > @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
> >           This is required for communicating with Qualcomm PMICs and
> >           other devices that have the SPMI interface.
> >  
> > +config SPMI_MTK_PMIF
> > +       tristate "Mediatek SPMI Controller (PMIC Arbiter)"
> > +       help
> > +         If you say yes to this option, support will be included for the
> > +         built-in SPMI PMIC Arbiter interface on Mediatek family
> > +         processors.
> > +
> > +         This is required for communicating with Mediatek PMICs and
> > +         other devices that have the SPMI interface.
> 
> Preferably add another newline here to unstick the 'endif'
> 

Thanks. I will update it in the next patch.

> >  endif
> > diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
> > new file mode 100644
> > index 000000000000..4ac4643f89f3
> > --- /dev/null
> > +++ b/drivers/spmi/spmi-mtk-pmif.c
> > @@ -0,0 +1,488 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2021 MediaTek Inc.
> > +
> > +#include <linux/clk.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/spmi.h>
> > +
> > +#define SWINF_IDLE     0x00
> > +#define SWINF_WFVLDCLR 0x06
> > +
> > +#define GET_SWINF(x)   (((x) >> 1) & 0x7)
> > +
> > +#define PMIF_CMD_REG_0         0
> > +#define PMIF_CMD_REG           1
> > +#define PMIF_CMD_EXT_REG       2
> > +#define PMIF_CMD_EXT_REG_LONG  3
> > +
> > +#define PMIF_DELAY_US   10
> > +#define PMIF_TIMEOUT_US (10 * 1000)
> > +
> > +#define PMIF_CHAN_OFFSET 0x5
> > +
> > +#define PMIF_MAX_CLKS  3
> > +
> > +#define SPMI_OP_ST_BUSY 1
> > +
> > +struct ch_reg {
> > +       u32 ch_sta;
> > +       u32 wdata;
> > +       u32 rdata;
> > +       u32 ch_send;
> > +       u32 ch_rdy;
> > +};
> > +
> > +struct pmif_data {
> > +       const u32       *regs;
> > +       const u32       *spmimst_regs;
> > +       u32     soc_chan;
> 
> Is this used?
> 

Yes.

> > +};
> > +
> > +struct pmif {
> > +       void __iomem    *base;
> > +       void __iomem    *spmimst_base;
> > +       raw_spinlock_t  lock;
> 
> Why is the spinlock raw? Is it used in hard irq handling?
> 

Thanks for the comment. After reviewing the code, I will remove it and
update it in the next patch.

> > +       struct ch_reg   chan;
> > +       struct clk_bulk_data clks[PMIF_MAX_CLKS];
> > +       u32 nclks;
> > +       const struct pmif_data *data;
> > +};
> > +
> > +static const char * const pmif_clock_names[] = {
> > +       "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
> > +};
> > +
> > +enum pmif_regs {
> > +       PMIF_INIT_DONE,
> > +       PMIF_INF_EN,
> > +       PMIF_ARB_EN,
> > +       PMIF_CMDISSUE_EN,
> > +       PMIF_TIMER_CTRL,
> > +       PMIF_SPI_MODE_CTRL,
> > +       PMIF_IRQ_EVENT_EN_0,
> > +       PMIF_IRQ_FLAG_0,
> > +       PMIF_IRQ_CLR_0,
> > +       PMIF_IRQ_EVENT_EN_1,
> > +       PMIF_IRQ_FLAG_1,
> > +       PMIF_IRQ_CLR_1,
> > +       PMIF_IRQ_EVENT_EN_2,
> > +       PMIF_IRQ_FLAG_2,
> > +       PMIF_IRQ_CLR_2,
> > +       PMIF_IRQ_EVENT_EN_3,
> > +       PMIF_IRQ_FLAG_3,
> > +       PMIF_IRQ_CLR_3,
> > +       PMIF_IRQ_EVENT_EN_4,
> > +       PMIF_IRQ_FLAG_4,
> > +       PMIF_IRQ_CLR_4,
> > +       PMIF_WDT_EVENT_EN_0,
> > +       PMIF_WDT_FLAG_0,
> > +       PMIF_WDT_EVENT_EN_1,
> > +       PMIF_WDT_FLAG_1,
> > +       PMIF_SWINF_0_STA,
> > +       PMIF_SWINF_0_WDATA_31_0,
> > +       PMIF_SWINF_0_RDATA_31_0,
> > +       PMIF_SWINF_0_ACC,
> > +       PMIF_SWINF_0_VLD_CLR,
> > +       PMIF_SWINF_1_STA,
> > +       PMIF_SWINF_1_WDATA_31_0,
> > +       PMIF_SWINF_1_RDATA_31_0,
> > +       PMIF_SWINF_1_ACC,
> > +       PMIF_SWINF_1_VLD_CLR,
> > +       PMIF_SWINF_2_STA,
> > +       PMIF_SWINF_2_WDATA_31_0,
> > +       PMIF_SWINF_2_RDATA_31_0,
> > +       PMIF_SWINF_2_ACC,
> > +       PMIF_SWINF_2_VLD_CLR,
> > +       PMIF_SWINF_3_STA,
> > +       PMIF_SWINF_3_WDATA_31_0,
> > +       PMIF_SWINF_3_RDATA_31_0,
> > +       PMIF_SWINF_3_ACC,
> > +       PMIF_SWINF_3_VLD_CLR,
> > +};
> > +
> > +static const u32 mt6873_regs[] = {
> > +       [PMIF_INIT_DONE] =      0x0000,
> > +       [PMIF_INF_EN] =         0x0024,
> > +       [PMIF_ARB_EN] =         0x0150,
> > +       [PMIF_CMDISSUE_EN] =    0x03B4,
> > +       [PMIF_TIMER_CTRL] =     0x03E0,
> > +       [PMIF_SPI_MODE_CTRL] =  0x0400,
> > +       [PMIF_IRQ_EVENT_EN_0] = 0x0418,
> > +       [PMIF_IRQ_FLAG_0] =     0x0420,
> > +       [PMIF_IRQ_CLR_0] =      0x0424,
> > +       [PMIF_IRQ_EVENT_EN_1] = 0x0428,
> > +       [PMIF_IRQ_FLAG_1] =     0x0430,
> > +       [PMIF_IRQ_CLR_1] =      0x0434,
> > +       [PMIF_IRQ_EVENT_EN_2] = 0x0438,
> > +       [PMIF_IRQ_FLAG_2] =     0x0440,
> > +       [PMIF_IRQ_CLR_2] =      0x0444,
> > +       [PMIF_IRQ_EVENT_EN_3] = 0x0448,
> > +       [PMIF_IRQ_FLAG_3] =     0x0450,
> > +       [PMIF_IRQ_CLR_3] =      0x0454,
> > +       [PMIF_IRQ_EVENT_EN_4] = 0x0458,
> > +       [PMIF_IRQ_FLAG_4] =     0x0460,
> > +       [PMIF_IRQ_CLR_4] =      0x0464,
> > +       [PMIF_WDT_EVENT_EN_0] = 0x046C,
> > +       [PMIF_WDT_FLAG_0] =     0x0470,
> > +       [PMIF_WDT_EVENT_EN_1] = 0x0474,
> > +       [PMIF_WDT_FLAG_1] =     0x0478,
> > +       [PMIF_SWINF_0_ACC] =    0x0C00,
> > +       [PMIF_SWINF_0_WDATA_31_0] =     0x0C04,
> > +       [PMIF_SWINF_0_RDATA_31_0] =     0x0C14,
> > +       [PMIF_SWINF_0_VLD_CLR] =        0x0C24,
> > +       [PMIF_SWINF_0_STA] =    0x0C28,
> > +       [PMIF_SWINF_1_ACC] =    0x0C40,
> > +       [PMIF_SWINF_1_WDATA_31_0] =     0x0C44,
> > +       [PMIF_SWINF_1_RDATA_31_0] =     0x0C54,
> > +       [PMIF_SWINF_1_VLD_CLR] =        0x0C64,
> > +       [PMIF_SWINF_1_STA] =    0x0C68,
> > +       [PMIF_SWINF_2_ACC] =    0x0C80,
> > +       [PMIF_SWINF_2_WDATA_31_0] =     0x0C84,
> > +       [PMIF_SWINF_2_RDATA_31_0] =     0x0C94,
> > +       [PMIF_SWINF_2_VLD_CLR] =        0x0CA4,
> > +       [PMIF_SWINF_2_STA] =    0x0CA8,
> > +       [PMIF_SWINF_3_ACC] =    0x0CC0,
> > +       [PMIF_SWINF_3_WDATA_31_0] =     0x0CC4,
> > +       [PMIF_SWINF_3_RDATA_31_0] =     0x0CD4,
> > +       [PMIF_SWINF_3_VLD_CLR] =        0x0CE4,
> > +       [PMIF_SWINF_3_STA] =    0x0CE8,
> > +};
> > +
> > +enum spmi_regs {
> > +       SPMI_OP_ST_CTRL,
> > +       SPMI_GRP_ID_EN,
> > +       SPMI_OP_ST_STA,
> > +       SPMI_MST_SAMPL,
> > +       SPMI_MST_REQ_EN,
> > +       SPMI_REC_CTRL,
> > +       SPMI_REC0,
> > +       SPMI_REC1,
> > +       SPMI_REC2,
> > +       SPMI_REC3,
> > +       SPMI_REC4,
> > +       SPMI_MST_DBG,
> > +};
> > +
> > +static const u32 mt6873_spmi_regs[] = {
> 
> There's only one of these so far. Is there going to be a different
> register layout in the future? If we can avoid the indirection it would
> be ideal.
> 

Yes, we have other chips with different registers for spmi driver in the
feature.

> > +       [SPMI_OP_ST_CTRL] =     0x0000,
> > +       [SPMI_GRP_ID_EN] =      0x0004,
> > +       [SPMI_OP_ST_STA] =      0x0008,
> > +       [SPMI_MST_SAMPL] =      0x000c,
> > +       [SPMI_MST_REQ_EN] =     0x0010,
> > +       [SPMI_REC_CTRL] =       0x0040,
> > +       [SPMI_REC0] =           0x0044,
> > +       [SPMI_REC1] =           0x0048,
> > +       [SPMI_REC2] =           0x004c,
> > +       [SPMI_REC3] =           0x0050,
> > +       [SPMI_REC4] =           0x0054,
> > +       [SPMI_MST_DBG] =        0x00fc,
> > +};
> > +
> > +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
> > +{
> > +       return readl(arb->base + arb->data->regs[reg]);
> > +}
> > +
> > +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
> > +{
> > +       writel(val, arb->base + arb->data->regs[reg]);
> > +}
> > +
> > +static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
> > +{
> > +       writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
> > +}
> > +
> > +static bool pmif_is_fsm_vldclr(struct pmif *arb)
> > +{
> > +       u32 reg_rdata;
> > +
> > +       reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
> > +       return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
> > +}
> > +
> > +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       u32 rdata, cmd;
> > +       int ret;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> > +               return -EINVAL;
> > +       }
> > +
> > +       /* Check the opcode */
> > +       if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
> > +               return -EINVAL;
> > +
> > +       cmd = opc - SPMI_CMD_RESET;
> > +
> > +       mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
> > +       ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
> > +                                       rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0)
> > +               dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
> > +
> > +       return ret;
> > +}
> > +
> > +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> > +                             u16 addr, u8 *buf, size_t len)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       struct ch_reg *inf_reg;
> > +       int ret;
> > +       u32 data, cmd;
> > +       unsigned long flags;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> > +               return -EINVAL;
> > +       }
> > +
> > +       if (len > 4) {
> > +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> > +               return -EINVAL;
> > +       }
> > +
> > +       if (opc >= 0x60 && opc <= 0x7f)
> > +               opc = PMIF_CMD_REG;
> > +       else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
> > +               opc = PMIF_CMD_EXT_REG_LONG;
> > +       else
> > +               return -EINVAL;
> > +
> > +       raw_spin_lock_irqsave(&arb->lock, flags);
> > +
> > +       /* Wait for Software Interface FSM state to be IDLE. */
> > +       inf_reg = &arb->chan;
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_IDLE,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               /* set channel ready if the data has transferred */
> > +               if (pmif_is_fsm_vldclr(arb))
> > +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> > +               goto out;
> > +       }
> > +
> > +       /* Send the command. */
> > +       cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
> > +       pmif_writel(arb, cmd, inf_reg->ch_send);
> > +
> > +       /*
> > +        * Wait for Software Interface FSM state to be WFVLDCLR,
> > +        * read the data and clear the valid flag.
> > +        */
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_WFVLDCLR,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
> > +               goto out;
> > +       }
> > +
> > +       data = pmif_readl(arb, inf_reg->rdata);
> > +       memcpy(buf, &data, len);
> > +       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +
> > +out:
> > +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +
> > +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> > +                              u16 addr, const u8 *buf, size_t len)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       struct ch_reg *inf_reg;
> > +       int ret;
> > +       u32 data, cmd;
> > +       unsigned long flags;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> 
> Feels like something we should push up into the core framework instead
> of having each driver figure out.
> 

Thanks for the review.
After checking the framework, it already has the same check, so I will remove it in the next patch.

> > +               return -EINVAL;
> > +       }
> > +
> > +       if (len > 4) {
> > +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> 
> Feels like something we should push up into the core framework instead
> of having each driver figure out.
> 

Thanks for the comment, it's our hw design, not for common driver. 

> > +               return -EINVAL;
> > +       }
> > +
> > +       /* Check the opcode */
> > +       if (opc >= 0x40 && opc <= 0x5F)
> > +               opc = PMIF_CMD_REG;
> > +       else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
> > +               opc = PMIF_CMD_EXT_REG_LONG;
> > +       else if (opc >= 0x80)
> > +               opc = PMIF_CMD_REG_0;
> > +       else
> > +               return -EINVAL;
> > +
> > +       raw_spin_lock_irqsave(&arb->lock, flags);
> > +
> > +       /* Wait for Software Interface FSM state to be IDLE. */
> > +       inf_reg = &arb->chan;
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_IDLE,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               /* set channel ready if the data has transferred */
> > +               if (pmif_is_fsm_vldclr(arb))
> > +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> > +               goto out;
> > +       }
> > +
> > +       /* Set the write data. */
> > +       memcpy(&data, buf, len);
> > +       pmif_writel(arb, data, inf_reg->wdata);
> > +
> > +       /* Send the command. */
> > +       cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
> > +       pmif_writel(arb, cmd, inf_reg->ch_send);
> 
> What is BIT 29? Is that special somehow?
> 

Bit 29 means write or read cmd.
1 for write and 0 for read. 

> > +
> > +out:
> > +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +


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Re: [PATCH v6 3/4] spmi: mediatek: Add support for MT6873/8192

[Hsin-hsiung Wang]

Hi,

On Mon, 2021-02-08 at 14:21 -0800, Stephen Boyd wrote:
> Quoting Hsin-Hsiung Wang (2021-02-06 21:19:13)
> > diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
> > index a53bad541f1a..418848840999 100644
> > --- a/drivers/spmi/Kconfig
> > +++ b/drivers/spmi/Kconfig
> > @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
> >           This is required for communicating with Qualcomm PMICs and
> >           other devices that have the SPMI interface.
> >  
> > +config SPMI_MTK_PMIF
> > +       tristate "Mediatek SPMI Controller (PMIC Arbiter)"
> > +       help
> > +         If you say yes to this option, support will be included for the
> > +         built-in SPMI PMIC Arbiter interface on Mediatek family
> > +         processors.
> > +
> > +         This is required for communicating with Mediatek PMICs and
> > +         other devices that have the SPMI interface.
> 
> Preferably add another newline here to unstick the 'endif'
> 

Thanks. I will update it in the next patch.

> >  endif
> > diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c
> > new file mode 100644
> > index 000000000000..4ac4643f89f3
> > --- /dev/null
> > +++ b/drivers/spmi/spmi-mtk-pmif.c
> > @@ -0,0 +1,488 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2021 MediaTek Inc.
> > +
> > +#include <linux/clk.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/spmi.h>
> > +
> > +#define SWINF_IDLE     0x00
> > +#define SWINF_WFVLDCLR 0x06
> > +
> > +#define GET_SWINF(x)   (((x) >> 1) & 0x7)
> > +
> > +#define PMIF_CMD_REG_0         0
> > +#define PMIF_CMD_REG           1
> > +#define PMIF_CMD_EXT_REG       2
> > +#define PMIF_CMD_EXT_REG_LONG  3
> > +
> > +#define PMIF_DELAY_US   10
> > +#define PMIF_TIMEOUT_US (10 * 1000)
> > +
> > +#define PMIF_CHAN_OFFSET 0x5
> > +
> > +#define PMIF_MAX_CLKS  3
> > +
> > +#define SPMI_OP_ST_BUSY 1
> > +
> > +struct ch_reg {
> > +       u32 ch_sta;
> > +       u32 wdata;
> > +       u32 rdata;
> > +       u32 ch_send;
> > +       u32 ch_rdy;
> > +};
> > +
> > +struct pmif_data {
> > +       const u32       *regs;
> > +       const u32       *spmimst_regs;
> > +       u32     soc_chan;
> 
> Is this used?
> 

Yes.

> > +};
> > +
> > +struct pmif {
> > +       void __iomem    *base;
> > +       void __iomem    *spmimst_base;
> > +       raw_spinlock_t  lock;
> 
> Why is the spinlock raw? Is it used in hard irq handling?
> 

Thanks for the comment. After reviewing the code, I will remove it and
update it in the next patch.

> > +       struct ch_reg   chan;
> > +       struct clk_bulk_data clks[PMIF_MAX_CLKS];
> > +       u32 nclks;
> > +       const struct pmif_data *data;
> > +};
> > +
> > +static const char * const pmif_clock_names[] = {
> > +       "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux",
> > +};
> > +
> > +enum pmif_regs {
> > +       PMIF_INIT_DONE,
> > +       PMIF_INF_EN,
> > +       PMIF_ARB_EN,
> > +       PMIF_CMDISSUE_EN,
> > +       PMIF_TIMER_CTRL,
> > +       PMIF_SPI_MODE_CTRL,
> > +       PMIF_IRQ_EVENT_EN_0,
> > +       PMIF_IRQ_FLAG_0,
> > +       PMIF_IRQ_CLR_0,
> > +       PMIF_IRQ_EVENT_EN_1,
> > +       PMIF_IRQ_FLAG_1,
> > +       PMIF_IRQ_CLR_1,
> > +       PMIF_IRQ_EVENT_EN_2,
> > +       PMIF_IRQ_FLAG_2,
> > +       PMIF_IRQ_CLR_2,
> > +       PMIF_IRQ_EVENT_EN_3,
> > +       PMIF_IRQ_FLAG_3,
> > +       PMIF_IRQ_CLR_3,
> > +       PMIF_IRQ_EVENT_EN_4,
> > +       PMIF_IRQ_FLAG_4,
> > +       PMIF_IRQ_CLR_4,
> > +       PMIF_WDT_EVENT_EN_0,
> > +       PMIF_WDT_FLAG_0,
> > +       PMIF_WDT_EVENT_EN_1,
> > +       PMIF_WDT_FLAG_1,
> > +       PMIF_SWINF_0_STA,
> > +       PMIF_SWINF_0_WDATA_31_0,
> > +       PMIF_SWINF_0_RDATA_31_0,
> > +       PMIF_SWINF_0_ACC,
> > +       PMIF_SWINF_0_VLD_CLR,
> > +       PMIF_SWINF_1_STA,
> > +       PMIF_SWINF_1_WDATA_31_0,
> > +       PMIF_SWINF_1_RDATA_31_0,
> > +       PMIF_SWINF_1_ACC,
> > +       PMIF_SWINF_1_VLD_CLR,
> > +       PMIF_SWINF_2_STA,
> > +       PMIF_SWINF_2_WDATA_31_0,
> > +       PMIF_SWINF_2_RDATA_31_0,
> > +       PMIF_SWINF_2_ACC,
> > +       PMIF_SWINF_2_VLD_CLR,
> > +       PMIF_SWINF_3_STA,
> > +       PMIF_SWINF_3_WDATA_31_0,
> > +       PMIF_SWINF_3_RDATA_31_0,
> > +       PMIF_SWINF_3_ACC,
> > +       PMIF_SWINF_3_VLD_CLR,
> > +};
> > +
> > +static const u32 mt6873_regs[] = {
> > +       [PMIF_INIT_DONE] =      0x0000,
> > +       [PMIF_INF_EN] =         0x0024,
> > +       [PMIF_ARB_EN] =         0x0150,
> > +       [PMIF_CMDISSUE_EN] =    0x03B4,
> > +       [PMIF_TIMER_CTRL] =     0x03E0,
> > +       [PMIF_SPI_MODE_CTRL] =  0x0400,
> > +       [PMIF_IRQ_EVENT_EN_0] = 0x0418,
> > +       [PMIF_IRQ_FLAG_0] =     0x0420,
> > +       [PMIF_IRQ_CLR_0] =      0x0424,
> > +       [PMIF_IRQ_EVENT_EN_1] = 0x0428,
> > +       [PMIF_IRQ_FLAG_1] =     0x0430,
> > +       [PMIF_IRQ_CLR_1] =      0x0434,
> > +       [PMIF_IRQ_EVENT_EN_2] = 0x0438,
> > +       [PMIF_IRQ_FLAG_2] =     0x0440,
> > +       [PMIF_IRQ_CLR_2] =      0x0444,
> > +       [PMIF_IRQ_EVENT_EN_3] = 0x0448,
> > +       [PMIF_IRQ_FLAG_3] =     0x0450,
> > +       [PMIF_IRQ_CLR_3] =      0x0454,
> > +       [PMIF_IRQ_EVENT_EN_4] = 0x0458,
> > +       [PMIF_IRQ_FLAG_4] =     0x0460,
> > +       [PMIF_IRQ_CLR_4] =      0x0464,
> > +       [PMIF_WDT_EVENT_EN_0] = 0x046C,
> > +       [PMIF_WDT_FLAG_0] =     0x0470,
> > +       [PMIF_WDT_EVENT_EN_1] = 0x0474,
> > +       [PMIF_WDT_FLAG_1] =     0x0478,
> > +       [PMIF_SWINF_0_ACC] =    0x0C00,
> > +       [PMIF_SWINF_0_WDATA_31_0] =     0x0C04,
> > +       [PMIF_SWINF_0_RDATA_31_0] =     0x0C14,
> > +       [PMIF_SWINF_0_VLD_CLR] =        0x0C24,
> > +       [PMIF_SWINF_0_STA] =    0x0C28,
> > +       [PMIF_SWINF_1_ACC] =    0x0C40,
> > +       [PMIF_SWINF_1_WDATA_31_0] =     0x0C44,
> > +       [PMIF_SWINF_1_RDATA_31_0] =     0x0C54,
> > +       [PMIF_SWINF_1_VLD_CLR] =        0x0C64,
> > +       [PMIF_SWINF_1_STA] =    0x0C68,
> > +       [PMIF_SWINF_2_ACC] =    0x0C80,
> > +       [PMIF_SWINF_2_WDATA_31_0] =     0x0C84,
> > +       [PMIF_SWINF_2_RDATA_31_0] =     0x0C94,
> > +       [PMIF_SWINF_2_VLD_CLR] =        0x0CA4,
> > +       [PMIF_SWINF_2_STA] =    0x0CA8,
> > +       [PMIF_SWINF_3_ACC] =    0x0CC0,
> > +       [PMIF_SWINF_3_WDATA_31_0] =     0x0CC4,
> > +       [PMIF_SWINF_3_RDATA_31_0] =     0x0CD4,
> > +       [PMIF_SWINF_3_VLD_CLR] =        0x0CE4,
> > +       [PMIF_SWINF_3_STA] =    0x0CE8,
> > +};
> > +
> > +enum spmi_regs {
> > +       SPMI_OP_ST_CTRL,
> > +       SPMI_GRP_ID_EN,
> > +       SPMI_OP_ST_STA,
> > +       SPMI_MST_SAMPL,
> > +       SPMI_MST_REQ_EN,
> > +       SPMI_REC_CTRL,
> > +       SPMI_REC0,
> > +       SPMI_REC1,
> > +       SPMI_REC2,
> > +       SPMI_REC3,
> > +       SPMI_REC4,
> > +       SPMI_MST_DBG,
> > +};
> > +
> > +static const u32 mt6873_spmi_regs[] = {
> 
> There's only one of these so far. Is there going to be a different
> register layout in the future? If we can avoid the indirection it would
> be ideal.
> 

Yes, we have other chips with different registers for spmi driver in the
feature.

> > +       [SPMI_OP_ST_CTRL] =     0x0000,
> > +       [SPMI_GRP_ID_EN] =      0x0004,
> > +       [SPMI_OP_ST_STA] =      0x0008,
> > +       [SPMI_MST_SAMPL] =      0x000c,
> > +       [SPMI_MST_REQ_EN] =     0x0010,
> > +       [SPMI_REC_CTRL] =       0x0040,
> > +       [SPMI_REC0] =           0x0044,
> > +       [SPMI_REC1] =           0x0048,
> > +       [SPMI_REC2] =           0x004c,
> > +       [SPMI_REC3] =           0x0050,
> > +       [SPMI_REC4] =           0x0054,
> > +       [SPMI_MST_DBG] =        0x00fc,
> > +};
> > +
> > +static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
> > +{
> > +       return readl(arb->base + arb->data->regs[reg]);
> > +}
> > +
> > +static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
> > +{
> > +       writel(val, arb->base + arb->data->regs[reg]);
> > +}
> > +
> > +static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg)
> > +{
> > +       writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]);
> > +}
> > +
> > +static bool pmif_is_fsm_vldclr(struct pmif *arb)
> > +{
> > +       u32 reg_rdata;
> > +
> > +       reg_rdata = pmif_readl(arb, arb->chan.ch_sta);
> > +       return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR;
> > +}
> > +
> > +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       u32 rdata, cmd;
> > +       int ret;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> > +               return -EINVAL;
> > +       }
> > +
> > +       /* Check the opcode */
> > +       if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
> > +               return -EINVAL;
> > +
> > +       cmd = opc - SPMI_CMD_RESET;
> > +
> > +       mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
> > +       ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA],
> > +                                       rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0)
> > +               dev_err(&ctrl->dev, "timeout, err = %d\n", ret);
> > +
> > +       return ret;
> > +}
> > +
> > +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> > +                             u16 addr, u8 *buf, size_t len)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       struct ch_reg *inf_reg;
> > +       int ret;
> > +       u32 data, cmd;
> > +       unsigned long flags;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> > +               return -EINVAL;
> > +       }
> > +
> > +       if (len > 4) {
> > +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> > +               return -EINVAL;
> > +       }
> > +
> > +       if (opc >= 0x60 && opc <= 0x7f)
> > +               opc = PMIF_CMD_REG;
> > +       else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f))
> > +               opc = PMIF_CMD_EXT_REG_LONG;
> > +       else
> > +               return -EINVAL;
> > +
> > +       raw_spin_lock_irqsave(&arb->lock, flags);
> > +
> > +       /* Wait for Software Interface FSM state to be IDLE. */
> > +       inf_reg = &arb->chan;
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_IDLE,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               /* set channel ready if the data has transferred */
> > +               if (pmif_is_fsm_vldclr(arb))
> > +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> > +               goto out;
> > +       }
> > +
> > +       /* Send the command. */
> > +       cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr;
> > +       pmif_writel(arb, cmd, inf_reg->ch_send);
> > +
> > +       /*
> > +        * Wait for Software Interface FSM state to be WFVLDCLR,
> > +        * read the data and clear the valid flag.
> > +        */
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_WFVLDCLR,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n");
> > +               goto out;
> > +       }
> > +
> > +       data = pmif_readl(arb, inf_reg->rdata);
> > +       memcpy(buf, &data, len);
> > +       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +
> > +out:
> > +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +
> > +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
> > +                              u16 addr, const u8 *buf, size_t len)
> > +{
> > +       struct pmif *arb = spmi_controller_get_drvdata(ctrl);
> > +       struct ch_reg *inf_reg;
> > +       int ret;
> > +       u32 data, cmd;
> > +       unsigned long flags;
> > +
> > +       /* Check for argument validation. */
> > +       if (sid & ~0xf) {
> > +               dev_err(&ctrl->dev, "exceed the max slv id\n");
> 
> Feels like something we should push up into the core framework instead
> of having each driver figure out.
> 

Thanks for the review.
After checking the framework, it already has the same check, so I will remove it in the next patch.

> > +               return -EINVAL;
> > +       }
> > +
> > +       if (len > 4) {
> > +               dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len);
> 
> Feels like something we should push up into the core framework instead
> of having each driver figure out.
> 

Thanks for the comment, it's our hw design, not for common driver. 

> > +               return -EINVAL;
> > +       }
> > +
> > +       /* Check the opcode */
> > +       if (opc >= 0x40 && opc <= 0x5F)
> > +               opc = PMIF_CMD_REG;
> > +       else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37))
> > +               opc = PMIF_CMD_EXT_REG_LONG;
> > +       else if (opc >= 0x80)
> > +               opc = PMIF_CMD_REG_0;
> > +       else
> > +               return -EINVAL;
> > +
> > +       raw_spin_lock_irqsave(&arb->lock, flags);
> > +
> > +       /* Wait for Software Interface FSM state to be IDLE. */
> > +       inf_reg = &arb->chan;
> > +       ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta],
> > +                                       data, GET_SWINF(data) == SWINF_IDLE,
> > +                                       PMIF_DELAY_US, PMIF_TIMEOUT_US);
> > +       if (ret < 0) {
> > +               /* set channel ready if the data has transferred */
> > +               if (pmif_is_fsm_vldclr(arb))
> > +                       pmif_writel(arb, 1, inf_reg->ch_rdy);
> > +               dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n");
> > +               goto out;
> > +       }
> > +
> > +       /* Set the write data. */
> > +       memcpy(&data, buf, len);
> > +       pmif_writel(arb, data, inf_reg->wdata);
> > +
> > +       /* Send the command. */
> > +       cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr;
> > +       pmif_writel(arb, cmd, inf_reg->ch_send);
> 
> What is BIT 29? Is that special somehow?
> 

Bit 29 means write or read cmd.
1 for write and 0 for read. 

> > +
> > +out:
> > +       raw_spin_unlock_irqrestore(&arb->lock, flags);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +


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