* FAILED: patch "[PATCH] arm64: Extend workaround for erratum 1024718 to all versions" failed to apply to 5.4-stable tree
@ 2021-03-01 12:15 gregkh
2021-03-01 12:54 ` [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 Suzuki K Poulose
0 siblings, 1 reply; 14+ messages in thread
From: gregkh @ 2021-03-01 12:15 UTC (permalink / raw)
To: suzuki.poulose, catalin.marinas, hayashi.kunihiko, james.morse, will
Cc: stable
The patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From c0b15c25d25171db4b70cc0b7dbc1130ee94017d Mon Sep 17 00:00:00 2001
From: Suzuki K Poulose <suzuki.poulose@arm.com>
Date: Wed, 3 Feb 2021 23:00:57 +0000
Subject: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions
of Cortex-A55
The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.
Cc: stable@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com
[will: Update Kconfig help text]
Signed-off-by: Will Deacon <will@kernel.org>
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f39568b28ec1..3dfb25afa616 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -522,7 +522,7 @@ config ARM64_ERRATUM_1024718
help
This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
- Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+ Affected Cortex-A55 cores (all revisions) could cause incorrect
update of the hardware dirty bit when the DBM/AP bits are updated
without a break-before-make. The workaround is to disable the usage
of hardware DBM locally on the affected cores. CPUs not affected by
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index e99eddec0a46..db400ca77427 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
/* List of CPUs which have broken DBM support. */
static const struct midr_range cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_1024718
- MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
/* Kryo4xx Silver (rdpe => r1p0) */
MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
#endif
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-03-01 12:15 FAILED: patch "[PATCH] arm64: Extend workaround for erratum 1024718 to all versions" failed to apply to 5.4-stable tree gregkh
@ 2021-03-01 12:54 ` Suzuki K Poulose
2021-03-01 12:58 ` [PATCH v2] " Suzuki K Poulose
0 siblings, 1 reply; 14+ messages in thread
From: Suzuki K Poulose @ 2021-03-01 12:54 UTC (permalink / raw)
To: stable; +Cc: suzuki.poulose, gregkh, will, catalin.marinas
commit c0b15c25d25171db4b70cc0b7dbc1130ee94017d upstream
The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.
Cc: stable@vger.kernel.org # v5.4-
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com
[will: Update Kconfig help text]
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/Kconfig | 2 +-
arch/arm64/kernel/cpufeature.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a0bc9bbb92f3..0ad21882aa04 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -489,7 +489,7 @@ config ARM64_ERRATUM_1024718
help
This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
- Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+ Affected Cortex-A55 cores (all versions) could cause incorrect
update of the hardware dirty bit when the DBM/AP bits are updated
without a break-before-make. The workaround is to disable the usage
of hardware DBM locally on the affected cores. CPUs not affected by
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f2ec84540414..79caab15ccbf 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1092,7 +1092,7 @@ static bool cpu_has_broken_dbm(void)
/* List of CPUs which have broken DBM support. */
static const struct midr_range cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_1024718
- MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
#endif
{},
};
--
2.24.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-03-01 12:54 ` [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 Suzuki K Poulose
@ 2021-03-01 12:58 ` Suzuki K Poulose
2021-03-01 13:11 ` Greg KH
0 siblings, 1 reply; 14+ messages in thread
From: Suzuki K Poulose @ 2021-03-01 12:58 UTC (permalink / raw)
To: stable; +Cc: suzuki.poulose, gregkh, will, catalin.marinas
commit c0b15c25d25171db4b70cc0b7dbc1130ee94017d upstream
The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.
Cc: stable@vger.kernel.org # v5.4-
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com
[will: Update Kconfig help text]
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes in v2:
- Match the Kconfig text to the original commit
"versions" => "revisions"
arch/arm64/Kconfig | 2 +-
arch/arm64/kernel/cpufeature.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a0bc9bbb92f3..9c8ea5939865 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -489,7 +489,7 @@ config ARM64_ERRATUM_1024718
help
This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
- Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+ Affected Cortex-A55 cores (all revisions) could cause incorrect
update of the hardware dirty bit when the DBM/AP bits are updated
without a break-before-make. The workaround is to disable the usage
of hardware DBM locally on the affected cores. CPUs not affected by
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f2ec84540414..79caab15ccbf 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1092,7 +1092,7 @@ static bool cpu_has_broken_dbm(void)
/* List of CPUs which have broken DBM support. */
static const struct midr_range cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_1024718
- MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
#endif
{},
};
--
2.24.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-03-01 12:58 ` [PATCH v2] " Suzuki K Poulose
@ 2021-03-01 13:11 ` Greg KH
0 siblings, 0 replies; 14+ messages in thread
From: Greg KH @ 2021-03-01 13:11 UTC (permalink / raw)
To: Suzuki K Poulose; +Cc: stable, will, catalin.marinas
On Mon, Mar 01, 2021 at 12:58:15PM +0000, Suzuki K Poulose wrote:
> commit c0b15c25d25171db4b70cc0b7dbc1130ee94017d upstream
>
> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
> we apply the work around for r0p0 - r1p0. Unfortunately this
> won't be fixed for the future revisions for the CPU. Thus
> extend the work around for all versions of A55, to cover
> for r2p0 and any future revisions.
>
> Cc: stable@vger.kernel.org # v5.4-
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Link: https://lore.kernel.org/r/20210203230057.3961239-1-suzuki.poulose@arm.com
> [will: Update Kconfig help text]
> Signed-off-by: Will Deacon <will@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes in v2:
> - Match the Kconfig text to the original commit
> "versions" => "revisions"
>
> arch/arm64/Kconfig | 2 +-
> arch/arm64/kernel/cpufeature.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Applied to 5.4.y and 4.19.y, if it needs to go anywhere older, please
provide working backports.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
@ 2021-02-03 23:00 ` Suzuki K Poulose
0 siblings, 0 replies; 14+ messages in thread
From: Suzuki K Poulose @ 2021-02-03 23:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: will, catalin.marinas, Suzuki K Poulose, stable, James Morse,
Kunihiko Hayashi
The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.
Cc: stable@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/kernel/cpufeature.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index e99eddec0a46..db400ca77427 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
/* List of CPUs which have broken DBM support. */
static const struct midr_range cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_1024718
- MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
/* Kryo4xx Silver (rdpe => r1p0) */
MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
#endif
--
2.24.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
@ 2021-02-03 23:00 ` Suzuki K Poulose
0 siblings, 0 replies; 14+ messages in thread
From: Suzuki K Poulose @ 2021-02-03 23:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Kunihiko Hayashi, Suzuki K Poulose, catalin.marinas, stable,
James Morse, will
The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
we apply the work around for r0p0 - r1p0. Unfortunately this
won't be fixed for the future revisions for the CPU. Thus
extend the work around for all versions of A55, to cover
for r2p0 and any future revisions.
Cc: stable@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/kernel/cpufeature.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index e99eddec0a46..db400ca77427 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
/* List of CPUs which have broken DBM support. */
static const struct midr_range cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_1024718
- MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
/* Kryo4xx Silver (rdpe => r1p0) */
MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
#endif
--
2.24.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-02-03 23:00 ` Suzuki K Poulose
@ 2021-02-04 9:54 ` Will Deacon
-1 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2021-02-04 9:54 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: linux-arm-kernel, catalin.marinas, stable, James Morse, Kunihiko Hayashi
Hi Suzuki,
On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote:
> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
> we apply the work around for r0p0 - r1p0. Unfortunately this
> won't be fixed for the future revisions for the CPU. Thus
> extend the work around for all versions of A55, to cover
> for r2p0 and any future revisions.
>
> Cc: stable@vger.kernel.org
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/kernel/cpufeature.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index e99eddec0a46..db400ca77427 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
> /* List of CPUs which have broken DBM support. */
> static const struct midr_range cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_1024718
> - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
I think we have bigger problems with this erratum, since cpu_has_hw_af()
doesn't taken this erratum into account at all, meaning that
arch_faults_on_old_pte() will return the wrong value on any system with an
A55.
Please can you fix that along with this patch? You'll need to pay extra
attention to the stuff I've queued on for-next/faultaround, where we will
actually want arch_wants_old_prefaulted_pte() to return 'true' if any of the
CPUs have DBM, since it's a pure performance thing.
Cheers,
Will
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
@ 2021-02-04 9:54 ` Will Deacon
0 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2021-02-04 9:54 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: catalin.marinas, Kunihiko Hayashi, James Morse, stable, linux-arm-kernel
Hi Suzuki,
On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote:
> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
> we apply the work around for r0p0 - r1p0. Unfortunately this
> won't be fixed for the future revisions for the CPU. Thus
> extend the work around for all versions of A55, to cover
> for r2p0 and any future revisions.
>
> Cc: stable@vger.kernel.org
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/kernel/cpufeature.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index e99eddec0a46..db400ca77427 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
> /* List of CPUs which have broken DBM support. */
> static const struct midr_range cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_1024718
> - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
I think we have bigger problems with this erratum, since cpu_has_hw_af()
doesn't taken this erratum into account at all, meaning that
arch_faults_on_old_pte() will return the wrong value on any system with an
A55.
Please can you fix that along with this patch? You'll need to pay extra
attention to the stuff I've queued on for-next/faultaround, where we will
actually want arch_wants_old_prefaulted_pte() to return 'true' if any of the
CPUs have DBM, since it's a pure performance thing.
Cheers,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-02-04 9:54 ` Will Deacon
@ 2021-02-05 17:41 ` Suzuki K Poulose
-1 siblings, 0 replies; 14+ messages in thread
From: Suzuki K Poulose @ 2021-02-05 17:41 UTC (permalink / raw)
To: Will Deacon
Cc: linux-arm-kernel, catalin.marinas, stable, James Morse, Kunihiko Hayashi
Hi Will
On 2/4/21 9:54 AM, Will Deacon wrote:
> Hi Suzuki,
>
> On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote:
>> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
>> we apply the work around for r0p0 - r1p0. Unfortunately this
>> won't be fixed for the future revisions for the CPU. Thus
>> extend the work around for all versions of A55, to cover
>> for r2p0 and any future revisions.
>>
>> Cc: stable@vger.kernel.org
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: James Morse <james.morse@arm.com>
>> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> arch/arm64/kernel/cpufeature.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index e99eddec0a46..db400ca77427 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
>> /* List of CPUs which have broken DBM support. */
>> static const struct midr_range cpus[] = {
>> #ifdef CONFIG_ARM64_ERRATUM_1024718
>> - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
>> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
>
> I think we have bigger problems with this erratum, since cpu_has_hw_af()
> doesn't taken this erratum into account at all, meaning that
> arch_faults_on_old_pte() will return the wrong value on any system with an
> A55.
Please note that we enable HW_AF on these CPUs even with this erratum as
they are not affected. It is only the DBM that we selectively disable. Thus
the AF flag checks are still valid (See __cpu_setup in arch/arm64/mm/proc.S).
Or am I miss something ?
Kind regards
Suzuki
>
> Please can you fix that along with this patch? You'll need to pay extra
> attention to the stuff I've queued on for-next/faultaround, where we will
> actually want arch_wants_old_prefaulted_pte() to return 'true' if any of the
> CPUs have DBM, since it's a pure performance thing.
>
> Cheers,
>
> Will
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
@ 2021-02-05 17:41 ` Suzuki K Poulose
0 siblings, 0 replies; 14+ messages in thread
From: Suzuki K Poulose @ 2021-02-05 17:41 UTC (permalink / raw)
To: Will Deacon
Cc: catalin.marinas, Kunihiko Hayashi, James Morse, stable, linux-arm-kernel
Hi Will
On 2/4/21 9:54 AM, Will Deacon wrote:
> Hi Suzuki,
>
> On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote:
>> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
>> we apply the work around for r0p0 - r1p0. Unfortunately this
>> won't be fixed for the future revisions for the CPU. Thus
>> extend the work around for all versions of A55, to cover
>> for r2p0 and any future revisions.
>>
>> Cc: stable@vger.kernel.org
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: James Morse <james.morse@arm.com>
>> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> arch/arm64/kernel/cpufeature.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index e99eddec0a46..db400ca77427 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
>> /* List of CPUs which have broken DBM support. */
>> static const struct midr_range cpus[] = {
>> #ifdef CONFIG_ARM64_ERRATUM_1024718
>> - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
>> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
>
> I think we have bigger problems with this erratum, since cpu_has_hw_af()
> doesn't taken this erratum into account at all, meaning that
> arch_faults_on_old_pte() will return the wrong value on any system with an
> A55.
Please note that we enable HW_AF on these CPUs even with this erratum as
they are not affected. It is only the DBM that we selectively disable. Thus
the AF flag checks are still valid (See __cpu_setup in arch/arm64/mm/proc.S).
Or am I miss something ?
Kind regards
Suzuki
>
> Please can you fix that along with this patch? You'll need to pay extra
> attention to the stuff I've queued on for-next/faultaround, where we will
> actually want arch_wants_old_prefaulted_pte() to return 'true' if any of the
> CPUs have DBM, since it's a pure performance thing.
>
> Cheers,
>
> Will
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-02-05 17:41 ` Suzuki K Poulose
@ 2021-02-08 12:29 ` Will Deacon
-1 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2021-02-08 12:29 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: linux-arm-kernel, catalin.marinas, stable, James Morse, Kunihiko Hayashi
On Fri, Feb 05, 2021 at 05:41:05PM +0000, Suzuki K Poulose wrote:
> On 2/4/21 9:54 AM, Will Deacon wrote:
> > On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote:
> > > The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
> > > we apply the work around for r0p0 - r1p0. Unfortunately this
> > > won't be fixed for the future revisions for the CPU. Thus
> > > extend the work around for all versions of A55, to cover
> > > for r2p0 and any future revisions.
> > >
> > > Cc: stable@vger.kernel.org
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: James Morse <james.morse@arm.com>
> > > Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > ---
> > > arch/arm64/kernel/cpufeature.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > > index e99eddec0a46..db400ca77427 100644
> > > --- a/arch/arm64/kernel/cpufeature.c
> > > +++ b/arch/arm64/kernel/cpufeature.c
> > > @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
> > > /* List of CPUs which have broken DBM support. */
> > > static const struct midr_range cpus[] = {
> > > #ifdef CONFIG_ARM64_ERRATUM_1024718
> > > - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
> > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
> >
> > I think we have bigger problems with this erratum, since cpu_has_hw_af()
> > doesn't taken this erratum into account at all, meaning that
> > arch_faults_on_old_pte() will return the wrong value on any system with an
> > A55.
>
> Please note that we enable HW_AF on these CPUs even with this erratum as
> they are not affected. It is only the DBM that we selectively disable. Thus
> the AF flag checks are still valid (See __cpu_setup in arch/arm64/mm/proc.S).
> Or am I miss something ?
Thanks, you're completely right! I'll queue this one then, and update the
Kconfig test at the same time.
Will
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
@ 2021-02-08 12:29 ` Will Deacon
0 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2021-02-08 12:29 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: catalin.marinas, Kunihiko Hayashi, James Morse, stable, linux-arm-kernel
On Fri, Feb 05, 2021 at 05:41:05PM +0000, Suzuki K Poulose wrote:
> On 2/4/21 9:54 AM, Will Deacon wrote:
> > On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote:
> > > The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
> > > we apply the work around for r0p0 - r1p0. Unfortunately this
> > > won't be fixed for the future revisions for the CPU. Thus
> > > extend the work around for all versions of A55, to cover
> > > for r2p0 and any future revisions.
> > >
> > > Cc: stable@vger.kernel.org
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: James Morse <james.morse@arm.com>
> > > Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > ---
> > > arch/arm64/kernel/cpufeature.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > > index e99eddec0a46..db400ca77427 100644
> > > --- a/arch/arm64/kernel/cpufeature.c
> > > +++ b/arch/arm64/kernel/cpufeature.c
> > > @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
> > > /* List of CPUs which have broken DBM support. */
> > > static const struct midr_range cpus[] = {
> > > #ifdef CONFIG_ARM64_ERRATUM_1024718
> > > - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
> > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
> >
> > I think we have bigger problems with this erratum, since cpu_has_hw_af()
> > doesn't taken this erratum into account at all, meaning that
> > arch_faults_on_old_pte() will return the wrong value on any system with an
> > A55.
>
> Please note that we enable HW_AF on these CPUs even with this erratum as
> they are not affected. It is only the DBM that we selectively disable. Thus
> the AF flag checks are still valid (See __cpu_setup in arch/arm64/mm/proc.S).
> Or am I miss something ?
Thanks, you're completely right! I'll queue this one then, and update the
Kconfig test at the same time.
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
2021-02-03 23:00 ` Suzuki K Poulose
@ 2021-02-08 14:55 ` Will Deacon
-1 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2021-02-08 14:55 UTC (permalink / raw)
To: linux-arm-kernel, Suzuki K Poulose
Cc: catalin.marinas, kernel-team, Will Deacon, Kunihiko Hayashi,
James Morse, stable
On Wed, 3 Feb 2021 23:00:57 +0000, Suzuki K Poulose wrote:
> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
> we apply the work around for r0p0 - r1p0. Unfortunately this
> won't be fixed for the future revisions for the CPU. Thus
> extend the work around for all versions of A55, to cover
> for r2p0 and any future revisions.
Applied to arm64 (for-next/errata), thanks!
[1/1] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
https://git.kernel.org/arm64/c/c0b15c25d251
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
@ 2021-02-08 14:55 ` Will Deacon
0 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2021-02-08 14:55 UTC (permalink / raw)
To: linux-arm-kernel, Suzuki K Poulose
Cc: Kunihiko Hayashi, catalin.marinas, stable, Will Deacon,
James Morse, kernel-team
On Wed, 3 Feb 2021 23:00:57 +0000, Suzuki K Poulose wrote:
> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However
> we apply the work around for r0p0 - r1p0. Unfortunately this
> won't be fixed for the future revisions for the CPU. Thus
> extend the work around for all versions of A55, to cover
> for r2p0 and any future revisions.
Applied to arm64 (for-next/errata), thanks!
[1/1] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55
https://git.kernel.org/arm64/c/c0b15c25d251
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-03-01 13:12 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-01 12:15 FAILED: patch "[PATCH] arm64: Extend workaround for erratum 1024718 to all versions" failed to apply to 5.4-stable tree gregkh
2021-03-01 12:54 ` [PATCH] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 Suzuki K Poulose
2021-03-01 12:58 ` [PATCH v2] " Suzuki K Poulose
2021-03-01 13:11 ` Greg KH
-- strict thread matches above, loose matches on Subject: below --
2021-02-03 23:00 [PATCH] " Suzuki K Poulose
2021-02-03 23:00 ` Suzuki K Poulose
2021-02-04 9:54 ` Will Deacon
2021-02-04 9:54 ` Will Deacon
2021-02-05 17:41 ` Suzuki K Poulose
2021-02-05 17:41 ` Suzuki K Poulose
2021-02-08 12:29 ` Will Deacon
2021-02-08 12:29 ` Will Deacon
2021-02-08 14:55 ` Will Deacon
2021-02-08 14:55 ` Will Deacon
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