* [igt-dev] [RFC i-g-t 01/11] Sync i915_drm.h UAPI for PXP
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 02/11] Add basic PXP testing of buffer and context alloc Alan Previn
` (11 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Sync i915_drm.h UAPI for PXP
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
include/drm-uapi/i915_drm.h | 94 ++++++++++++++++++++++++++++++++++++-
1 file changed, 93 insertions(+), 1 deletion(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index bf9ea471..62828148 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1694,11 +1716,76 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * Enable usage of protected content with the context. This flag can only be
+ * set at context creation time and, when set to true, must be preceded by
+ * an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE to false. This flag
+ * can't be set to true in conjunction with setting the
+ * I915_CONTEXT_PARAM_BANNABLE flag to false.
+ *
+ * Given the numerous restriction on this flag, there are several unique
+ * failure cases:
+ *
+ * -ENODEV: feature not available
+ * -EEXIST: trying to modify an existing context
+ * -EPERM: trying to mark a recoverable or not bannable context as protected
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull << 32)
+
+/*
+ * I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true, buffer contents is expected to be protected by PXP
+ * encryption and requires decryption for scan out and processing. This is
+ * only possible on platforms that have PXP enabled, on all other scenarios
+ * setting this flag will cause the ioctl to fail and return -ENODEV.
+ *
+ * Protected buffers can only be used with contexts created using the
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. The buffer contents are
+ * considered invalid after a PXP session teardown.
+ *
+ * Given the restriction above, the following errors are possible when
+ * submitting a protected object in an execbuf call:
+ *
+ * -ENODEV: PXP session not currently active
+ * -EIO: buffer has become invalid after a teardown event
+ * -EPERM: buffer submitted using a context not marked as protected
+ */
+#define I915_OBJECT_PARAM_PROTECTED_CONTENT 0x0
+/* Must be kept compact -- no holes and well documented */
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
@@ -1924,6 +2011,7 @@ struct drm_i915_reg_read {
struct drm_i915_reset_stats {
__u32 ctx_id;
__u32 flags;
+#define I915_CONTEXT_INVALIDATED 0x1
/* All resets since boot/module reload, for all contexts */
__u32 reset_count;
@@ -2093,7 +2181,7 @@ struct drm_i915_perf_open_param {
* Change metrics_set captured by a stream.
*
* If the stream is bound to a specific context, the configuration change
- * will performed __inline__ with that context such that it takes effect before
+ * will performed inline with that context such that it takes effect before
* the next execbuf submission.
*
* Returns the previously bound metrics set id, or a negative error code.
@@ -2376,6 +2464,10 @@ struct drm_i915_query_perf_config {
__u8 data[];
};
+
+/* ID of the protected content session managed by i915 when PXP is active */
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
+
#if defined(__cplusplus)
}
#endif
--
2.25.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [igt-dev] [RFC i-g-t 02/11] Add basic PXP testing of buffer and context alloc
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 01/11] Sync i915_drm.h UAPI for PXP Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-03 23:41 ` Chris Wilson
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 03/11] Add PXP attributes into lib batchbuffer and buffer structs Alan Previn
` (10 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Test PXP capability support as well as the allocation of protected
buffers and protected contexts.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
tests/Makefile.sources | 3 +
tests/i915/i915_pxp.c | 410 +++++++++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
3 files changed, 414 insertions(+)
create mode 100644 tests/i915/i915_pxp.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 4f24fb3a..1bbb4d7b 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -517,6 +517,9 @@ i915_pm_rps_SOURCES = i915/i915_pm_rps.c
TESTS_progs += i915_pm_sseu
i915_pm_sseu_SOURCES = i915/i915_pm_sseu.c
+TESTS_progs += i915_pxp
+i915_pxp_SOURCES = i915/i915_pxp.c
+
TESTS_progs += i915_query
i915_query_SOURCES = i915/i915_query.c
diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
new file mode 100644
index 00000000..40a817b2
--- /dev/null
+++ b/tests/i915/i915_pxp.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <sys/ioctl.h>
+
+#include "igt.h"
+#include "i915/gem.h"
+
+IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
+ "that allows the handling of protected content through "
+ "the arbitration of hardware protected sessions.");
+
+/* test-configs for protected buffer creation*/
+#define BO_ALLOC_NO_HW_SUPPORT 1
+#define BO_ALLOC_PROTECT_ON 2
+#define BO_ALLOC_PROTECT_OFF 3
+
+/* test-configs for protected context creation*/
+#define CTX_ALLOC_NO_HW_SUPPORT 1
+#define CTX_ALLOC_RECOVER_OFF_PROTECT_OFF 2
+#define CTX_ALLOC_RECOVER_OFF_PROTECT_ON 3
+#define CTX_ALLOC_RECOVER_ON_PROTECT_OFF 4
+#define CTX_ALLOC_RECOVER_ON_PROTECT_ON 5
+#define CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON 6
+#define CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF 7
+#define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
+#define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
+
+static bool is_pxp_hw_supported(int i915)
+{
+ uint32_t gen;
+
+ gen = intel_gen(intel_get_drm_devid(i915));
+ if (!gen) {
+ igt_info("No device info found - assume no PXP support.\n");
+ return false;
+ }
+
+ if (gen >= 12)
+ return true;
+
+ return false;
+}
+
+static uint32_t create_protected_bo(int i915, uint32_t size,
+ bool with_protected_param,
+ bool protected_is_true, int expected_return)
+{
+ int ret;
+
+ struct drm_i915_gem_object_param protected_param = {
+ .param = I915_OBJECT_PARAM | I915_OBJECT_PARAM_PROTECTED_CONTENT,
+ .data = 0,
+ };
+
+ struct drm_i915_gem_create_ext_setparam setparam_protected = {
+ .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
+ .param = protected_param,
+ };
+
+ struct drm_i915_gem_create_ext create_ext = {
+ .size = size,
+ .extensions = (uintptr_t)&setparam_protected,
+ };
+
+ if (!with_protected_param) {
+ create_ext.extensions = 0;
+ } else {
+ if (protected_is_true) {
+ protected_param.data = 1;
+ setparam_protected.param = protected_param;
+ } else {
+ protected_param.data = 0;
+ setparam_protected.param = protected_param;
+ }
+ }
+
+ ret = ioctl(i915, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ igt_assert_eq(ret, expected_return);
+
+ return create_ext.handle;
+}
+
+static void test_create_protected_buffer(int i915, uint32_t test_cfg)
+{
+ uint32_t bo;
+
+ switch (test_cfg) {
+ case BO_ALLOC_NO_HW_SUPPORT:
+ bo = create_protected_bo(i915, 4096, false, false, 0);
+ gem_close(i915, bo);
+ bo = create_protected_bo(i915, 4096, true, true, -ENODEV);
+ igt_assert_eq(bo, 0);
+ break;
+
+ case BO_ALLOC_PROTECT_OFF:
+ bo = create_protected_bo(i915, 4096, false, false, 0);
+ gem_close(i915, bo);
+ break;
+
+ case BO_ALLOC_PROTECT_ON:
+ bo = create_protected_bo(i915, 4096, true, true, 0);
+ gem_close(i915, bo);
+ break;
+
+ default:
+ igt_info("Skipping unknown buffer test_cfg = %d\n", test_cfg);
+ break;
+ }
+}
+
+static int create_ext_ioctl(int i915,
+ struct drm_i915_gem_context_create_ext *arg)
+{
+ int err;
+
+ err = 0;
+ if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
+ err = -errno;
+ igt_assume(err);
+ }
+
+ errno = 0;
+ return err;
+}
+
+static uint32_t create_protected_ctx(int i915, bool with_protected_param,
+ bool protected_is_true,
+ bool with_recoverable_param,
+ bool recoverable_is_true,
+ int expected_return)
+{
+ int ret;
+
+ struct drm_i915_gem_context_create_ext_setparam p_prot = {
+ .base = {
+ .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ .next_extension = 0,
+ },
+ .param = {
+ .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+ .value = 0,
+ }
+ };
+ struct drm_i915_gem_context_create_ext_setparam p_norecover = {
+ .base = {
+ .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ .next_extension = 0,
+ },
+ .param = {
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ }
+ };
+ struct drm_i915_gem_context_create_ext create = {
+ .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ .extensions = 0,
+ };
+
+ p_prot.param.value = protected_is_true;
+ p_norecover.param.value = recoverable_is_true;
+
+ if (with_protected_param && with_recoverable_param) {
+ create.extensions = to_user_pointer(&(p_norecover.base));
+ p_norecover.base.next_extension =
+ to_user_pointer(&(p_prot.base));
+ } else if (!with_protected_param && with_recoverable_param) {
+ create.extensions = to_user_pointer(&(p_norecover.base));
+ p_norecover.base.next_extension = 0;
+ } else if (with_protected_param && !with_recoverable_param) {
+ create.extensions = to_user_pointer(&(p_prot.base));
+ p_prot.base.next_extension = 0;
+ } else if (!with_protected_param && !with_recoverable_param) {
+ create.flags = 0;
+ }
+
+ ret = create_ext_ioctl(i915, &create);
+ igt_assert_eq(ret, expected_return);
+
+ return create.ctx_id;
+}
+
+#define CHANGE_PARAM_PROTECTED 0x0001
+#define CHANGE_PARAM_RECOVERY 0x0002
+static void modify_ctx_protected_param(int i915, uint32_t ctx_id,
+ uint32_t change_param_mask,
+ bool param_value, int expected_return)
+{
+ int ret;
+
+ struct drm_i915_gem_context_param ctx_param = {
+ .ctx_id = ctx_id,
+ .param = 0,
+ .value = 0,
+ };
+
+ if (change_param_mask == CHANGE_PARAM_PROTECTED) {
+ ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
+ ctx_param.value = (int)param_value;
+ } else if (change_param_mask == CHANGE_PARAM_RECOVERY) {
+ ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
+ ctx_param.value = (int)param_value;
+ } else {
+ return;
+ }
+
+ ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &ctx_param);
+
+ igt_assert_eq(ret, expected_return);
+}
+
+static void assert_ctx_protected_param(int i915, uint32_t ctx_id,
+ bool is_protected)
+{
+ int ret;
+
+ struct drm_i915_gem_context_param ctx_param = {
+ .ctx_id = ctx_id,
+ .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+ };
+
+ ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+ igt_assert_eq(ret, 0);
+ igt_assert_eq(ctx_param.value, (int)is_protected);
+}
+
+static void assert_ctx_recovery_param(int i915, uint32_t ctx_id,
+ bool is_recoverable)
+{
+ int ret;
+
+ struct drm_i915_gem_context_param ctx_param = {
+ .ctx_id = ctx_id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ };
+
+ ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+ igt_assert_eq(ret, 0);
+ igt_assert_eq(ctx_param.value, (int)is_recoverable);
+}
+
+static void test_create_protected_context(int i915, uint32_t test_cfg)
+{
+ uint32_t ctx;
+
+ switch (test_cfg) {
+ case CTX_ALLOC_NO_HW_SUPPORT:
+ ctx = create_protected_ctx(i915, true, true, true, false,
+ -ENODEV);
+ igt_assert_eq(ctx, 0);
+ case CTX_ALLOC_RECOVER_OFF_PROTECT_OFF:
+ ctx = create_protected_ctx(i915, true, false, true, false, 0);
+ assert_ctx_protected_param(i915, ctx, false);
+ assert_ctx_recovery_param(i915, ctx, false);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ case CTX_ALLOC_RECOVER_OFF_PROTECT_ON:
+ ctx = create_protected_ctx(i915, true, true, true, false, 0);
+ assert_ctx_protected_param(i915, ctx, true);
+ assert_ctx_recovery_param(i915, ctx, false);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ case CTX_ALLOC_RECOVER_ON_PROTECT_OFF:
+ ctx = create_protected_ctx(i915, true, false, true, true, 0);
+ assert_ctx_protected_param(i915, ctx, false);
+ assert_ctx_recovery_param(i915, ctx, true);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ case CTX_ALLOC_RECOVER_ON_PROTECT_ON:
+ ctx = create_protected_ctx(i915, true, true, true, true,
+ -EPERM);
+ igt_assert_eq(ctx, 0);
+ ctx = create_protected_ctx(i915, true, true, false, false,
+ -EPERM);
+ igt_assert_eq(ctx, 0);
+ break;
+
+ case CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON:
+ ctx = create_protected_ctx(i915, true, true, true, false, 0);
+ assert_ctx_protected_param(i915, ctx, true);
+ assert_ctx_recovery_param(i915, ctx, false);
+ modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
+ true, -EPERM);
+ assert_ctx_recovery_param(i915, ctx, false);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ case CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF:
+ ctx = create_protected_ctx(i915, true, true, true, false, 0);
+ assert_ctx_protected_param(i915, ctx, true);
+ assert_ctx_recovery_param(i915, ctx, false);
+ modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
+ false, -EPERM);
+ assert_ctx_protected_param(i915, ctx, true);
+ assert_ctx_recovery_param(i915, ctx, false);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ case CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID:
+ ctx = create_protected_ctx(i915, true, true, true, false, 0);
+ assert_ctx_protected_param(i915, ctx, true);
+ assert_ctx_recovery_param(i915, ctx, false);
+ modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
+ true, -EPERM);
+ modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
+ false, -EPERM);
+ assert_ctx_protected_param(i915, ctx, true);
+ assert_ctx_recovery_param(i915, ctx, false);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ case CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID:
+ ctx = create_protected_ctx(i915, false, false, false, false, 0);
+ assert_ctx_protected_param(i915, ctx, false);
+ assert_ctx_recovery_param(i915, ctx, true);
+ modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
+ false, 0);
+ modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
+ true, -EPERM);
+ assert_ctx_protected_param(i915, ctx, false);
+ assert_ctx_recovery_param(i915, ctx, false);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ default:
+ igt_info("Skipping unknown context test_cfg = %d\n", test_cfg);
+ break;
+ }
+}
+
+igt_main
+{
+ int i915 = -1;
+ bool pxp_supported = false;
+
+ igt_fixture
+ {
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require(i915);
+ igt_require_gem(i915);
+ pxp_supported = is_pxp_hw_supported(i915);
+ }
+
+ igt_subtest_group {
+ igt_fixture {
+ igt_require((pxp_supported == 0));
+ }
+
+ igt_describe("Verify protected buffer on unsupported hw:");
+ igt_subtest("hw-rejects-pxp-buffer")
+ test_create_protected_buffer(i915,
+ BO_ALLOC_NO_HW_SUPPORT);
+ igt_describe("Verify protected context on unsupported hw:");
+ igt_subtest("hw-rejects-pxp-context")
+ test_create_protected_context(i915,
+ CTX_ALLOC_NO_HW_SUPPORT);
+ }
+
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(pxp_supported);
+ }
+
+ igt_describe("Verify protected buffer on supported hw:");
+ igt_subtest("create-regular-buffer")
+ test_create_protected_buffer(i915,
+ BO_ALLOC_PROTECT_OFF);
+ igt_subtest("create-protected-buffer")
+ test_create_protected_buffer(i915, BO_ALLOC_PROTECT_ON);
+
+ igt_describe("Verify protected context on supported hw:");
+ igt_subtest("create-regular-context-1")
+ test_create_protected_context(
+ i915, CTX_ALLOC_RECOVER_OFF_PROTECT_OFF);
+ igt_subtest("create-regular-context-2")
+ test_create_protected_context(
+ i915, CTX_ALLOC_RECOVER_ON_PROTECT_OFF);
+ igt_subtest("fail-invalid-protected-context")
+ test_create_protected_context(
+ i915, CTX_ALLOC_RECOVER_ON_PROTECT_ON);
+ igt_subtest("create-valid-protected-context")
+ test_create_protected_context(
+ i915, CTX_ALLOC_RECOVER_OFF_PROTECT_ON);
+
+ igt_describe("Verify protected context integrity:");
+ igt_subtest("reject-modify-context-protection-on")
+ test_create_protected_context(
+ i915,
+ CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID);
+ igt_subtest("reject-modify-context-protection-off-1")
+ test_create_protected_context(
+ i915, CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON);
+ igt_subtest("reject-modify-context-protection-off-2")
+ test_create_protected_context(
+ i915, CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF);
+ igt_subtest("reject-modify-context-protection-off-3")
+ test_create_protected_context(
+ i915,
+ CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID);
+ }
+
+ igt_fixture {
+ close(i915);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index 825e0183..395bbbf5 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -233,6 +233,7 @@ i915_progs = [
'i915_pm_dc',
'i915_pm_rps',
'i915_pm_sseu',
+ 'i915_pxp',
'i915_query',
'i915_selftest',
'i915_suspend',
--
2.25.1
_______________________________________________
igt-dev mailing list
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 02/11] Add basic PXP testing of buffer and context alloc
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 02/11] Add basic PXP testing of buffer and context alloc Alan Previn
@ 2021-03-03 23:41 ` Chris Wilson
2021-03-04 17:12 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2021-03-03 23:41 UTC (permalink / raw)
To: Alan Previn, igt-dev; +Cc: Alan Previn
Quoting Alan Previn (2021-03-02 22:53:25)
> Test PXP capability support as well as the allocation of protected
> buffers and protected contexts.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
> tests/Makefile.sources | 3 +
> tests/i915/i915_pxp.c | 410 +++++++++++++++++++++++++++++++++++++++++
This is a GEM interface so gem_ctx_pxp or gem_exec_pxp, with gem_pxp as
a final if either the other two don't fit.
(Now when we move to i915/i915_gem_foo.c is another question).
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [igt-dev] [RFC i-g-t 02/11] Add basic PXP testing of buffer and context alloc
2021-03-03 23:41 ` Chris Wilson
@ 2021-03-04 17:12 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 26+ messages in thread
From: Teres Alexis, Alan Previn @ 2021-03-04 17:12 UTC (permalink / raw)
To: Chris Wilson, igt-dev
Thanks Chris - got it. Im assuming future kms subtest will still qualify for "gem_.." test name since its reacting on this GEM interface feature.
-----Original Message-----
From: Chris Wilson <chris@chris-wilson.co.uk>
Sent: Wednesday, March 3, 2021 3:42 PM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>; igt-dev@lists.freedesktop.org
Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Subject: Re: [igt-dev] [RFC i-g-t 02/11] Add basic PXP testing of buffer and context alloc
Quoting Alan Previn (2021-03-02 22:53:25)
> Test PXP capability support as well as the allocation of protected
> buffers and protected contexts.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
> tests/Makefile.sources | 3 +
> tests/i915/i915_pxp.c | 410
> +++++++++++++++++++++++++++++++++++++++++
This is a GEM interface so gem_ctx_pxp or gem_exec_pxp, with gem_pxp as a final if either the other two don't fit.
(Now when we move to i915/i915_gem_foo.c is another question).
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] [RFC i-g-t 03/11] Add PXP attributes into lib batchbuffer and buffer structs
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 01/11] Sync i915_drm.h UAPI for PXP Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 02/11] Add basic PXP testing of buffer and context alloc Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint Alan Previn
` (9 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Eventually when we get to testing PXP rendering capability,
we can reuse lib's rendercopy feature. However to do that,
we need to pass information about PXP-session-enablement
and which buffers are protected.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
lib/intel_batchbuffer.h | 7 +++++++
lib/intel_bufops.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 76989eaa..3ef9e30d 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -437,6 +437,12 @@ typedef void (*igt_media_spinfunc_t)(int i915,
igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
+struct igt_pxp {
+ bool enabled;
+ int apptype;
+ uint32_t appid;
+};
+
/*
* Batchbuffer without libdrm dependency
*/
@@ -459,6 +465,7 @@ struct intel_bb {
bool supports_48b_address;
uint32_t ctx;
+ struct igt_pxp pxp;
/* Cache */
void *root;
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 8debe7f2..0a272eaa 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -41,6 +41,9 @@ struct intel_buf {
uint32_t *ptr;
bool cpu_write;
+ /* Content Protection*/
+ bool is_protected;
+
/* For debugging purposes */
char name[INTEL_BUF_NAME_MAXSIZE + 1];
};
--
2.25.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (2 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 03/11] Add PXP attributes into lib batchbuffer and buffer structs Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-03 23:50 ` Chris Wilson
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 05/11] Add MI_SET_APPID instruction definition Alan Previn
` (8 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
As a control checkpoint, allocate buffers to be used
as texture and render target in the 3d engine for a
regular src to dest copy blit and verify buffer pixels.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
tests/i915/i915_pxp.c | 181 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 181 insertions(+)
diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
index 40a817b2..f12ca3d5 100644
--- a/tests/i915/i915_pxp.c
+++ b/tests/i915/i915_pxp.c
@@ -28,6 +28,11 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
#define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
#define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
+/* test-configs for protected rendering operations */
+#define COPY3D_BASELINE_SRC_TO_DST 1
+#define COPY3D_PROTECTED_SRC_TO_PROTDST 2
+#define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
+
static bool is_pxp_hw_supported(int i915)
{
uint32_t gen;
@@ -333,10 +338,172 @@ static void test_create_protected_context(int i915, uint32_t test_cfg)
}
}
+static void fill_bo_content(int i915, uint32_t bo,
+ uint32_t size, uint32_t initcolor)
+{
+ uint32_t *ptr, *ptrtmp;
+ int loop = 0;
+
+ ptr = gem_mmap__cpu_coherent(i915, bo, 0,
+ size, PROT_WRITE);
+ igt_assert(ptr);
+ ptrtmp = ptr;
+
+ /* read and count all dword matches till size */
+ while (loop++ < (size/4)) {
+ *ptrtmp = initcolor;
+ ++ptrtmp;
+ }
+
+ igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+#define COMPARE_COLOR_READIBLE 1
+#define COMPARE_COLOR_UNREADIBLE 2
+#define COMPARE_N_PIXELS_VERBOSELY 0
+static void assert_bo_content_check(int i915, uint32_t bo,
+ int compare_op, uint32_t size, uint32_t color)
+{
+ uint32_t *ptr, *ptrtmp;
+ int loop = 0, num_matches = 0;
+ uint32_t value;
+ bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+
+ ptr = gem_mmap__cpu_coherent(i915, bo, 0,
+ size, PROT_READ);
+ igt_assert(ptr);
+ ptrtmp = ptr;
+
+ if (COMPARE_N_PIXELS_VERBOSELY) {
+ igt_info("--------->>>\n");
+ while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
+ value = *ptrtmp;
+ igt_info("Color read = 0x%08x ", value);
+ igt_info("expected %c= 0x%08x)\n",
+ op_readible?'=':'!', color);
+ ++ptrtmp;
+ ++loop;
+ }
+ igt_info("<<<---------\n");
+ ptrtmp = ptr;
+ loop = 0;
+ }
+
+ /*count all pixels for matches */
+ while (loop++ < (size/4)) {
+ value = *ptrtmp;
+ if (value == color)
+ ++num_matches;
+ ++ptrtmp;
+ }
+
+ if (op_readible)
+ igt_assert_eq(num_matches, (size/4));
+ else
+ igt_assert_eq(num_matches, 0);
+
+ igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
+ uint32_t size, uint32_t init_color)
+{
+ uint32_t bo;
+
+ bo = create_protected_bo(i915, size,
+ protected, protected, 0);
+ igt_assert(bo);
+ fill_bo_content(i915, bo, size, init_color);
+ assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
+ size, init_color);
+
+ return bo;
+}
+
+/* Rendering tests surface attributes, keep it simple:
+ * page aligned width==stride, thus, and size
+ */
+#define TSTSURF_WIDTH 1024
+#define TSTSURF_HEIGHT 128
+#define TSTSURF_BYTESPP 4
+#define TSTSURF_STRIDE (TSTSURF_WIDTH*TSTSURF_BYTESPP)
+#define TSTSURF_SIZE (TSTSURF_STRIDE*TSTSURF_HEIGHT)
+#define TSTSURF_FILLCOLOR1 0xfaceface
+#define TSTSURF_INITCOLOR1 0x12341234
+
+static void test_render_protected_buffer(int i915, uint32_t test_cfg)
+{
+ uint32_t ctx, srcbo, dstbo;
+ struct intel_buf *srcbuf, *dstbuf;
+ struct buf_ops *bops;
+ struct intel_bb *ibb;
+ uint32_t devid;
+ igt_render_copyfunc_t rendercopy;
+
+ devid = intel_get_drm_devid(i915);
+ igt_assert(devid);
+
+ rendercopy = igt_get_render_copyfunc(devid);
+ igt_assert(rendercopy);
+
+ bops = buf_ops_create(i915);
+ igt_assert(bops);
+
+ switch (test_cfg) {
+ case COPY3D_BASELINE_SRC_TO_DST:
+ /* Perform a regular 3d copy as a control checkpoint */
+ ctx = create_protected_ctx(i915, false, false,
+ false, false, 0);
+ assert_ctx_protected_param(i915, ctx, false);
+
+ dstbo = alloc_and_fill_dest_buff(i915, false,
+ TSTSURF_SIZE, TSTSURF_INITCOLOR1);
+ dstbuf = intel_buf_create_using_handle(bops, dstbo,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT,
+ TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+ srcbo = alloc_and_fill_dest_buff(i915, false,
+ TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+ srcbuf = intel_buf_create_using_handle(bops, srcbo,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT,
+ TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+ ibb = intel_bb_create_with_context(i915, ctx, 4096);
+ igt_assert(ibb);
+
+ gen12_render_copyfunc(ibb,
+ srcbuf, 0, 0,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT,
+ dstbuf, 0, 0);
+ gem_sync(i915, dstbo);
+
+ assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
+ TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+
+ intel_bb_destroy(ibb);
+ intel_buf_destroy(srcbuf);
+ gem_close(i915, srcbo);
+ intel_buf_destroy(dstbuf);
+ gem_close(i915, dstbo);
+ gem_context_destroy(i915, ctx);
+ break;
+
+ default:
+ igt_info("Skipping unknown render test_cfg = %d\n",
+ test_cfg);
+ break;
+ }
+
+ buf_ops_destroy(bops);
+}
+
+
igt_main
{
int i915 = -1;
bool pxp_supported = false;
+ igt_render_copyfunc_t rendercopy = NULL;
+ uint32_t devid = 0;
igt_fixture
{
@@ -403,6 +570,20 @@ igt_main
i915,
CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID);
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(pxp_supported);
+ devid = intel_get_drm_devid(i915);
+ igt_assert(devid);
+ rendercopy = igt_get_render_copyfunc(devid);
+ igt_require(rendercopy);
+ }
+
+ igt_describe("Verify protected render operations:");
+ igt_subtest("regular-baseline-src-copy-readible")
+ test_render_protected_buffer(i915,
+ COPY3D_BASELINE_SRC_TO_DST);
+ }
igt_fixture {
close(i915);
--
2.25.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint Alan Previn
@ 2021-03-03 23:50 ` Chris Wilson
2021-03-04 17:14 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2021-03-03 23:50 UTC (permalink / raw)
To: Alan Previn, igt-dev; +Cc: Alan Previn
Quoting Alan Previn (2021-03-02 22:53:27)
> As a control checkpoint, allocate buffers to be used
> as texture and render target in the 3d engine for a
> regular src to dest copy blit and verify buffer pixels.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
> tests/i915/i915_pxp.c | 181 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 181 insertions(+)
>
> diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
> index 40a817b2..f12ca3d5 100644
> --- a/tests/i915/i915_pxp.c
> +++ b/tests/i915/i915_pxp.c
> @@ -28,6 +28,11 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
> #define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
> #define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
>
> +/* test-configs for protected rendering operations */
> +#define COPY3D_BASELINE_SRC_TO_DST 1
> +#define COPY3D_PROTECTED_SRC_TO_PROTDST 2
> +#define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
> +
> static bool is_pxp_hw_supported(int i915)
> {
> uint32_t gen;
> @@ -333,10 +338,172 @@ static void test_create_protected_context(int i915, uint32_t test_cfg)
> }
> }
>
> +static void fill_bo_content(int i915, uint32_t bo,
> + uint32_t size, uint32_t initcolor)
> +{
> + uint32_t *ptr, *ptrtmp;
> + int loop = 0;
> +
> + ptr = gem_mmap__cpu_coherent(i915, bo, 0,
> + size, PROT_WRITE);
> + igt_assert(ptr);
Already done.
So the map here is in the WB, but the data may not be in the CPU cache
nor properly tracked as the buffer may not be cache coherent.
Same for the check.
Use gem_mmap__device_coherent() by default and cpu_coherent only when
you want to handle the cache coherency.
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint
2021-03-03 23:50 ` Chris Wilson
@ 2021-03-04 17:14 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 26+ messages in thread
From: Teres Alexis, Alan Previn @ 2021-03-04 17:14 UTC (permalink / raw)
To: Chris Wilson, igt-dev
Thanks Chris - will fix to gem_mmap__device_coherent().
-----Original Message-----
From: Chris Wilson <chris@chris-wilson.co.uk>
Sent: Wednesday, March 3, 2021 3:51 PM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>; igt-dev@lists.freedesktop.org
Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Subject: Re: [igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint
Quoting Alan Previn (2021-03-02 22:53:27)
> As a control checkpoint, allocate buffers to be used as texture and
> render target in the 3d engine for a regular src to dest copy blit and
> verify buffer pixels.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
> tests/i915/i915_pxp.c | 181
> ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 181 insertions(+)
>
> diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c index
> 40a817b2..f12ca3d5 100644
> --- a/tests/i915/i915_pxp.c
> +++ b/tests/i915/i915_pxp.c
> @@ -28,6 +28,11 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
> #define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8 #define
> CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
>
> +/* test-configs for protected rendering operations */ #define
> +COPY3D_BASELINE_SRC_TO_DST 1 #define COPY3D_PROTECTED_SRC_TO_PROTDST
> +2 #define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
> +
> static bool is_pxp_hw_supported(int i915) {
> uint32_t gen;
> @@ -333,10 +338,172 @@ static void test_create_protected_context(int i915, uint32_t test_cfg)
> }
> }
>
> +static void fill_bo_content(int i915, uint32_t bo,
> + uint32_t size, uint32_t initcolor) {
> + uint32_t *ptr, *ptrtmp;
> + int loop = 0;
> +
> + ptr = gem_mmap__cpu_coherent(i915, bo, 0,
> + size, PROT_WRITE);
> + igt_assert(ptr);
Already done.
So the map here is in the WB, but the data may not be in the CPU cache nor properly tracked as the buffer may not be cache coherent.
Same for the check.
Use gem_mmap__device_coherent() by default and cpu_coherent only when you want to handle the cache coherency.
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] [RFC i-g-t 05/11] Add MI_SET_APPID instruction definition
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (3 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy Alan Previn
` (7 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Add MI_SET_APPID instruction and param definitions
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
lib/intel_reg.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ac1fc6cb..553f4839 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define CTXT_PALETTE_SAVE_DISABLE (1<<3)
#define CTXT_PALETTE_RESTORE_DISABLE (1<<2)
+#define MI_SET_APPID (0x0e<<23)
+#define APPID_CTXSAVE_INHIBIT (1<<8)
+#define APPID_CTXREST_INHIBIT (1<<9)
+#define DISPLAY_APPTYPE (0)
+#define TRANSCODE_APPTYPE (1)
+#define APPTYPE(n) ((n & 0x1)<<7)
+#define APPID(n) (n & 0x7f)
+
+
/* Dword 0 */
#define MI_VERTEX_BUFFER (0x17<<23)
#define MI_VERTEX_BUFFER_IDX(x) (x<<20)
--
2.25.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (4 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 05/11] Add MI_SET_APPID instruction definition Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-03 23:55 ` Chris Wilson
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 07/11] Add subtest to copy raw source to protected dest Alan Previn
` (6 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
1. In _gen9_render_op, check if the incoming batchbuffer
was marked with pxp enabled. If so, insert MI_SET_APPID
along with PIPE_CONTROL instructions at the start and
end of the rendering operation in the command buffer.
2. The two PIPE_CONTROLs will enable protected memory
at the start of the batch and disabling protected
memory at the end of it. These PIPE_CONTROLs require a
Post-Sync operation with a write to memory.
3. In order to satisfy #2, _gen9_render_op shall
allocate and pin a bo that is referenced by the
PIPE_CONTROL PostSync write to memory.
4. _gen9_render_op shall check the incoming surface
buffers for "is_protected" flag and if its set, it
will mark the SURFACE_STATE's MOCS field accordingly.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
lib/rendercopy_gen9.c | 123 +++++++++++++++++++++++++++++++++++++++---
1 file changed, 116 insertions(+), 7 deletions(-)
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index eecf73d3..705f26a2 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -19,7 +19,8 @@
#include "intel_bufops.h"
#include "intel_batchbuffer.h"
#include "intel_io.h"
-#include "rendercopy.h"
+#include "igt.h"
+#include "i915/gem.h"
#include "gen9_render.h"
#include "intel_reg.h"
#include "igt_aux.h"
@@ -152,6 +153,8 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
ss->ss0.tiled_mode = 3;
ss->ss1.memory_object_control = I915_MOCS_PTE << 1;
+ if (buf->is_protected)
+ ss->ss1.memory_object_control |= 1;
if (buf->tiling == I915_TILING_Yf)
ss->ss5.trmode = 1;
@@ -873,6 +876,89 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset)
intel_bb_out(ibb, 0); /* index buffer offset, ignored */
}
+#define GFX_OP_PIPE_CONTROL ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_BEFORE 0x1234fed0
+#define PS_OP_TAG_AFTER 0x5678cbaf
+static void gen12_emit_pxp_state(struct intel_bb *ibb, bool enable,
+ struct intel_buf *fenceb)
+{
+ uint32_t pipe_ctl_flags;
+ uint32_t set_app_id, ps_op_id;
+
+ if (ibb->pxp.enabled) {
+ if (enable) {
+ pipe_ctl_flags = PIPE_CONTROL_FLUSH_ENABLE;
+ intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+ intel_bb_out(ibb, pipe_ctl_flags);
+
+ set_app_id = MI_SET_APPID |
+ APPTYPE(ibb->pxp.apptype) |
+ APPID(ibb->pxp.appid);
+ intel_bb_out(ibb, set_app_id);
+
+ pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_ENABLE;
+ ps_op_id = PS_OP_TAG_BEFORE;
+ } else {
+ pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_DISABLE;
+ ps_op_id = PS_OP_TAG_AFTER;
+ }
+ pipe_ctl_flags |= (PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_DATA_CACHE_INVALIDATE |
+ PIPE_CONTROL_POST_SYNC_OP);
+ intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+ intel_bb_out(ibb, pipe_ctl_flags);
+ intel_bb_emit_reloc(ibb, fenceb->handle,
+ 0, I915_GEM_DOMAIN_COMMAND,
+ (enable?0:8), fenceb->addr.offset);
+ intel_bb_out(ibb, ps_op_id);
+ intel_bb_out(ibb, ps_op_id);
+ }
+}
+
+
+static void assert_pxp_ps_op_bo_completed(int i915, uint32_t bo,
+ uint32_t maptype)
+{
+ uint32_t *ptr;
+ uint32_t success_mask = 0x0;
+
+ switch (maptype) {
+ case I915_GEM_DOMAIN_CPU:
+ ptr = gem_mmap__cpu(i915, bo, 0, 4096, PROT_READ);
+ gem_set_domain(i915, bo, I915_GEM_DOMAIN_CPU,
+ I915_GEM_DOMAIN_CPU);
+ break;
+ case I915_GEM_DOMAIN_GTT:
+ ptr = gem_mmap__gtt(i915, bo, 4096, PROT_READ);
+ gem_set_domain(i915, bo, I915_GEM_DOMAIN_GTT,
+ I915_GEM_DOMAIN_GTT);
+ break;
+ default:
+ case I915_GEM_DOMAIN_WC:
+ ptr = gem_mmap__device_coherent(i915, bo, 0, 4096, PROT_READ);
+ gem_set_domain(i915, bo, I915_GEM_DOMAIN_WC,
+ I915_GEM_DOMAIN_WC);
+ break;
+ }
+ igt_assert(ptr);
+ if (ptr[0] == PS_OP_TAG_BEFORE && ptr[1] == PS_OP_TAG_BEFORE)
+ success_mask |= 0x1;
+ if (ptr[2] == PS_OP_TAG_AFTER && ptr[3] == PS_OP_TAG_AFTER)
+ success_mask |= 0x2;
+
+ igt_assert_eq(success_mask, 0x3);
+ igt_assert(gem_munmap(ptr, 4096) == 0);
+}
+
/* The general rule is if it's named gen6 it is directly copied from
* gen6_render_copyfunc.
*
@@ -922,6 +1008,16 @@ void _gen9_render_op(struct intel_bb *ibb,
uint32_t vertex_buffer;
uint32_t aux_pgtable_state;
bool fast_clear = !src;
+ struct intel_buf fenceb;
+ struct buf_ops *fencebops;
+
+ if (ibb->pxp.enabled) {
+ fencebops = buf_ops_create(ibb->i915);
+ igt_assert(fencebops);
+ intel_buf_init(fencebops, &fenceb,
+ 1024, 4, 32, 0, I915_TILING_NONE, 0);
+ intel_bb_add_intel_buf(ibb, &fenceb, true);
+ }
if (!fast_clear)
igt_assert(src->bpp == dst->bpp);
@@ -952,6 +1048,9 @@ void _gen9_render_op(struct intel_bb *ibb,
/* TODO: there is other state which isn't setup */
intel_bb_ptr_set(ibb, 0);
+ if (ibb->pxp.enabled)
+ gen12_emit_pxp_state(ibb, true, &fenceb);
+
/* Start emitting the commands. The order roughly follows the mesa blorp
* order */
intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
@@ -963,13 +1062,12 @@ void _gen9_render_op(struct intel_bb *ibb,
for (int i = 0; i < 4; i++) {
intel_bb_out(ibb, MI_STORE_DWORD_IMM);
intel_bb_emit_reloc(ibb, dst->handle,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst->cc.offset + i*sizeof(float),
- dst->addr.offset);
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ dst->cc.offset + i*sizeof(float),
+ dst->addr.offset);
intel_bb_out(ibb, *(uint32_t*)&clear_color[i]);
- }
- }
-
+ }
+ }
gen8_emit_sip(ibb);
@@ -1023,10 +1121,21 @@ void _gen9_render_op(struct intel_bb *ibb,
gen8_emit_vf_topology(ibb);
gen8_emit_primitive(ibb, vertex_buffer);
+ if (ibb->pxp.enabled)
+ gen12_emit_pxp_state(ibb, false, &fenceb);
+
intel_bb_emit_bbe(ibb);
intel_bb_exec(ibb, intel_bb_offset(ibb),
I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
dump_batch(ibb);
+
+ if (ibb->pxp.enabled) {
+ gem_sync(ibb->i915, fenceb.handle);
+ assert_pxp_ps_op_bo_completed(ibb->i915,
+ fenceb.handle, I915_GEM_DOMAIN_WC);
+ buf_ops_destroy(fencebops);
+ }
+
intel_bb_reset(ibb, false);
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy Alan Previn
@ 2021-03-03 23:55 ` Chris Wilson
2021-03-18 23:34 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2021-03-03 23:55 UTC (permalink / raw)
To: Alan Previn, igt-dev; +Cc: Alan Previn
Quoting Alan Previn (2021-03-02 22:53:29)
> 1. In _gen9_render_op, check if the incoming batchbuffer
> was marked with pxp enabled. If so, insert MI_SET_APPID
> along with PIPE_CONTROL instructions at the start and
> end of the rendering operation in the command buffer.
>
> 2. The two PIPE_CONTROLs will enable protected memory
> at the start of the batch and disabling protected
> memory at the end of it. These PIPE_CONTROLs require a
> Post-Sync operation with a write to memory.
>
> 3. In order to satisfy #2, _gen9_render_op shall
> allocate and pin a bo that is referenced by the
> PIPE_CONTROL PostSync write to memory.
Or, just have the caller do 1-3 once for its protected context.
Call it something like intel_bb_enable_pxp(), intel_bb_set_pxp if it
should be reversible.
> + if (ibb->pxp.enabled) {
> + gem_sync(ibb->i915, fenceb.handle);
No implicit syncs, ever. That will hide too may issues.
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy
2021-03-03 23:55 ` Chris Wilson
@ 2021-03-18 23:34 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 26+ messages in thread
From: Teres Alexis, Alan Previn @ 2021-03-18 23:34 UTC (permalink / raw)
To: Chris Wilson, igt-dev
Hi there Chris,
WRT below review feedback:
"... just have the caller do 1-3 once for its protected context. Call it something like intel_bb_enable_pxp(), intel_bb_set_pxp if it should be reversible.",..
If we are thinking about having this new "intel_bb_set_pxp" function to dispatch the MI_SET_APPID and PIPE_CONTROL HW instructions out to HW at the time its called, it wouldn't work. The reason for this is because the HW requires that enabling protected memory access and disabling protected memory access must be programmed in pairs within the same "dispatch of commands" to HW. I've tested and confirmed this. I was thinking about prepending and appending the ibb used by _gen9_render_op (at the point when it calls intel_bb_exec) but that doesn’t look scalable since the rendering code is manipulating the ibb pointers and splitting the batchbuffer bo to be used for both the 3d state as well as 3d instruction. It might be possible to create and chain batches at the time of intel_bb_exec depending on the pxp state but this would be a decent amount of re-write of the intel_batchbuffer init + cleanup code too. Are you okay with using the intel_bb_set_pxp to only mark the intended pxp state but still have the _gen9_render_op actually trigger those enable-disable instruction pairs?
...alan
-----Original Message-----
From: Chris Wilson <chris@chris-wilson.co.uk>
Sent: Wednesday, March 3, 2021 3:56 PM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>; igt-dev@lists.freedesktop.org
Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Subject: Re: [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy
Quoting Alan Previn (2021-03-02 22:53:29)
> 1. In _gen9_render_op, check if the incoming batchbuffer
> was marked with pxp enabled. If so, insert MI_SET_APPID
> along with PIPE_CONTROL instructions at the start and
> end of the rendering operation in the command buffer.
>
> 2. The two PIPE_CONTROLs will enable protected memory
> at the start of the batch and disabling protected
> memory at the end of it. These PIPE_CONTROLs require a
> Post-Sync operation with a write to memory.
>
> 3. In order to satisfy #2, _gen9_render_op shall
> allocate and pin a bo that is referenced by the
> PIPE_CONTROL PostSync write to memory.
Or, just have the caller do 1-3 once for its protected context.
Call it something like intel_bb_enable_pxp(), intel_bb_set_pxp if it should be reversible.
> + if (ibb->pxp.enabled) {
> + gem_sync(ibb->i915, fenceb.handle);
No implicit syncs, ever. That will hide too may issues.
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] [RFC i-g-t 07/11] Add subtest to copy raw source to protected dest
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (5 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 08/11] Add test where both src and dest are protected Alan Previn
` (5 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Add subtest to 3d-copy raw source buffer (with
known readible content) to a destination buffer
marked as protected with a protected session using
default session keys. The destination buffer is
verified to be different from the source (when
read via CPU) because its encrypted.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
tests/i915/i915_pxp.c | 48 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
index f12ca3d5..e36da7ec 100644
--- a/tests/i915/i915_pxp.c
+++ b/tests/i915/i915_pxp.c
@@ -429,7 +429,9 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
#define TSTSURF_STRIDE (TSTSURF_WIDTH*TSTSURF_BYTESPP)
#define TSTSURF_SIZE (TSTSURF_STRIDE*TSTSURF_HEIGHT)
#define TSTSURF_FILLCOLOR1 0xfaceface
+#define TSTSURF_FILLCOLOR2 0xdeaddead
#define TSTSURF_INITCOLOR1 0x12341234
+#define TSTSURF_INITCOLOR2 0x56785678
static void test_render_protected_buffer(int i915, uint32_t test_cfg)
{
@@ -488,6 +490,49 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
gem_context_destroy(i915, ctx);
break;
+ case COPY3D_PROTECTED_SRC_TO_PROTDST:
+ /* Perform a protected render operation but only label
+ * the dest as protected. After rendering, the content
+ * should be encrypted
+ */
+ ctx = create_protected_ctx(i915, true, true,
+ true, false, 0);
+ assert_ctx_protected_param(i915, ctx, true);
+
+ dstbo = alloc_and_fill_dest_buff(i915, true,
+ TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+ dstbuf = intel_buf_create_using_handle(bops, dstbo,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT,
+ TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+ dstbuf->is_protected = true;
+
+ srcbo = alloc_and_fill_dest_buff(i915, false,
+ TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+ srcbuf = intel_buf_create_using_handle(bops, srcbo,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT,
+ TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+ ibb = intel_bb_create_with_context(i915, ctx, 4096);
+ igt_assert(ibb);
+
+ ibb->pxp.enabled = true;
+ ibb->pxp.apptype = DISPLAY_APPTYPE;
+ ibb->pxp.appid = I915_PROTECTED_CONTENT_DEFAULT_SESSION;
+
+ gen12_render_copyfunc(ibb, srcbuf, 0, 0,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+ gem_sync(i915, dstbo);
+
+ assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
+ TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+
+ intel_bb_destroy(ibb);
+ intel_buf_destroy(srcbuf);
+ gem_close(i915, srcbo);
+ intel_buf_destroy(dstbuf);
+ gem_close(i915, dstbo);
+ gem_context_destroy(i915, ctx);
+ break;
default:
igt_info("Skipping unknown render test_cfg = %d\n",
test_cfg);
@@ -583,6 +628,9 @@ igt_main
igt_subtest("regular-baseline-src-copy-readible")
test_render_protected_buffer(i915,
COPY3D_BASELINE_SRC_TO_DST);
+ igt_subtest("protected-raw-src-copy-not-readible")
+ test_render_protected_buffer(i915,
+ COPY3D_PROTECTED_SRC_TO_PROTDST);
}
igt_fixture {
--
2.25.1
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^ permalink raw reply related [flat|nested] 26+ messages in thread* [igt-dev] [RFC i-g-t 08/11] Add test where both src and dest are protected
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (6 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 07/11] Add subtest to copy raw source to protected dest Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-03 23:56 ` Chris Wilson
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 09/11] Add test to verify session key renewed after suspend-resume cycle Alan Previn
` (4 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
When both the source and destination surfaces are
protected, the destination pixel result of the 3d
copy operation would be the same as the source. By
appending this test case to the end of the prior
test (raw-src to protected-dest) and reusing the
previous' test destination as the current source,
we can prove the difference in results clearly
by repeating the same render operation but having
a src buffer that is protected in this case.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
lib/intel_batchbuffer.c | 12 +++++
lib/intel_batchbuffer.h | 2 +
tests/i915/i915_pxp.c | 117 ++++++++++++++++++++++++++++++++++------
3 files changed, 116 insertions(+), 15 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 8118dc94..819fd85d 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2193,6 +2193,18 @@ void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
}
+/**
+ * intel_bb_exec_noassert:
+ *
+ * Wrapper around intel_bb_exec but without assertion and
+ * GEM_EXEC ioctl return value is passed back to caller.
+ */
+int intel_bb_exec_noassert(struct intel_bb *ibb, uint32_t end_offset,
+ uint64_t flags, bool sync)
+{
+ return __intel_bb_exec(ibb, end_offset, flags, sync);
+}
+
/**
* intel_bb_get_object_address:
* @ibb: pointer to intel_bb
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 3ef9e30d..2748b3d3 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -634,6 +634,8 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
uint64_t flags, bool sync);
+int intel_bb_exec_noassert(struct intel_bb *ibb, uint32_t end_offset,
+ uint64_t flags, bool sync);
uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle);
bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf);
diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
index e36da7ec..2290fe34 100644
--- a/tests/i915/i915_pxp.c
+++ b/tests/i915/i915_pxp.c
@@ -360,31 +360,53 @@ static void fill_bo_content(int i915, uint32_t bo,
#define COMPARE_COLOR_READIBLE 1
#define COMPARE_COLOR_UNREADIBLE 2
+#define COMPARE_BUFFER_READIBLE 3
+#define COMPARE_BUFFER_UNREADIBLE 4
+#define COPY_BUFFER 5
+
#define COMPARE_N_PIXELS_VERBOSELY 0
static void assert_bo_content_check(int i915, uint32_t bo,
- int compare_op, uint32_t size, uint32_t color)
+ int compare_op, uint32_t size, uint32_t color, uint32_t *auxptr, int auxsize)
{
- uint32_t *ptr, *ptrtmp;
+ uint32_t *ptr, *ptrtmp, *auxtmp;
int loop = 0, num_matches = 0;
uint32_t value;
- bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+ bool op_readible = ((compare_op == COMPARE_COLOR_READIBLE) ||
+ (compare_op == COMPARE_BUFFER_READIBLE));
+ bool chk_buff = ((compare_op == COMPARE_BUFFER_READIBLE) ||
+ (compare_op == COMPARE_BUFFER_UNREADIBLE));
ptr = gem_mmap__cpu_coherent(i915, bo, 0,
size, PROT_READ);
igt_assert(ptr);
ptrtmp = ptr;
+ if (chk_buff) {
+ if (auxsize < size)
+ auxptr = NULL;
+ igt_assert(auxptr);
+ auxtmp = auxptr;
+ }
+
if (COMPARE_N_PIXELS_VERBOSELY) {
igt_info("--------->>>\n");
while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
value = *ptrtmp;
- igt_info("Color read = 0x%08x ", value);
- igt_info("expected %c= 0x%08x)\n",
- op_readible?'=':'!', color);
+ if (chk_buff)
+ color = *auxtmp;
+ if (compare_op == COPY_BUFFER)
+ igt_info("Color copy = 0x%08x\n", value);
+ else {
+ igt_info("Color read = 0x%08x ", value);
+ igt_info("expected %c= 0x%08x)\n",
+ op_readible?'=':'!', color);
+ }
+ ++auxtmp;
++ptrtmp;
++loop;
}
igt_info("<<<---------\n");
+ auxtmp = auxptr;
ptrtmp = ptr;
loop = 0;
}
@@ -392,8 +414,25 @@ static void assert_bo_content_check(int i915, uint32_t bo,
/*count all pixels for matches */
while (loop++ < (size/4)) {
value = *ptrtmp;
- if (value == color)
- ++num_matches;
+ switch (compare_op) {
+ case COMPARE_COLOR_READIBLE:
+ case COMPARE_COLOR_UNREADIBLE:
+ if (value == color)
+ ++num_matches;
+ break;
+ case COMPARE_BUFFER_READIBLE:
+ case COMPARE_BUFFER_UNREADIBLE:
+ if (value == (*auxtmp))
+ ++num_matches;
+ ++auxtmp;
+ break;
+ case COPY_BUFFER:
+ *auxtmp = value;
+ ++auxtmp;
+ break;
+ default:
+ break;
+ }
++ptrtmp;
}
@@ -415,7 +454,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
igt_assert(bo);
fill_bo_content(i915, bo, size, init_color);
assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
- size, init_color);
+ size, init_color, NULL, 0);
return bo;
}
@@ -432,15 +471,16 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
#define TSTSURF_FILLCOLOR2 0xdeaddead
#define TSTSURF_INITCOLOR1 0x12341234
#define TSTSURF_INITCOLOR2 0x56785678
-
+#define TSTSURF_INITCOLOR3 0xabcdabcd
static void test_render_protected_buffer(int i915, uint32_t test_cfg)
{
- uint32_t ctx, srcbo, dstbo;
- struct intel_buf *srcbuf, *dstbuf;
+ uint32_t ctx, srcbo, dstbo, dstbo2;
+ struct intel_buf *srcbuf, *dstbuf, *dstbuf2;
struct buf_ops *bops;
struct intel_bb *ibb;
uint32_t devid;
igt_render_copyfunc_t rendercopy;
+ uint32_t encrypted[TSTSURF_SIZE/TSTSURF_BYTESPP];
devid = intel_get_drm_devid(i915);
igt_assert(devid);
@@ -480,7 +520,7 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
gem_sync(i915, dstbo);
assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
- TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+ TSTSURF_SIZE, TSTSURF_FILLCOLOR1, NULL, 0);
intel_bb_destroy(ibb);
intel_buf_destroy(srcbuf);
@@ -491,6 +531,7 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
break;
case COPY3D_PROTECTED_SRC_TO_PROTDST:
+ case COPY3D_PROTECTED_PROTSRC_TO_PROTDST:
/* Perform a protected render operation but only label
* the dest as protected. After rendering, the content
* should be encrypted
@@ -524,13 +565,57 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
gem_sync(i915, dstbo);
assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
- TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+ TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
+
+ if (test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST) {
+ intel_bb_destroy(ibb);
+ intel_buf_destroy(srcbuf);
+ gem_close(i915, srcbo);
+ intel_buf_destroy(dstbuf);
+ gem_close(i915, dstbo);
+ gem_context_destroy(i915, ctx);
+ break;
+ }
+
+ /* For COPY3D_PROTECTED_PROTSRC_TO_PROTDST, reuse
+ * prior dst as the new-src and create a new dst2 as
+ * the new-dest. Take a copy of encrypted content
+ * from new-src for comparison after render operation.
+ * After the rendering, we should find no difference
+ * in content since both new-src and new-dest are
+ * labelled as encrypted. HW should read and decrypt
+ * new-src, perform the render and re-encrypt when
+ * going into new-dest
+ */
+ assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+ TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
+
+ dstbo2 = alloc_and_fill_dest_buff(i915, false,
+ TSTSURF_SIZE, TSTSURF_INITCOLOR3);
+ dstbuf2 = intel_buf_create_using_handle(bops, dstbo2,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT,
+ TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+ dstbuf2->is_protected = true;
+
+ dstbuf->is_protected = true;/*this time, src is protected*/
+ ibb->pxp.enabled = true;
+ ibb->pxp.apptype = DISPLAY_APPTYPE;
+ ibb->pxp.appid = I915_PROTECTED_CONTENT_DEFAULT_SESSION;
+
+ gen12_render_copyfunc(ibb, dstbuf, 0, 0,
+ TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf2, 0, 0);
+ gem_sync(i915, dstbo2);
+
+ assert_bo_content_check(i915, dstbo2, COMPARE_BUFFER_READIBLE,
+ TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
intel_bb_destroy(ibb);
intel_buf_destroy(srcbuf);
gem_close(i915, srcbo);
intel_buf_destroy(dstbuf);
gem_close(i915, dstbo);
+ intel_buf_destroy(dstbuf2);
+ gem_close(i915, dstbo2);
gem_context_destroy(i915, ctx);
break;
default:
@@ -542,7 +627,6 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
buf_ops_destroy(bops);
}
-
igt_main
{
int i915 = -1;
@@ -631,6 +715,9 @@ igt_main
igt_subtest("protected-raw-src-copy-not-readible")
test_render_protected_buffer(i915,
COPY3D_PROTECTED_SRC_TO_PROTDST);
+ igt_subtest("protected-encrypted-src-copy-not-readible")
+ test_render_protected_buffer(i915,
+ COPY3D_PROTECTED_PROTSRC_TO_PROTDST);
}
igt_fixture {
--
2.25.1
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 08/11] Add test where both src and dest are protected
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 08/11] Add test where both src and dest are protected Alan Previn
@ 2021-03-03 23:56 ` Chris Wilson
2021-03-04 17:32 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2021-03-03 23:56 UTC (permalink / raw)
To: Alan Previn, igt-dev; +Cc: Alan Previn
Quoting Alan Previn (2021-03-02 22:53:31)
> When both the source and destination surfaces are
> protected, the destination pixel result of the 3d
> copy operation would be the same as the source. By
> appending this test case to the end of the prior
> test (raw-src to protected-dest) and reusing the
> previous' test destination as the current source,
> we can prove the difference in results clearly
> by repeating the same render operation but having
> a src buffer that is protected in this case.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
> lib/intel_batchbuffer.c | 12 +++++
> lib/intel_batchbuffer.h | 2 +
> tests/i915/i915_pxp.c | 117 ++++++++++++++++++++++++++++++++++------
> 3 files changed, 116 insertions(+), 15 deletions(-)
>
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 8118dc94..819fd85d 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -2193,6 +2193,18 @@ void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
> igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync), 0);
> }
>
> +/**
> + * intel_bb_exec_noassert:
> + *
> + * Wrapper around intel_bb_exec but without assertion and
> + * GEM_EXEC ioctl return value is passed back to caller.
> + */
> +int intel_bb_exec_noassert(struct intel_bb *ibb, uint32_t end_offset,
> + uint64_t flags, bool sync)
> +{
> + return __intel_bb_exec(ibb, end_offset, flags, sync);
* blinks
It's called __intel_bb_exec() as is the pattern already established
across igt.
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 08/11] Add test where both src and dest are protected
2021-03-03 23:56 ` Chris Wilson
@ 2021-03-04 17:32 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 26+ messages in thread
From: Teres Alexis, Alan Previn @ 2021-03-04 17:32 UTC (permalink / raw)
To: Chris Wilson, igt-dev
Apologies for question: Are you suggesting I promote __intel_exec_bb into lib-headers to be reusable across IGT? (which works great - I just wasn’t sure if that was okay).
...alan
-----Original Message-----
From: Chris Wilson <chris@chris-wilson.co.uk>
Sent: Wednesday, March 3, 2021 3:57 PM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>; igt-dev@lists.freedesktop.org
Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Subject: Re: [igt-dev] [RFC i-g-t 08/11] Add test where both src and dest are protected
Quoting Alan Previn (2021-03-02 22:53:31)
> When both the source and destination surfaces are protected, the
> destination pixel result of the 3d copy operation would be the same as
> the source. By appending this test case to the end of the prior test
> (raw-src to protected-dest) and reusing the previous' test destination
> as the current source, we can prove the difference in results clearly
> by repeating the same render operation but having a src buffer that is
> protected in this case.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
> lib/intel_batchbuffer.c | 12 +++++
> lib/intel_batchbuffer.h | 2 +
> tests/i915/i915_pxp.c | 117 ++++++++++++++++++++++++++++++++++------
> 3 files changed, 116 insertions(+), 15 deletions(-)
>
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index
> 8118dc94..819fd85d 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -2193,6 +2193,18 @@ void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
> igt_assert_eq(__intel_bb_exec(ibb, end_offset, flags, sync),
> 0); }
>
> +/**
> + * intel_bb_exec_noassert:
> + *
> + * Wrapper around intel_bb_exec but without assertion and
> + * GEM_EXEC ioctl return value is passed back to caller.
> + */
> +int intel_bb_exec_noassert(struct intel_bb *ibb, uint32_t end_offset,
> + uint64_t flags, bool sync) {
> + return __intel_bb_exec(ibb, end_offset, flags, sync);
* blinks
It's called __intel_bb_exec() as is the pattern already established across igt.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] [RFC i-g-t 09/11] Add test to verify session key renewed after suspend-resume cycle
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (7 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 08/11] Add test where both src and dest are protected Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-03 23:59 ` Chris Wilson
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 10/11] Verify gem_execbuf fails with stale PXP context after teardown Alan Previn
` (3 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Add a subtest to verify that before and after a suspend-resume
cycle, repeating the same protected rendering operation yields
different encrypted output reflecting updated encryption keys
after auto-teardown.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
tests/i915/i915_pxp.c | 107 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 105 insertions(+), 2 deletions(-)
diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
index 2290fe34..11ca05df 100644
--- a/tests/i915/i915_pxp.c
+++ b/tests/i915/i915_pxp.c
@@ -6,6 +6,8 @@
#include <sys/ioctl.h>
#include "igt.h"
+#include "igt_device.h"
+#include "igt_sysfs.h"
#include "i915/gem.h"
IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
@@ -32,6 +34,19 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
#define COPY3D_BASELINE_SRC_TO_DST 1
#define COPY3D_PROTECTED_SRC_TO_PROTDST 2
#define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
+#define COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED 4
+
+/* test-configs for power-management triggered protected session teardown */
+#define SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE 1
+#define SESSION_PMSUSPEND_TEARDOWN_PROTCTX_BAN_CHK 2
+#define SESSION_PMSUSPEND_TEARDOWN_PROTCTX_BAN_EXEC 3
+#define SESSION_PMSUSPEND_TEARDOWN_PROTBO_BAN_EXEC 4
+
+/* Struct and defintions for power management. */
+struct powermgt_data {
+ int debugfsdir;
+ bool has_runtime_pm;
+};
static bool is_pxp_hw_supported(int i915)
{
@@ -472,7 +487,8 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
#define TSTSURF_INITCOLOR1 0x12341234
#define TSTSURF_INITCOLOR2 0x56785678
#define TSTSURF_INITCOLOR3 0xabcdabcd
-static void test_render_protected_buffer(int i915, uint32_t test_cfg)
+static void __test_render_protected_buffer(int i915, uint32_t test_cfg,
+ uint32_t *outpixels, int outsize)
{
uint32_t ctx, srcbo, dstbo, dstbo2;
struct intel_buf *srcbuf, *dstbuf, *dstbuf2;
@@ -532,6 +548,7 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
case COPY3D_PROTECTED_SRC_TO_PROTDST:
case COPY3D_PROTECTED_PROTSRC_TO_PROTDST:
+ case COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED:
/* Perform a protected render operation but only label
* the dest as protected. After rendering, the content
* should be encrypted
@@ -567,7 +584,12 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
- if (test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST) {
+ if (test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED)
+ assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+ TSTSURF_SIZE, 0, outpixels, outsize);
+
+ if ((test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST) ||
+ (test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED)) {
intel_bb_destroy(ibb);
intel_buf_destroy(srcbuf);
gem_close(i915, srcbo);
@@ -627,10 +649,75 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
buf_ops_destroy(bops);
}
+static void test_render_protected_buffer(int i915, uint32_t test_cfg)
+{
+ __test_render_protected_buffer(i915, test_cfg, NULL, 0);
+}
+
+static void init_powermgt_resources(int i915, struct powermgt_data *pm)
+{
+ pm->debugfsdir = igt_debugfs_dir(i915);
+ igt_require(pm->debugfsdir != -1);
+ pm->has_runtime_pm = igt_setup_runtime_pm(i915);
+ igt_require(pm->has_runtime_pm);
+
+}
+
+static void trigger_powermgt_suspend_cycle(int i915,
+ struct powermgt_data *pm)
+{
+ igt_pm_enable_sata_link_power_management();
+
+
+ igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_DEVICES);
+
+ igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
+ gem_test_engine(i915, I915_EXEC_RENDER);
+ while ((!igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_ACTIVE))) {
+ igt_info("Waited 10 secs for resume - kick render again!\n");
+ gem_test_engine(i915, I915_EXEC_RENDER);
+ }
+}
+
+static void test_protected_session_teardown(int i915, uint32_t test_cfg,
+ struct powermgt_data *pm)
+{
+ uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
+ uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
+ int matched_after_keychange = 0, loop = 0;
+
+ switch (test_cfg) {
+ case SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE:
+ __test_render_protected_buffer(i915,
+ COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED,
+ encrypted_pixels_b4, TSTSURF_SIZE);
+
+ trigger_powermgt_suspend_cycle(i915, pm);
+
+ __test_render_protected_buffer(i915,
+ COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED,
+ encrypted_pixels_aft, TSTSURF_SIZE);
+
+ while (loop < (TSTSURF_SIZE/TSTSURF_BYTESPP)) {
+ if (encrypted_pixels_b4[loop] ==
+ encrypted_pixels_aft[loop])
+ ++matched_after_keychange;
+ ++loop;
+ }
+ igt_assert_eq(matched_after_keychange, 0);
+ break;
+ default:
+ igt_info("Skipping unknown power-mgt test_cfg = %d\n",
+ test_cfg);
+ break;
+ }
+}
+
igt_main
{
int i915 = -1;
bool pxp_supported = false;
+ struct powermgt_data pm = {0};
igt_render_copyfunc_t rendercopy = NULL;
uint32_t devid = 0;
@@ -719,6 +806,22 @@ igt_main
test_render_protected_buffer(i915,
COPY3D_PROTECTED_PROTSRC_TO_PROTDST);
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(pxp_supported);
+ devid = intel_get_drm_devid(i915);
+ igt_assert(devid);
+ rendercopy = igt_get_render_copyfunc(devid);
+ igt_require(rendercopy);
+ init_powermgt_resources(i915, &pm);
+ }
+ igt_describe("Verify suspend-resume teardown management:");
+ igt_subtest("verify-pxp-key-change-after-suspend-resume") {
+ test_protected_session_teardown(i915,
+ SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE,
+ &pm);
+ }
+ }
igt_fixture {
close(i915);
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 09/11] Add test to verify session key renewed after suspend-resume cycle
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 09/11] Add test to verify session key renewed after suspend-resume cycle Alan Previn
@ 2021-03-03 23:59 ` Chris Wilson
2021-03-04 18:27 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2021-03-03 23:59 UTC (permalink / raw)
To: Alan Previn, igt-dev; +Cc: Alan Previn
Quoting Alan Previn (2021-03-02 22:53:32)
> +static void trigger_powermgt_suspend_cycle(int i915,
> + struct powermgt_data *pm)
> +{
> + igt_pm_enable_sata_link_power_management();
> +
> +
> + igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_DEVICES);
> +
> + igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
> + gem_test_engine(i915, I915_EXEC_RENDER);
> + while ((!igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_ACTIVE))) {
With an autosuspend delay of 0, this is not guaranteed to ever report
ACTIVE.
Just drop everything after wait_for_pm_status(SUSPENDED) as clearly
using the protected rendercopy must wake the device.
-Chris
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^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 09/11] Add test to verify session key renewed after suspend-resume cycle
2021-03-03 23:59 ` Chris Wilson
@ 2021-03-04 18:27 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 26+ messages in thread
From: Teres Alexis, Alan Previn @ 2021-03-04 18:27 UTC (permalink / raw)
To: Chris Wilson, igt-dev
Right - got it. Thanks.
...alan
-----Original Message-----
From: Chris Wilson <chris@chris-wilson.co.uk>
Sent: Wednesday, March 3, 2021 4:00 PM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>; igt-dev@lists.freedesktop.org
Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Subject: Re: [igt-dev] [RFC i-g-t 09/11] Add test to verify session key renewed after suspend-resume cycle
Quoting Alan Previn (2021-03-02 22:53:32)
> +static void trigger_powermgt_suspend_cycle(int i915,
> + struct powermgt_data *pm)
> +{
> + igt_pm_enable_sata_link_power_management();
> +
> +
> + igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
> + SUSPEND_TEST_DEVICES);
> +
> + igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
> + gem_test_engine(i915, I915_EXEC_RENDER);
> + while
> + ((!igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_ACTIVE))) {
With an autosuspend delay of 0, this is not guaranteed to ever report ACTIVE.
Just drop everything after wait_for_pm_status(SUSPENDED) as clearly using the protected rendercopy must wake the device.
-Chris
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] [RFC i-g-t 10/11] Verify gem_execbuf fails with stale PXP context after teardown
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (8 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 09/11] Add test to verify session key renewed after suspend-resume cycle Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 11/11] Verify gem_execbuf fails with stale PXP buffer " Alan Previn
` (2 subsequent siblings)
12 siblings, 0 replies; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Add a subtest to verify that reusing a stale protected context
in a gem_execbuff after a teardown (triggered by suspend-resume
cycle) shall fail with -EIO error.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
tests/i915/i915_pxp.c | 132 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
index 11ca05df..b8c82ea9 100644
--- a/tests/i915/i915_pxp.c
+++ b/tests/i915/i915_pxp.c
@@ -679,12 +679,107 @@ static void trigger_powermgt_suspend_cycle(int i915,
}
}
+#define GFX_OP_PIPE_CONTROL ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_BEFORE 0x1234fed0
+#define PS_OP_TAG_AFTER 0x5678cbaf
+static void emit_pipectrl(struct intel_bb *ibb,
+ struct intel_buf *fenceb, bool before)
+{
+ uint32_t pipe_ctl_flags = 0;
+ uint32_t ps_op_id;
+
+ intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+ intel_bb_out(ibb, pipe_ctl_flags);
+
+ if (before)
+ ps_op_id = PS_OP_TAG_BEFORE;
+ else
+ ps_op_id = PS_OP_TAG_AFTER;
+
+ pipe_ctl_flags = (PIPE_CONTROL_FLUSH_ENABLE |
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_POST_SYNC_OP);
+ intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+ intel_bb_out(ibb, pipe_ctl_flags);
+ intel_bb_emit_reloc(ibb, fenceb->handle,
+ 0, I915_GEM_DOMAIN_COMMAND,
+ (before?0:8), fenceb->addr.offset);
+ intel_bb_out(ibb, ps_op_id);
+ intel_bb_out(ibb, ps_op_id);
+ intel_bb_out(ibb, MI_NOOP);
+ intel_bb_out(ibb, MI_NOOP);
+}
+
+static void assert_pipectl_storedw_done(int i915, uint32_t bo,
+ uint32_t maptype)
+{
+ uint32_t *ptr;
+ uint32_t success_mask = 0x0;
+
+ switch (maptype) {
+ case I915_GEM_DOMAIN_CPU:
+ ptr = gem_mmap__cpu(i915, bo, 0, 4096, PROT_READ);
+ gem_set_domain(i915, bo, I915_GEM_DOMAIN_CPU,
+ I915_GEM_DOMAIN_CPU);
+ break;
+ case I915_GEM_DOMAIN_GTT:
+ ptr = gem_mmap__gtt(i915, bo, 4096, PROT_READ);
+ gem_set_domain(i915, bo, I915_GEM_DOMAIN_GTT,
+ I915_GEM_DOMAIN_GTT);
+ break;
+ default:
+ case I915_GEM_DOMAIN_WC:
+ ptr = gem_mmap__device_coherent(i915, bo, 0, 4096, PROT_READ);
+ gem_set_domain(i915, bo, I915_GEM_DOMAIN_WC,
+ I915_GEM_DOMAIN_WC);
+ break;
+ }
+ igt_assert(ptr);
+ if (ptr[0] == PS_OP_TAG_BEFORE && ptr[1] == PS_OP_TAG_BEFORE)
+ success_mask |= 0x1;
+
+ igt_assert_eq(success_mask, 0x1);
+ igt_assert(gem_munmap(ptr, 4096) == 0);
+}
+
+static void gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb,
+ uint32_t ctx, struct intel_buf *fence, int expected_gemexec_response)
+{
+ int execret;
+
+ intel_bb_ptr_set(ibb, 0);
+ intel_bb_add_intel_buf(ibb, fence, true);
+ emit_pipectrl(ibb, fence, true);
+ intel_bb_emit_bbe(ibb);
+ execret = intel_bb_exec_noassert(ibb, intel_bb_offset(ibb),
+ I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
+
+ igt_assert_eq(execret, expected_gemexec_response);
+ if (expected_gemexec_response == 0) {
+ gem_sync(ibb->i915, fence->handle);
+ assert_pipectl_storedw_done(i915,
+ fence->handle, I915_GEM_DOMAIN_WC);
+ }
+}
+
static void test_protected_session_teardown(int i915, uint32_t test_cfg,
struct powermgt_data *pm)
{
uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
int matched_after_keychange = 0, loop = 0;
+ uint32_t ctx, fencebo;
+ struct intel_buf *fencebuf;
+ struct buf_ops *bops;
+ struct intel_bb *ibb;
switch (test_cfg) {
case SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE:
@@ -706,6 +801,38 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
}
igt_assert_eq(matched_after_keychange, 0);
break;
+
+ case SESSION_PMSUSPEND_TEARDOWN_PROTCTX_BAN_EXEC:
+ ctx = create_protected_ctx(i915, true, true,
+ true, false, 0);
+ assert_ctx_protected_param(i915, ctx, true);
+
+ ibb = intel_bb_create_with_context(i915, ctx, 4096);
+ igt_assert(ibb);
+
+ bops = buf_ops_create(i915);
+ igt_assert(bops);
+
+ fencebo = create_protected_bo(i915, 4096,
+ false, false, 0);
+ igt_assert(fencebo);
+ fill_bo_content(i915, fencebo, 1024, 0x0);
+
+ fencebuf = intel_buf_create_using_handle(bops, fencebo,
+ 256, 4, 32, 0, I915_TILING_NONE, 0);
+ intel_bb_add_intel_buf(ibb, fencebuf, true);
+
+ gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, 0);
+ trigger_powermgt_suspend_cycle(i915, pm);
+ gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+
+ intel_bb_destroy(ibb);
+ intel_buf_destroy(fencebuf);
+ gem_close(i915, fencebo);
+ gem_context_destroy(i915, ctx);
+ buf_ops_destroy(bops);
+ break;
+
default:
igt_info("Skipping unknown power-mgt test_cfg = %d\n",
test_cfg);
@@ -821,6 +948,11 @@ igt_main
SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE,
&pm);
}
+ igt_subtest("reject-old-context-execution-after-suspend-resume") {
+ test_protected_session_teardown(i915,
+ SESSION_PMSUSPEND_TEARDOWN_PROTCTX_BAN_EXEC,
+ &pm);
+ }
}
igt_fixture {
--
2.25.1
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 26+ messages in thread* [igt-dev] [RFC i-g-t 11/11] Verify gem_execbuf fails with stale PXP buffer after teardown
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (9 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 10/11] Verify gem_execbuf fails with stale PXP context after teardown Alan Previn
@ 2021-03-02 22:53 ` Alan Previn
2021-03-04 0:01 ` Chris Wilson
2021-03-03 16:12 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce PXP Test Patchwork
2021-03-03 19:08 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
12 siblings, 1 reply; 26+ messages in thread
From: Alan Previn @ 2021-03-02 22:53 UTC (permalink / raw)
To: igt-dev; +Cc: Alan Previn
Add a subtest to verify that reusing a stale protected buffer
with a fresh protected context, in a gem_execbuff after a
teardown (triggered by suspend-resume cycle) shall fail
with -EIO error.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
tests/i915/i915_pxp.c | 44 ++++++++++++++++++++++++++++++++++++-------
1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
index b8c82ea9..4d639c0f 100644
--- a/tests/i915/i915_pxp.c
+++ b/tests/i915/i915_pxp.c
@@ -776,10 +776,10 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
int matched_after_keychange = 0, loop = 0;
- uint32_t ctx, fencebo;
+ uint32_t ctx, ctx2, fencebo;
struct intel_buf *fencebuf;
struct buf_ops *bops;
- struct intel_bb *ibb;
+ struct intel_bb *ibb, *ibb2;
switch (test_cfg) {
case SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE:
@@ -803,6 +803,7 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
break;
case SESSION_PMSUSPEND_TEARDOWN_PROTCTX_BAN_EXEC:
+ case SESSION_PMSUSPEND_TEARDOWN_PROTBO_BAN_EXEC:
ctx = create_protected_ctx(i915, true, true,
true, false, 0);
assert_ctx_protected_param(i915, ctx, true);
@@ -813,10 +814,16 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
bops = buf_ops_create(i915);
igt_assert(bops);
- fencebo = create_protected_bo(i915, 4096,
- false, false, 0);
- igt_assert(fencebo);
- fill_bo_content(i915, fencebo, 1024, 0x0);
+ if (test_cfg == SESSION_PMSUSPEND_TEARDOWN_PROTCTX_BAN_EXEC) {
+ /* use normal buffers for testing for invalidation
+ * of protected contexts to ensure kernel is catching
+ * the invalidated context*/
+ fencebo = alloc_and_fill_dest_buff(i915, false,
+ 4096, 0);
+ } else {
+ fencebo = alloc_and_fill_dest_buff(i915, true,
+ 4096, 0);
+ }
fencebuf = intel_buf_create_using_handle(bops, fencebo,
256, 4, 32, 0, I915_TILING_NONE, 0);
@@ -824,12 +831,30 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, 0);
trigger_powermgt_suspend_cycle(i915, pm);
- gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+
+ if (test_cfg == SESSION_PMSUSPEND_TEARDOWN_PROTBO_BAN_EXEC) {
+ /* after teardown, alloc new assets for everything
+ * except the bo to ensure the kernel is catching
+ * the invalidated bo
+ */
+ ctx2 = create_protected_ctx(i915, true, true,
+ true, false, 0);
+ assert_ctx_protected_param(i915, ctx2, true);
+ ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
+ igt_assert(ibb2);
+ gem_execbuf_flush_store_dw(i915, ibb2, ctx2, fencebuf, -EIO);
+ } else {
+ gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+ }
intel_bb_destroy(ibb);
intel_buf_destroy(fencebuf);
gem_close(i915, fencebo);
gem_context_destroy(i915, ctx);
+ if (test_cfg == SESSION_PMSUSPEND_TEARDOWN_PROTBO_BAN_EXEC) {
+ intel_bb_destroy(ibb2);
+ gem_context_destroy(i915, ctx2);
+ }
buf_ops_destroy(bops);
break;
@@ -953,6 +978,11 @@ igt_main
SESSION_PMSUSPEND_TEARDOWN_PROTCTX_BAN_EXEC,
&pm);
}
+ igt_subtest("reject-old-buffer-execution-after-suspend-resume") {
+ test_protected_session_teardown(i915,
+ SESSION_PMSUSPEND_TEARDOWN_PROTBO_BAN_EXEC,
+ &pm);
+ }
}
igt_fixture {
--
2.25.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [igt-dev] [RFC i-g-t 11/11] Verify gem_execbuf fails with stale PXP buffer after teardown
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 11/11] Verify gem_execbuf fails with stale PXP buffer " Alan Previn
@ 2021-03-04 0:01 ` Chris Wilson
2021-03-04 19:14 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2021-03-04 0:01 UTC (permalink / raw)
To: Alan Previn, igt-dev; +Cc: Alan Previn
Quoting Alan Previn (2021-03-02 22:53:34)
> Add a subtest to verify that reusing a stale protected buffer
> with a fresh protected context, in a gem_execbuff after a
> teardown (triggered by suspend-resume cycle) shall fail
> with -EIO error.
I'm used to having a rationale as to why that is the uABI. We can read
the code, but not the why.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [igt-dev] [RFC i-g-t 11/11] Verify gem_execbuf fails with stale PXP buffer after teardown
2021-03-04 0:01 ` Chris Wilson
@ 2021-03-04 19:14 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 26+ messages in thread
From: Teres Alexis, Alan Previn @ 2021-03-04 19:14 UTC (permalink / raw)
To: Chris Wilson, igt-dev
Understood - will add the why into the commit message.
...alan
-----Original Message-----
From: Chris Wilson <chris@chris-wilson.co.uk>
Sent: Wednesday, March 3, 2021 4:02 PM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>; igt-dev@lists.freedesktop.org
Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
Subject: Re: [igt-dev] [RFC i-g-t 11/11] Verify gem_execbuf fails with stale PXP buffer after teardown
Quoting Alan Previn (2021-03-02 22:53:34)
> Add a subtest to verify that reusing a stale protected buffer with a
> fresh protected context, in a gem_execbuff after a teardown (triggered
> by suspend-resume cycle) shall fail with -EIO error.
I'm used to having a rationale as to why that is the uABI. We can read the code, but not the why.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Introduce PXP Test
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (10 preceding siblings ...)
2021-03-02 22:53 ` [igt-dev] [RFC i-g-t 11/11] Verify gem_execbuf fails with stale PXP buffer " Alan Previn
@ 2021-03-03 16:12 ` Patchwork
2021-03-03 19:08 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
12 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2021-03-03 16:12 UTC (permalink / raw)
To: Alan Previn; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 5171 bytes --]
== Series Details ==
Series: Introduce PXP Test
URL : https://patchwork.freedesktop.org/series/87570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9823 -> IGTPW_5567
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/index.html
Known issues
------------
Here are the changes found in IGTPW_5567 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-cml-s: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-cml-s/igt@amdgpu/amd_cs_nop@nop-compute0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_exec_fence@basic-wait@bcs0:
- fi-cml-s: NOTRUN -> [SKIP][3] ([i915#1208]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-cml-s/igt@gem_exec_fence@basic-wait@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-cml-s: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-cml-s/igt@gem_huc_copy@huc-copy.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-cml-s: NOTRUN -> [SKIP][5] ([fdo#109284] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-cml-s/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-s: NOTRUN -> [SKIP][6] ([fdo#109285])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-cml-s/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-s: NOTRUN -> [SKIP][7] ([fdo#109278] / [i915#533])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-cml-s/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@i915_selftest@live@client:
- fi-glk-dsi: [DMESG-FAIL][8] ([i915#3047]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/fi-glk-dsi/igt@i915_selftest@live@client.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-glk-dsi/igt@i915_selftest@live@client.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][10] ([i915#2782]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3047]: https://gitlab.freedesktop.org/drm/intel/issues/3047
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (38 -> 32)
------------------------------
Additional (1): fi-cml-s
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-dg1-1 fi-cml-drallion fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6020 -> IGTPW_5567
CI-20190529: 20190529
CI_DRM_9823: d559dcad6da00e498bb2c41967a9e5487545b8ba @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5567: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/index.html
IGT_6020: 8382d9e87bba39ecc6fa879b2491e28c7fb2e3c7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@i915_pxp@create-protected-buffer
+igt@i915_pxp@create-regular-buffer
+igt@i915_pxp@create-regular-context-1
+igt@i915_pxp@create-regular-context-2
+igt@i915_pxp@create-valid-protected-context
+igt@i915_pxp@fail-invalid-protected-context
+igt@i915_pxp@hw-rejects-pxp-buffer
+igt@i915_pxp@hw-rejects-pxp-context
+igt@i915_pxp@protected-encrypted-src-copy-not-readible
+igt@i915_pxp@protected-raw-src-copy-not-readible
+igt@i915_pxp@regular-baseline-src-copy-readible
+igt@i915_pxp@reject-modify-context-protection-off-1
+igt@i915_pxp@reject-modify-context-protection-off-2
+igt@i915_pxp@reject-modify-context-protection-off-3
+igt@i915_pxp@reject-modify-context-protection-on
+igt@i915_pxp@reject-old-buffer-execution-after-suspend-resume
+igt@i915_pxp@reject-old-context-execution-after-suspend-resume
+igt@i915_pxp@verify-pxp-key-change-after-suspend-resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/index.html
[-- Attachment #1.2: Type: text/html, Size: 6098 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 26+ messages in thread* [igt-dev] ✗ Fi.CI.IGT: failure for Introduce PXP Test
2021-03-02 22:53 [igt-dev] [RFC i-g-t 00/11] Introduce PXP Test Alan Previn
` (11 preceding siblings ...)
2021-03-03 16:12 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce PXP Test Patchwork
@ 2021-03-03 19:08 ` Patchwork
12 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2021-03-03 19:08 UTC (permalink / raw)
To: Alan Previn; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 30236 bytes --]
== Series Details ==
Series: Introduce PXP Test
URL : https://patchwork.freedesktop.org/series/87570/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9823_full -> IGTPW_5567_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5567_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5567_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5567_full:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_pxp@hw-rejects-pxp-buffer} (NEW):
- shard-iclb: NOTRUN -> [FAIL][1] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb1/igt@i915_pxp@hw-rejects-pxp-buffer.html
- shard-apl: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl1/igt@i915_pxp@hw-rejects-pxp-buffer.html
- shard-kbl: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl3/igt@i915_pxp@hw-rejects-pxp-buffer.html
- shard-snb: NOTRUN -> [FAIL][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-snb6/igt@i915_pxp@hw-rejects-pxp-buffer.html
* {igt@i915_pxp@hw-rejects-pxp-context} (NEW):
- shard-tglb: NOTRUN -> [SKIP][5] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb7/igt@i915_pxp@hw-rejects-pxp-context.html
- shard-glk: NOTRUN -> [FAIL][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk2/igt@i915_pxp@hw-rejects-pxp-context.html
- shard-hsw: NOTRUN -> [FAIL][7] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw4/igt@i915_pxp@hw-rejects-pxp-context.html
* {igt@i915_pxp@reject-modify-context-protection-off-2} (NEW):
- shard-tglb: NOTRUN -> [FAIL][8] +11 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb1/igt@i915_pxp@reject-modify-context-protection-off-2.html
* {igt@i915_pxp@verify-pxp-key-change-after-suspend-resume} (NEW):
- shard-iclb: NOTRUN -> [SKIP][9] +13 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb3/igt@i915_pxp@verify-pxp-key-change-after-suspend-resume.html
New tests
---------
New tests have been introduced between CI_DRM_9823_full and IGTPW_5567_full:
### New IGT tests (18) ###
* igt@i915_pxp@create-protected-buffer:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@i915_pxp@create-regular-buffer:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0] s
* igt@i915_pxp@create-regular-context-1:
- Statuses : 1 fail(s) 6 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@create-regular-context-2:
- Statuses : 1 fail(s) 5 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@create-valid-protected-context:
- Statuses : 1 fail(s) 6 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@fail-invalid-protected-context:
- Statuses : 1 fail(s) 5 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@hw-rejects-pxp-buffer:
- Statuses : 5 fail(s) 1 skip(s)
- Exec time: [0.0, 0.10] s
* igt@i915_pxp@hw-rejects-pxp-context:
- Statuses : 3 fail(s) 1 skip(s)
- Exec time: [0.0, 0.12] s
* igt@i915_pxp@protected-encrypted-src-copy-not-readible:
- Statuses : 1 fail(s) 5 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@protected-raw-src-copy-not-readible:
- Statuses :
- Exec time: [None] s
* igt@i915_pxp@regular-baseline-src-copy-readible:
- Statuses : 1 fail(s) 6 skip(s)
- Exec time: [0.0, 0.01] s
* igt@i915_pxp@reject-modify-context-protection-off-1:
- Statuses : 1 fail(s) 5 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@reject-modify-context-protection-off-2:
- Statuses : 1 fail(s) 4 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@reject-modify-context-protection-off-3:
- Statuses : 1 fail(s) 5 skip(s)
- Exec time: [0.0, 0.03] s
* igt@i915_pxp@reject-modify-context-protection-on:
- Statuses : 1 fail(s) 3 skip(s)
- Exec time: [0.0, 0.00] s
* igt@i915_pxp@reject-old-buffer-execution-after-suspend-resume:
- Statuses :
- Exec time: [None] s
* igt@i915_pxp@reject-old-context-execution-after-suspend-resume:
- Statuses : 1 fail(s) 6 skip(s)
- Exec time: [0.0, 0.10] s
* igt@i915_pxp@verify-pxp-key-change-after-suspend-resume:
- Statuses : 1 fail(s) 6 skip(s)
- Exec time: [0.0, 0.01] s
Known issues
------------
Here are the changes found in IGTPW_5567_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-iclb: NOTRUN -> [SKIP][10] ([i915#1839])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb4/igt@feature_discovery@display-3x.html
- shard-tglb: NOTRUN -> [SKIP][11] ([i915#1839])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb2/igt@feature_discovery@display-3x.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-hsw: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw1/igt@gem_ctx_persistence@engines-mixed.html
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-snb2/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb3/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_exec_fair@basic-deadline:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#2846])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb2/igt@gem_exec_fair@basic-deadline.html
- shard-glk: NOTRUN -> [FAIL][16] ([i915#2846])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk9/igt@gem_exec_fair@basic-deadline.html
- shard-apl: NOTRUN -> [FAIL][17] ([i915#2846])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-glk8/igt@gem_exec_fair@basic-none-share@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-tglb: NOTRUN -> [FAIL][20] ([i915#2842]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb7/igt@gem_exec_fair@basic-none@vcs0.html
- shard-glk: NOTRUN -> [FAIL][21] ([i915#2842]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk9/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][22] -> [FAIL][23] ([i915#2842])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][24] ([i915#2842]) +5 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-iclb: NOTRUN -> [FAIL][25] ([i915#2389]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb8/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][26] ([i915#2389]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-snb6/igt@gem_exec_reloc@basic-wide-active@rcs0.html
- shard-kbl: NOTRUN -> [FAIL][27] ([i915#2389]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl3/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [PASS][28] -> [DMESG-WARN][29] ([i915#118] / [i915#95])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-glk9/igt@gem_exec_whisper@basic-fds-forked-all.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk3/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-iclb: [PASS][30] -> [INCOMPLETE][31] ([i915#1895])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-iclb5/igt@gem_exec_whisper@basic-queues-priority.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb5/igt@gem_exec_whisper@basic-queues-priority.html
* igt@gem_pwrite@basic-exhaustion:
- shard-snb: NOTRUN -> [WARN][32] ([i915#2658]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-snb6/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][33] ([i915#768]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb2/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109312])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb6/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_userptr_blits@mmap-offset-invalidate-active@wb:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271]) +164 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl1/igt@gem_userptr_blits@mmap-offset-invalidate-active@wb.html
* igt@gem_userptr_blits@mmap-offset-invalidate-idle@gtt:
- shard-tglb: NOTRUN -> [SKIP][36] ([i915#1317]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb1/igt@gem_userptr_blits@mmap-offset-invalidate-idle@gtt.html
* igt@gem_userptr_blits@mmap-offset-invalidate-idle@uc:
- shard-iclb: NOTRUN -> [SKIP][37] ([i915#1317]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb2/igt@gem_userptr_blits@mmap-offset-invalidate-idle@uc.html
* igt@gem_userptr_blits@mmap-offset-invalidate-idle@wb:
- shard-glk: NOTRUN -> [SKIP][38] ([fdo#109271]) +59 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk7/igt@gem_userptr_blits@mmap-offset-invalidate-idle@wb.html
* igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#112306])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb1/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#112306]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb3/igt@gen9_exec_parse@batch-without-end.html
* igt@i915_pm_backlight@basic-brightness:
- shard-hsw: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3012])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw2/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#1937])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [PASS][43] -> [WARN][44] ([i915#1519])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-hsw5/igt@i915_pm_rc6_residency@rc6-idle.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#109506] / [i915#2411])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb3/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109293] / [fdo#109506])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb4/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: NOTRUN -> [INCOMPLETE][47] ([i915#2782])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#111614]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb3/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#110725] / [fdo#111614]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb8/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +26 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl6/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +16 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl3/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109278] / [i915#1149])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb4/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk7/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109284] / [fdo#111827]) +10 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb7/igt@kms_color_chamelium@pipe-a-ctm-max.html
* igt@kms_color_chamelium@pipe-c-ctm-negative:
- shard-hsw: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw5/igt@kms_color_chamelium@pipe-c-ctm-negative.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-snb: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +22 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-snb5/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#109284] / [fdo#111827]) +7 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb2/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][58] ([i915#1319])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl1/igt@kms_content_protection@atomic-dpms.html
- shard-tglb: NOTRUN -> [SKIP][59] ([fdo#111828])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb6/igt@kms_content_protection@atomic-dpms.html
- shard-kbl: NOTRUN -> [TIMEOUT][60] ([i915#1319]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109278] / [fdo#109279])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][62] ([i915#180])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][63] ([fdo#109271]) +329 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-snb7/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109274] / [fdo#109278]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-single-move:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109278]) +13 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb1/igt@kms_cursor_legacy@pipe-d-single-move.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][66] -> [INCOMPLETE][67] ([i915#155] / [i915#180] / [i915#636])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#111825]) +21 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb1/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109274]) +8 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb7/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
- shard-tglb: NOTRUN -> [FAIL][70] ([i915#2122])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb7/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-dpms-off-vs-modeset@c-hdmi-a1:
- shard-hsw: [PASS][71] -> [DMESG-WARN][72] ([i915#44])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-hsw1/igt@kms_flip@flip-vs-dpms-off-vs-modeset@c-hdmi-a1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw5/igt@kms_flip@flip-vs-dpms-off-vs-modeset@c-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][73] ([i915#180]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-kbl: NOTRUN -> [FAIL][74] ([i915#2641])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2642]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2642])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2642]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
- shard-hsw: NOTRUN -> [SKIP][78] ([fdo#109271]) +69 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109280]) +20 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][80] -> [DMESG-WARN][81] ([i915#180]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][84] ([i915#265])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][85] ([fdo#111615])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb1/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-none:
- shard-hsw: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#533]) +7 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw5/igt@kms_plane_multiple@atomic-pipe-d-tiling-none.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2733])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl4/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
- shard-glk: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2733])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_prime@basic-crc@first-to-second:
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#1836])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb5/igt@kms_prime@basic-crc@first-to-second.html
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#1836])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb5/igt@kms_prime@basic-crc@first-to-second.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#658]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-iclb: NOTRUN -> [SKIP][92] ([i915#658]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb3/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
- shard-glk: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk4/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#658]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl7/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][95] -> [SKIP][96] ([fdo#109441]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr@suspend:
- shard-hsw: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#1072]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-hsw1/igt@kms_psr@suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271]) +227 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl8/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#533]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_vrr@flip-basic:
- shard-tglb: NOTRUN -> [SKIP][100] ([fdo#109502]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb1/igt@kms_vrr@flip-basic.html
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> [SKIP][101] ([fdo#109502]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb4/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-iclb: NOTRUN -> [SKIP][102] ([i915#2437])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb5/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2437])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl6/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#2530]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb4/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-tglb: NOTRUN -> [SKIP][105] ([i915#2530]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb5/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@prime_nv_api@i915_nv_double_import:
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109291]) +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb7/igt@prime_nv_api@i915_nv_double_import.html
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109291]) +3 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb8/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html
* igt@sysfs_clients@recycle-many:
- shard-iclb: [PASS][108] -> [FAIL][109] ([i915#3028]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-iclb3/igt@sysfs_clients@recycle-many.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-iclb4/igt@sysfs_clients@recycle-many.html
- shard-glk: [PASS][110] -> [FAIL][111] ([i915#3028]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-glk6/igt@sysfs_clients@recycle-many.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk2/igt@sysfs_clients@recycle-many.html
- shard-tglb: [PASS][112] -> [FAIL][113] ([i915#3028])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-tglb2/igt@sysfs_clients@recycle-many.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb3/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-10@rcs0:
- shard-glk: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#3026]) +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk9/igt@sysfs_clients@sema-10@rcs0.html
* igt@sysfs_clients@sema-10@vcs0:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#3026]) +3 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-apl8/igt@sysfs_clients@sema-10@vcs0.html
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#3026]) +3 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-kbl1/igt@sysfs_clients@sema-10@vcs0.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][117] ([i915#3063]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-tglb7/igt@gem_eio@unwedge-stress.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][119] ([i915#2842]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [FAIL][121] ([i915#2842]) -> [PASS][122] +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9823/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shar
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5567/index.html
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