[PATCH V2]: MIPS work

[PATCH V2]: MIPS work

[Huang Pei]

PATCH 1: 

No function change, just make ASE field sit close;

PATCH 2:

"CAC_BASE << 53" causes building warning MIPS32, changing CAC_BASE from 
UL into ULL causes new warnings for unmatch integer size on MIP32, let's
one step back, just fix the bug, make more comment

PATCH 3:

remove space

[PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table

[Huang Pei]

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/include/asm/ptrace.h | 10 +++++-----
 arch/mips/kernel/asm-offsets.c |  6 +++---
 arch/mips/kernel/ptrace.c      | 10 +++++-----
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 1e76774b36dd..e51691f2b7af 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -34,16 +34,16 @@ struct pt_regs {
 	/* Saved main processor registers. */
 	unsigned long regs[32];
 
+	unsigned long lo;
+	unsigned long hi;
 	/* Saved special registers. */
+	unsigned long cp0_epc;
+	unsigned long cp0_badvaddr;
 	unsigned long cp0_status;
-	unsigned long hi;
-	unsigned long lo;
+	unsigned long cp0_cause;
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 	unsigned long acx;
 #endif
-	unsigned long cp0_badvaddr;
-	unsigned long cp0_cause;
-	unsigned long cp0_epc;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	unsigned long long mpl[6];        /* MTM{0-5} */
 	unsigned long long mtp[6];        /* MTP{0-5} */
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index aebfda81120a..8a9ab78bcc63 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -60,13 +60,13 @@ void output_ptreg_defines(void)
 	OFFSET(PT_R31, pt_regs, regs[31]);
 	OFFSET(PT_LO, pt_regs, lo);
 	OFFSET(PT_HI, pt_regs, hi);
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
-	OFFSET(PT_ACX, pt_regs, acx);
-#endif
 	OFFSET(PT_EPC, pt_regs, cp0_epc);
 	OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
 	OFFSET(PT_STATUS, pt_regs, cp0_status);
 	OFFSET(PT_CAUSE, pt_regs, cp0_cause);
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+	OFFSET(PT_ACX, pt_regs, acx);
+#endif
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	OFFSET(PT_MPL, pt_regs, mpl);
 	OFFSET(PT_MTP, pt_regs, mtp);
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index db7c5be1d4a3..06ee1184fad3 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -886,15 +886,15 @@ static const struct pt_regs_offset regoffset_table[] = {
 	REG_OFFSET_NAME(r29, regs[29]),
 	REG_OFFSET_NAME(r30, regs[30]),
 	REG_OFFSET_NAME(r31, regs[31]),
-	REG_OFFSET_NAME(c0_status, cp0_status),
-	REG_OFFSET_NAME(hi, hi),
 	REG_OFFSET_NAME(lo, lo),
+	REG_OFFSET_NAME(hi, hi),
+	REG_OFFSET_NAME(c0_epc, cp0_epc),
+	REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
+	REG_OFFSET_NAME(c0_status, cp0_status),
+	REG_OFFSET_NAME(c0_cause, cp0_cause),
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 	REG_OFFSET_NAME(acx, acx),
 #endif
-	REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
-	REG_OFFSET_NAME(c0_cause, cp0_cause),
-	REG_OFFSET_NAME(c0_epc, cp0_epc),
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	REG_OFFSET_NAME(mpl0, mpl[0]),
 	REG_OFFSET_NAME(mpl1, mpl[1]),
-- 
2.17.1

[PATCH 2/3] MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling

[Huang Pei]

+. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached

+. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit

CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field.

+. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 48,
only save 48 - 12 + 5(for bit[63:59]) = 41 bits, aka. :

   bit[63:59] | 0000 0000 000 |  bit[47:12] | 0000 0000 0000

+. for CKSEG0, only save 29 - 12 = 17 bits

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/Kconfig    |  3 ++-
 arch/mips/mm/tlbex.c | 18 +++++++++++++++---
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2000bb2b0220..5741dae35b74 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2142,7 +2142,8 @@ config CPU_SUPPORTS_HUGEPAGES
 	depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
 config MIPS_PGD_C0_CONTEXT
 	bool
-	default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
+	depends on 64BIT
+	default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
 
 #
 # Set to y for ptrace access to watch registers.
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a7521b8f7658..7d89e016076e 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -848,8 +848,14 @@ void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
 		/* Clear lower 23 bits of context. */
 		uasm_i_dins(p, ptr, 0, 0, 23);
 
-		/* 1 0	1 0 1  << 6  xkphys cached */
+		/* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */
+#ifdef CONFIG_CPU_LOONGSON64
+		/* 0x98xx xxxx xxxx xxxx, bit[63:59]: 1 0 0 1 1 << 6, xphys cached */
+		uasm_i_ori(p, ptr, ptr, 0x4c0);
+#else
+		/* 0xa8xx xxxx xxxx xxxx, bit[63:59]: 1 0 1 0 1 << 6, xphys cached */
 		uasm_i_ori(p, ptr, ptr, 0x540);
+#endif
 		uasm_i_drotr(p, ptr, ptr, 11);
 #elif defined(CONFIG_SMP)
 		UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
@@ -1164,8 +1170,15 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
 
 	if (pgd_reg == -1) {
 		vmalloc_branch_delay_filled = 1;
-		/* 1 0	1 0 1  << 6  xkphys cached */
+		/* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */
+#ifdef CONFIG_CPU_LOONGSON64
+		/* 0x98xx xxxx xxxx xxxx, bit[63:59]: 1 0 0 1 1 << 6, xphys cached */
+		uasm_i_ori(p, ptr, ptr, 0x4c0);
+#else
+		/* 0xa8xx xxxx xxxx xxxx, bit[63:59]: 1 0 1 0 1 << 6, xphys cached */
 		uasm_i_ori(p, ptr, ptr, 0x540);
+#endif
+
 		uasm_i_drotr(p, ptr, ptr, 11);
 	}
 
@@ -1292,7 +1305,6 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
 
 	return rv;
 }
-
 /*
  * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
  * because EXL == 0.  If we wrap, we can also use the 32 instruction
-- 
2.17.1

[PATCH 3/3] MIPS: loongson64: alloc pglist_data at run time

[Huang Pei]

It can make some metadata of MM, like pglist_data and zone
NUMA-aware

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/loongson64/numa.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
index cf9459f79f9b..afafd367cb38 100644
--- a/arch/mips/loongson64/numa.c
+++ b/arch/mips/loongson64/numa.c
@@ -26,7 +26,6 @@
 #include <asm/wbflush.h>
 #include <boot_param.h>
 
-static struct pglist_data prealloc__node_data[MAX_NUMNODES];
 unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
 EXPORT_SYMBOL(__node_distances);
 struct pglist_data *__node_data[MAX_NUMNODES];
@@ -151,8 +150,12 @@ static void __init szmem(unsigned int node)
 
 static void __init node_mem_init(unsigned int node)
 {
+	struct pglist_data *nd;
 	unsigned long node_addrspace_offset;
 	unsigned long start_pfn, end_pfn;
+	unsigned long nd_pa;
+	int tnid;
+	const size_t nd_size = roundup(sizeof(pg_data_t), SMP_CACHE_BYTES);
 
 	node_addrspace_offset = nid_to_addrbase(node);
 	pr_info("Node%d's addrspace_offset is 0x%lx\n",
@@ -162,8 +165,16 @@ static void __init node_mem_init(unsigned int node)
 	pr_info("Node%d: start_pfn=0x%lx, end_pfn=0x%lx\n",
 		node, start_pfn, end_pfn);
 
-	__node_data[node] = prealloc__node_data + node;
-
+	nd_pa = memblock_phys_alloc_try_nid(nd_size, SMP_CACHE_BYTES, node);
+	if (!nd_pa)
+		panic("Cannot allocate %zu bytes for node %d data\n",
+		      nd_size, node);
+	nd = __va(nd_pa);
+	memset(nd, 0, sizeof(struct pglist_data));
+	tnid = early_pfn_to_nid(nd_pa >> PAGE_SHIFT);
+	if (tnid != node)
+		pr_info("NODE_DATA(%d) on node %d\n", node, tnid);
+	__node_data[node] = nd;
 	NODE_DATA(node)->node_start_pfn = start_pfn;
 	NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn;
 
-- 
2.17.1

Re: [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table

[Thomas Bogendoerfer]

On Fri, Mar 05, 2021 at 06:03:08PM +0800, Huang Pei wrote:
> Signed-off-by: Huang Pei <huangpei@loongson.cn>
> ---
>  arch/mips/include/asm/ptrace.h | 10 +++++-----
>  arch/mips/kernel/asm-offsets.c |  6 +++---
>  arch/mips/kernel/ptrace.c      | 10 +++++-----
>  3 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
> index 1e76774b36dd..e51691f2b7af 100644
> --- a/arch/mips/include/asm/ptrace.h
> +++ b/arch/mips/include/asm/ptrace.h
> @@ -34,16 +34,16 @@ struct pt_regs {
>  	/* Saved main processor registers. */
>  	unsigned long regs[32];
>  
> +	unsigned long lo;
> +	unsigned long hi;
>  	/* Saved special registers. */
> +	unsigned long cp0_epc;
> +	unsigned long cp0_badvaddr;
>  	unsigned long cp0_status;
> -	unsigned long hi;
> -	unsigned long lo;
> +	unsigned long cp0_cause;
>  #ifdef CONFIG_CPU_HAS_SMARTMIPS
>  	unsigned long acx;
>  #endif
> -	unsigned long cp0_badvaddr;
> -	unsigned long cp0_cause;
> -	unsigned long cp0_epc;
>  #ifdef CONFIG_CPU_CAVIUM_OCTEON
>  	unsigned long long mpl[6];        /* MTM{0-5} */
>  	unsigned long long mtp[6];        /* MTP{0-5} */

sorry this is pointless, I'm not taking this.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table

[黄沛]

What about other two patches? 


Current ftrace implementation is not safe on MIPS/SMP,

When disabling  tracing, we need to change 

Jal 
Addiu sp,sp,-offset

Into 

Nop
Nop

Atomically, but mips issue two writes, no 
matter ‎ in what order these writes are seen by
other cpu, ‎ it is wrecked in  these two case

Jal 
Nop

Or,

Nop
‎addiu sp,sp, _offset

‎Huang Pei


  Original Message  
From: Thomas Bogendoerfer
Sent: 2021年3月6日星期六 16:06
To: Huang Pei
Cc: ambrosehua@gmail.com; Bibo Mao; Andrew Morton; linux-mips@vger.kernel.org; linux-arch@vger.kernel.org; linux-mm@kvack.org; Jiaxun Yang; Paul Burton; Li Xuefeng; Yang Tiezhu; Gao Juxin; Huacai Chen; Jinyang He
Subject: Re: [PATCH 1/3] MIPS: sync arrangement of pt_regs with user_pt_regs and regoffset_table

On Fri, Mar 05, 2021 at 06:03:08PM +0800, Huang Pei wrote:
> Signed-off-by: Huang Pei <huangpei@loongson.cn>
> ---
> arch/mips/include/asm/ptrace.h | 10 +++++-----
> arch/mips/kernel/asm-offsets.c | 6 +++---
> arch/mips/kernel/ptrace.c | 10 +++++-----
> 3 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
> index 1e76774b36dd..e51691f2b7af 100644
> --- a/arch/mips/include/asm/ptrace.h
> +++ b/arch/mips/include/asm/ptrace.h
> @@ -34,16 +34,16 @@ struct pt_regs {
> /* Saved main processor registers. */
> unsigned long regs[32];
> 
> +	unsigned long lo;
> +	unsigned long hi;
> /* Saved special registers. */
> +	unsigned long cp0_epc;
> +	unsigned long cp0_badvaddr;
> unsigned long cp0_status;
> -	unsigned long hi;
> -	unsigned long lo;
> +	unsigned long cp0_cause;
> #ifdef CONFIG_CPU_HAS_SMARTMIPS
> unsigned long acx;
> #endif
> -	unsigned long cp0_badvaddr;
> -	unsigned long cp0_cause;
> -	unsigned long cp0_epc;
> #ifdef CONFIG_CPU_CAVIUM_OCTEON
> unsigned long long mpl[6]; /* MTM{0-5} */
> unsigned long long mtp[6]; /* MTP{0-5} */

sorry this is pointless, I'm not taking this.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]