[weiny2:tip-pks-v4.2-5.12-rc 6/16] arch/x86/mm/pkeys.c:250: warning: expecting prototype for optimizes MSR writes by maintaining a per cpu cache which can(). Prototype was for write_pkrs() instead

[weiny2:tip-pks-v4.2-5.12-rc 6/16] arch/x86/mm/pkeys.c:250: warning: expecting prototype for optimizes MSR writes by maintaining a per cpu cache which can(). Prototype was for write_pkrs() instead

[kernel test robot]

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tree:   https://github.com/weiny2/linux-kernel.git tip-pks-v4.2-5.12-rc
head:   84a3164e5bbe2fef506f7c3ba217b325cc142702
commit: c126e60b9338bf968bb1aed1fbd65f1ce38094e9 [6/16] x86/pks: Preserve the PKRS MSR on context switch
config: x86_64-randconfig-a012-20210308 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 820f508b08d7c94b2dd7847e9710d2bc36d3dd45)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # https://github.com/weiny2/linux-kernel/commit/c126e60b9338bf968bb1aed1fbd65f1ce38094e9
        git remote add weiny2 https://github.com/weiny2/linux-kernel.git
        git fetch --no-tags weiny2 tip-pks-v4.2-5.12-rc
        git checkout c126e60b9338bf968bb1aed1fbd65f1ce38094e9
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   arch/x86/mm/pkeys.c:250: warning: Function parameter or member 'new_pkrs' not described in 'write_pkrs'
>> arch/x86/mm/pkeys.c:250: warning: expecting prototype for optimizes MSR writes by maintaining a per cpu cache which can(). Prototype was for write_pkrs() instead


vim +250 arch/x86/mm/pkeys.c

   234	
   235	/**
   236	 * write_pkrs() optimizes MSR writes by maintaining a per cpu cache which can
   237	 * be checked quickly.
   238	 *
   239	 * It should also be noted that the underlying WRMSR(MSR_IA32_PKRS) is not
   240	 * serializing but still maintains ordering properties similar to WRPKRU.
   241	 * The current SDM section on PKRS needs updating but should be the same as
   242	 * that of WRPKRU.  So to quote from the WRPKRU text:
   243	 *
   244	 *     WRPKRU will never execute transiently. Memory accesses
   245	 *     affected by PKRU register will not execute (even transiently)
   246	 *     until all prior executions of WRPKRU have completed execution
   247	 *     and updated the PKRU register.
   248	 */
   249	void write_pkrs(u32 new_pkrs)
 > 250	{

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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