[PATCH net-next v3 v3 0/2] axienet clock additions

From: Robert Hancock <robert.hancock@calian.com>
To: radhey.shyam.pandey@xilinx.com, davem@davemloft.net, kuba@kernel.org
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
	Robert Hancock <robert.hancock@calian.com>
Subject: [PATCH net-next v3 v3 0/2] axienet clock additions
Date: Fri, 12 Mar 2021 13:52:12 -0600	[thread overview]
Message-ID: <20210312195214.4002847-1-robert.hancock@calian.com> (raw)

Add support to the axienet driver for controlling all of the clocks that
the logic core may utilize.

Note this patch set is dependent on "net: axienet: Fix probe error cleanup"
which has been submitted for the net tree.

Changed since v2:
-Additional clock description clarification

Changed since v1:
-Clarified clock usages in documentation and code comments

Robert Hancock (2):
  dt-bindings: net: xilinx_axienet: Document additional clocks
  net: axienet: Enable more clocks

 .../bindings/net/xilinx_axienet.txt           | 25 ++++++++++----
 drivers/net/ethernet/xilinx/xilinx_axienet.h  |  8 +++--
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 34 +++++++++++++++----
 .../net/ethernet/xilinx/xilinx_axienet_mdio.c |  4 +--
 4 files changed, 54 insertions(+), 17 deletions(-)

-- 
2.27.0