From: Jiuyang Liu <liu@jiuyang.me> To: unlisted-recipients:; (no To-header on input) Cc: Andrew Waterman <waterman@eecs.berkeley.edu>, Jiuyang Liu <liu@jiuyang.me>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atish.patra@wdc.com>, Anup Patel <anup.patel@wdc.com>, Andrew Morton <akpm@linux-foundation.org>, Mike Rapoport <rppt@kernel.org>, Kefeng Wang <wangkefeng.wang@huawei.com>, Zong Li <zong.li@sifive.com>, Greentime Hu <greentime.hu@sifive.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV Date: Tue, 16 Mar 2021 03:46:36 +0000 [thread overview] Message-ID: <20210316034638.16276-1-liu@jiuyang.me> (raw) In-Reply-To: <20210316015328.13516-1-liu@jiuyang.me> This patch inserts SFENCE.VMA after modifying PTE based on RISC-V specification. arch/riscv/include/asm/pgtable.h: 1. implement pte_user, pte_global and pte_leaf to check correspond attribute of a pte_t. 2. insert SFENCE.VMA in set_pte_at based on RISC-V Volume 2, Privileged Spec v. 20190608 page 66 and 67: If software modifies a non-leaf PTE, it should execute SFENCE.VMA with rs1=x0. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified. If software modifies a leaf PTE, it should execute SFENCE.VMA with rs1 set to a virtual address within the page. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified. arch/riscv/include/asm/tlbflush.h: 1. implement get_current_asid to get current program asid. 2. implement local_flush_tlb_asid to flush tlb with asid. Signed-off-by: Jiuyang Liu <liu@jiuyang.me> --- arch/riscv/include/asm/pgtable.h | 27 +++++++++++++++++++++++++++ arch/riscv/include/asm/tlbflush.h | 12 ++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index ebf817c1bdf4..5a47c60372c1 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -222,6 +222,16 @@ static inline int pte_write(pte_t pte) return pte_val(pte) & _PAGE_WRITE; } +static inline int pte_user(pte_t pte) +{ + return pte_val(pte) & _PAGE_USER; +} + +static inline int pte_global(pte_t pte) +{ + return pte_val(pte) & _PAGE_GLOBAL; +} + static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; @@ -248,6 +258,11 @@ static inline int pte_special(pte_t pte) return pte_val(pte) & _PAGE_SPECIAL; } +static inline int pte_leaf(pte_t pte) +{ + return pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC); +} + /* static inline pte_t pte_rdprotect(pte_t pte) */ static inline pte_t pte_wrprotect(pte_t pte) @@ -358,6 +373,18 @@ static inline void set_pte_at(struct mm_struct *mm, flush_icache_pte(pteval); set_pte(ptep, pteval); + + if (pte_present(pteval)) { + if (pte_leaf(pteval)) { + local_flush_tlb_page(addr); + } else { + if (pte_global(pteval)) + local_flush_tlb_all(); + else + local_flush_tlb_asid(); + + } + } } static inline void pte_clear(struct mm_struct *mm, diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 394cfbccdcd9..1f9b62b3670b 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -21,6 +21,18 @@ static inline void local_flush_tlb_page(unsigned long addr) { __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } + +static inline unsigned long get_current_asid(void) +{ + return (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; +} + +static inline void local_flush_tlb_asid(void) +{ + unsigned long asid = get_current_asid(); + __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) : "memory"); +} + #else /* CONFIG_MMU */ #define local_flush_tlb_all() do { } while (0) #define local_flush_tlb_page(addr) do { } while (0) -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Jiuyang Liu <liu@jiuyang.me> Cc: Andrew Waterman <waterman@eecs.berkeley.edu>, Jiuyang Liu <liu@jiuyang.me>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atish.patra@wdc.com>, Anup Patel <anup.patel@wdc.com>, Andrew Morton <akpm@linux-foundation.org>, Mike Rapoport <rppt@kernel.org>, Kefeng Wang <wangkefeng.wang@huawei.com>, Zong Li <zong.li@sifive.com>, Greentime Hu <greentime.hu@sifive.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV Date: Tue, 16 Mar 2021 03:46:36 +0000 [thread overview] Message-ID: <20210316034638.16276-1-liu@jiuyang.me> (raw) In-Reply-To: <20210316015328.13516-1-liu@jiuyang.me> This patch inserts SFENCE.VMA after modifying PTE based on RISC-V specification. arch/riscv/include/asm/pgtable.h: 1. implement pte_user, pte_global and pte_leaf to check correspond attribute of a pte_t. 2. insert SFENCE.VMA in set_pte_at based on RISC-V Volume 2, Privileged Spec v. 20190608 page 66 and 67: If software modifies a non-leaf PTE, it should execute SFENCE.VMA with rs1=x0. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified. If software modifies a leaf PTE, it should execute SFENCE.VMA with rs1 set to a virtual address within the page. If any PTE along the traversal path had its G bit set, rs2 must be x0; otherwise, rs2 should be set to the ASID for which the translation is being modified. arch/riscv/include/asm/tlbflush.h: 1. implement get_current_asid to get current program asid. 2. implement local_flush_tlb_asid to flush tlb with asid. Signed-off-by: Jiuyang Liu <liu@jiuyang.me> --- arch/riscv/include/asm/pgtable.h | 27 +++++++++++++++++++++++++++ arch/riscv/include/asm/tlbflush.h | 12 ++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index ebf817c1bdf4..5a47c60372c1 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -222,6 +222,16 @@ static inline int pte_write(pte_t pte) return pte_val(pte) & _PAGE_WRITE; } +static inline int pte_user(pte_t pte) +{ + return pte_val(pte) & _PAGE_USER; +} + +static inline int pte_global(pte_t pte) +{ + return pte_val(pte) & _PAGE_GLOBAL; +} + static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; @@ -248,6 +258,11 @@ static inline int pte_special(pte_t pte) return pte_val(pte) & _PAGE_SPECIAL; } +static inline int pte_leaf(pte_t pte) +{ + return pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC); +} + /* static inline pte_t pte_rdprotect(pte_t pte) */ static inline pte_t pte_wrprotect(pte_t pte) @@ -358,6 +373,18 @@ static inline void set_pte_at(struct mm_struct *mm, flush_icache_pte(pteval); set_pte(ptep, pteval); + + if (pte_present(pteval)) { + if (pte_leaf(pteval)) { + local_flush_tlb_page(addr); + } else { + if (pte_global(pteval)) + local_flush_tlb_all(); + else + local_flush_tlb_asid(); + + } + } } static inline void pte_clear(struct mm_struct *mm, diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 394cfbccdcd9..1f9b62b3670b 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -21,6 +21,18 @@ static inline void local_flush_tlb_page(unsigned long addr) { __asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"); } + +static inline unsigned long get_current_asid(void) +{ + return (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; +} + +static inline void local_flush_tlb_asid(void) +{ + unsigned long asid = get_current_asid(); + __asm__ __volatile__ ("sfence.vma x0, %0" : : "r" (asid) : "memory"); +} + #else /* CONFIG_MMU */ #define local_flush_tlb_all() do { } while (0) #define local_flush_tlb_page(addr) do { } while (0) -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-03-16 3:51 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-10 6:22 [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV Jiuyang 2021-03-10 6:22 ` Jiuyang 2021-03-16 1:53 ` [PATCH 2/2] Bug Fix for last patch Jiuyang Liu 2021-03-16 1:53 ` Jiuyang Liu 2021-03-16 3:15 ` Yixun Lan 2021-03-16 3:15 ` Yixun Lan 2021-03-16 3:40 ` Andrew Morton 2021-03-16 3:40 ` Andrew Morton 2021-03-16 3:46 ` Jiuyang Liu [this message] 2021-03-16 3:46 ` [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV Jiuyang Liu 2021-03-16 5:05 ` Anup Patel 2021-03-16 5:05 ` Anup Patel 2021-03-16 6:56 ` Jiuyang Liu 2021-03-16 6:56 ` Jiuyang Liu 2021-03-16 7:32 ` Anup Patel 2021-03-16 7:32 ` Anup Patel 2021-03-16 8:29 ` Andrew Waterman 2021-03-16 8:29 ` Andrew Waterman 2021-03-16 8:40 ` Anup Patel 2021-03-16 8:40 ` Anup Patel 2021-03-16 12:05 ` Alex Ghiti 2021-03-16 12:05 ` Alex Ghiti 2021-03-16 22:03 ` Andrew Waterman 2021-03-16 22:03 ` Andrew Waterman 2021-03-18 2:10 ` Jiuyang Liu 2021-03-18 2:10 ` Jiuyang Liu 2021-03-19 7:14 ` Alex Ghiti 2021-03-19 7:14 ` Alex Ghiti 2021-03-30 23:35 ` Palmer Dabbelt 2021-03-30 23:35 ` Palmer Dabbelt 2021-03-17 4:17 ` Palmer Dabbelt 2021-03-17 4:17 ` Palmer Dabbelt
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