From: Voon Weifeng <weifeng.voon@intel.com> To: "David S . Miller" <davem@davemloft.net>, Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Abreu <joabreu@synopsys.com>, Jakub Kicinski <kuba@kernel.org>, Giuseppe Cavallaro <peppe.cavallaro@st.com>, Andrew Lunn <andrew@lunn.ch>, Alexandre Torgue <alexandre.torgue@st.com>, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Ong Boon Leong <boon.leong.ong@intel.com>, Voon Weifeng <weifeng.voon@intel.com>, Wong Vee Khee <vee.khee.wong@intel.com> Subject: [RESEND v1 net-next 0/5] net: stmmac: enable multi-vector MSI Date: Tue, 16 Mar 2021 20:18:18 +0800 [thread overview] Message-ID: <20210316121823.18659-1-weifeng.voon@intel.com> (raw) This patchset adds support for multi MSI interrupts in addition to current single common interrupt implementation. Each MSI interrupt is tied to a newly introduce interrupt service routine(ISR). Hence, each interrupt will only go through the corresponding ISR. In order to increase the efficiency, enabling multi MSI interrupt will automatically select the interrupt mode configuration INTM=1. When INTM=1, the TX/RX transfer complete signal will only asserted on corresponding sbd_perch_tx_intr_o[] or sbd_perch_rx_intr_o[] without asserting signal on the common sbd_intr_o. Hence, for each TX/RX interrupts, only the corresponding ISR will be triggered. Every vendor might have different MSI vector assignment. So, this patchset only includes multi-vector MSI assignment for Intel platform. Ong Boon Leong (4): net: stmmac: introduce DMA interrupt status masking per traffic direction net: stmmac: make stmmac_interrupt() function more friendly to MSI net: stmmac: introduce MSI Interrupt routines for mac, safety, RX & TX stmmac: intel: add support for multi-vector msi and msi-x Wong, Vee Khee (1): net: stmmac: use interrupt mode INTM=1 for multi-MSI drivers/net/ethernet/stmicro/stmmac/common.h | 21 + .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 112 +++- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 24 +- .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 + .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 24 +- .../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 30 +- .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 22 +- .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 8 +- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 6 + .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 8 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 16 + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 482 +++++++++++++++--- include/linux/stmmac.h | 9 + 14 files changed, 676 insertions(+), 96 deletions(-) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Voon Weifeng <weifeng.voon@intel.com> To: "David S . Miller" <davem@davemloft.net>, Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Abreu <joabreu@synopsys.com>, Jakub Kicinski <kuba@kernel.org>, Giuseppe Cavallaro <peppe.cavallaro@st.com>, Andrew Lunn <andrew@lunn.ch>, Alexandre Torgue <alexandre.torgue@st.com>, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Ong Boon Leong <boon.leong.ong@intel.com>, Voon Weifeng <weifeng.voon@intel.com>, Wong Vee Khee <vee.khee.wong@intel.com> Subject: [RESEND v1 net-next 0/5] net: stmmac: enable multi-vector MSI Date: Tue, 16 Mar 2021 20:18:18 +0800 [thread overview] Message-ID: <20210316121823.18659-1-weifeng.voon@intel.com> (raw) This patchset adds support for multi MSI interrupts in addition to current single common interrupt implementation. Each MSI interrupt is tied to a newly introduce interrupt service routine(ISR). Hence, each interrupt will only go through the corresponding ISR. In order to increase the efficiency, enabling multi MSI interrupt will automatically select the interrupt mode configuration INTM=1. When INTM=1, the TX/RX transfer complete signal will only asserted on corresponding sbd_perch_tx_intr_o[] or sbd_perch_rx_intr_o[] without asserting signal on the common sbd_intr_o. Hence, for each TX/RX interrupts, only the corresponding ISR will be triggered. Every vendor might have different MSI vector assignment. So, this patchset only includes multi-vector MSI assignment for Intel platform. Ong Boon Leong (4): net: stmmac: introduce DMA interrupt status masking per traffic direction net: stmmac: make stmmac_interrupt() function more friendly to MSI net: stmmac: introduce MSI Interrupt routines for mac, safety, RX & TX stmmac: intel: add support for multi-vector msi and msi-x Wong, Vee Khee (1): net: stmmac: use interrupt mode INTM=1 for multi-MSI drivers/net/ethernet/stmicro/stmmac/common.h | 21 + .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 112 +++- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 24 +- .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 + .../net/ethernet/stmicro/stmmac/dwmac4_dma.h | 24 +- .../net/ethernet/stmicro/stmmac/dwmac4_lib.c | 30 +- .../net/ethernet/stmicro/stmmac/dwmac_dma.h | 22 +- .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 8 +- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 6 + .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 8 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 16 + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 482 +++++++++++++++--- include/linux/stmmac.h | 9 + 14 files changed, 676 insertions(+), 96 deletions(-) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-03-16 12:19 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-16 12:18 Voon Weifeng [this message] 2021-03-16 12:18 ` [RESEND v1 net-next 0/5] net: stmmac: enable multi-vector MSI Voon Weifeng 2021-03-16 12:18 ` [RESEND v1 net-next 1/5] net: stmmac: introduce DMA interrupt status masking per traffic direction Voon Weifeng 2021-03-16 12:18 ` Voon Weifeng 2021-03-16 12:18 ` [RESEND v1 net-next 2/5] net: stmmac: make stmmac_interrupt() function more friendly to MSI Voon Weifeng 2021-03-16 12:18 ` Voon Weifeng 2021-03-16 21:21 ` Jakub Kicinski 2021-03-16 21:21 ` Jakub Kicinski 2021-03-16 12:18 ` [RESEND v1 net-next 3/5] net: stmmac: introduce MSI Interrupt routines for mac, safety, RX & TX Voon Weifeng 2021-03-16 12:18 ` Voon Weifeng 2021-03-16 21:29 ` Jakub Kicinski 2021-03-16 21:29 ` Jakub Kicinski 2021-03-24 8:43 ` Voon, Weifeng 2021-03-24 8:43 ` Voon, Weifeng 2021-03-16 12:18 ` [RESEND v1 net-next 4/5] stmmac: intel: add support for multi-vector msi and msi-x Voon Weifeng 2021-03-16 12:18 ` Voon Weifeng 2021-03-16 21:32 ` Jakub Kicinski 2021-03-16 21:32 ` Jakub Kicinski 2021-03-16 12:18 ` [RESEND v1 net-next 5/5] net: stmmac: use interrupt mode INTM=1 for multi-MSI Voon Weifeng 2021-03-16 12:18 ` Voon Weifeng
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210316121823.18659-1-weifeng.voon@intel.com \ --to=weifeng.voon@intel.com \ --cc=alexandre.torgue@st.com \ --cc=andrew@lunn.ch \ --cc=boon.leong.ong@intel.com \ --cc=davem@davemloft.net \ --cc=joabreu@synopsys.com \ --cc=kuba@kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-stm32@st-md-mailman.stormreply.com \ --cc=mcoquelin.stm32@gmail.com \ --cc=netdev@vger.kernel.org \ --cc=peppe.cavallaro@st.com \ --cc=vee.khee.wong@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.