* [PATCH net-next 0/1] stmmac: add PCH and PSE PTP clock setting @ 2021-03-17 1:32 ` Ong Boon Leong 0 siblings, 0 replies; 6+ messages in thread From: Ong Boon Leong @ 2021-03-17 1:32 UTC (permalink / raw) To: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S . Miller, Jakub Kicinski Cc: Maxime Coquelin, netdev, linux-stm32, linux-arm-kernel, linux-kernel, Ong Boon Leong, Voon Weifeng, Wong Vee Khee Hi, Intel mGBE controllers that are integrated into EHL, TGL SoC have different clock source selection. This patch adds the required setting for running linuxptp time-sync. The patch has been tested on both PSE (/dev/ptp0) and PCH TSN(/dev/ptp2) and the results for the time sync looks correct. ############################ PSE TSN #################################### > cat gPTP.conf [global] gmCapable 1 priority1 248 priority2 248 logAnnounceInterval 0 logSyncInterval -3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 assume_two_step 1 path_trace_enabled 1 follow_up_info 1 transportSpecific 0x1 ptp_dst_mac 01:80:C2:00:00:0E network_transport L2 delay_mechanism P2P ingressLatency 231 egressLatency 147 tx_timestamp_timeout 50 > /usr/local/sbin/ptp4l -v 3.1 ################################# # Start ptp4l eth0 [verbose mode] ################################# > /usr/local/sbin/ptp4l -P2Hi eth0 -f gPTP.conf --step_threshold=1 -m ptp4l[8380.510]: selected /dev/ptp0 as PTP clock ptp4l[8380.535]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8380.535]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8381.655]: port 1: link down ptp4l[8381.655]: port 1: LISTENING to FAULTY on FAULT_DETECTED (FT_UNSPECIFIED) ptp4l[8381.676]: selected local clock f6cd9d.fffe.e6dc36 as best master ptp4l[8381.676]: port 1: assuming the grand master role ptp4l[8383.705]: port 1: link up ptp4l[8383.727]: port 1: FAULTY to LISTENING on INIT_COMPLETE ptp4l[8387.099]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES ptp4l[8387.099]: selected local clock f6cd9d.fffe.e6dc36 as best master ptp4l[8387.099]: port 1: assuming the grand master role ptp4l[8388.357]: port 1: new foreign master d63d87.fffe.60a9eb-1 ptp4l[8390.357]: selected best master clock d63d87.fffe.60a9eb ptp4l[8390.357]: port 1: MASTER to UNCALIBRATED on RS_SLAVE ptp4l[8390.981]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[8391.607]: rms 24333463708388 max 48666927416912 freq -1919 +/- 725 delay 101 +/- 0 ptp4l[8392.607]: rms 2 max 6 freq -2194 +/- 3 delay 101 +/- 0 ptp4l[8393.607]: rms 5 max 10 freq -2192 +/- 7 delay 101 +/- 0 ptp4l[8394.607]: rms 4 max 5 freq -2195 +/- 5 delay 100 +/- 0 ptp4l[8395.607]: rms 4 max 9 freq -2198 +/- 4 delay 100 +/- 0 ptp4l[8396.607]: rms 5 max 9 freq -2201 +/- 6 delay 100 +/- 0 ptp4l[8397.607]: rms 6 max 8 freq -2196 +/- 8 delay 101 +/- 0 ptp4l[8398.607]: rms 5 max 9 freq -2195 +/- 7 delay 102 +/- 0 ptp4l[8399.607]: rms 7 max 13 freq -2199 +/- 9 delay 102 +/- 0 ptp4l[8400.608]: rms 6 max 14 freq -2198 +/- 8 delay 101 +/- 0 ptp4l[8401.608]: rms 8 max 10 freq -2195 +/- 10 delay 101 +/- 0 ######################################################################### ############################ PCH TSN #################################### > cat gPTP.conf [global] gmCapable 1 priority1 248 priority2 248 logAnnounceInterval 0 logSyncInterval -3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 assume_two_step 1 path_trace_enabled 1 follow_up_info 1 transportSpecific 0x1 ptp_dst_mac 01:80:C2:00:00:0E network_transport L2 delay_mechanism P2P ingressLatency 503 egressLatency 275 tx_timestamp_timeout 50 > /usr/local/sbin/ptp4l -v 3.1 ################################# # Start ptp4l eth2 [verbose mode] ################################# > /usr/local/sbin/ptp4l -P2Hi eth2 -f gPTP.conf --step_threshold=1 -m ptp4l[8526.902]: selected /dev/ptp2 as PTP clock ptp4l[8526.957]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8526.957]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8526.957]: port 1: link down ptp4l[8526.957]: port 1: LISTENING to FAULTY on FAULT_DETECTED (FT_UNSPECIFIED) ptp4l[8526.978]: selected local clock 7ab054.fffe.8aaa86 as best master ptp4l[8526.979]: port 1: assuming the grand master role ptp4l[8528.026]: port 1: link up ptp4l[8528.058]: port 1: FAULTY to LISTENING on INIT_COMPLETE ptp4l[8531.070]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES ptp4l[8531.070]: selected local clock 7ab054.fffe.8aaa86 as best master ptp4l[8531.070]: port 1: assuming the grand master role ptp4l[8532.878]: port 1: new foreign master 5ee86b.fffe.dd4586-1 ptp4l[8534.878]: selected best master clock 5ee86b.fffe.dd4586 ptp4l[8534.878]: port 1: MASTER to UNCALIBRATED on RS_SLAVE ptp4l[8535.387]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[8536.012]: rms 24333477164408 max 48666954328964 freq -1980 +/- 749 delay 224 +/- 0 ptp4l[8537.012]: rms 48 max 61 freq -2195 +/- 13 delay 221 +/- 0 ptp4l[8538.012]: rms 29 max 43 freq -2182 +/- 6 delay 221 +/- 0 ptp4l[8539.012]: rms 13 max 27 freq -2192 +/- 14 delay 221 +/- 0 ptp4l[8540.012]: rms 8 max 13 freq -2205 +/- 10 delay 221 +/- 0 ptp4l[8541.013]: rms 12 max 20 freq -2217 +/- 13 delay 224 +/- 0 ptp4l[8542.013]: rms 7 max 17 freq -2214 +/- 10 delay 221 +/- 0 ptp4l[8543.013]: rms 7 max 11 freq -2208 +/- 10 delay 221 +/- 0 ptp4l[8544.013]: rms 8 max 16 freq -2214 +/- 10 delay 220 +/- 0 ######################################################################### Thanks Boon Leong Wong, Vee Khee (1): stmmac: intel: Add PSE and PCH PTP clock source selection .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 46 +++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 7 +++ .../net/ethernet/stmicro/stmmac/stmmac_ptp.c | 3 ++ include/linux/stmmac.h | 1 + 4 files changed, 57 insertions(+) -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH net-next 0/1] stmmac: add PCH and PSE PTP clock setting @ 2021-03-17 1:32 ` Ong Boon Leong 0 siblings, 0 replies; 6+ messages in thread From: Ong Boon Leong @ 2021-03-17 1:32 UTC (permalink / raw) To: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S . Miller, Jakub Kicinski Cc: Maxime Coquelin, netdev, linux-stm32, linux-arm-kernel, linux-kernel, Ong Boon Leong, Voon Weifeng, Wong Vee Khee Hi, Intel mGBE controllers that are integrated into EHL, TGL SoC have different clock source selection. This patch adds the required setting for running linuxptp time-sync. The patch has been tested on both PSE (/dev/ptp0) and PCH TSN(/dev/ptp2) and the results for the time sync looks correct. ############################ PSE TSN #################################### > cat gPTP.conf [global] gmCapable 1 priority1 248 priority2 248 logAnnounceInterval 0 logSyncInterval -3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 assume_two_step 1 path_trace_enabled 1 follow_up_info 1 transportSpecific 0x1 ptp_dst_mac 01:80:C2:00:00:0E network_transport L2 delay_mechanism P2P ingressLatency 231 egressLatency 147 tx_timestamp_timeout 50 > /usr/local/sbin/ptp4l -v 3.1 ################################# # Start ptp4l eth0 [verbose mode] ################################# > /usr/local/sbin/ptp4l -P2Hi eth0 -f gPTP.conf --step_threshold=1 -m ptp4l[8380.510]: selected /dev/ptp0 as PTP clock ptp4l[8380.535]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8380.535]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8381.655]: port 1: link down ptp4l[8381.655]: port 1: LISTENING to FAULTY on FAULT_DETECTED (FT_UNSPECIFIED) ptp4l[8381.676]: selected local clock f6cd9d.fffe.e6dc36 as best master ptp4l[8381.676]: port 1: assuming the grand master role ptp4l[8383.705]: port 1: link up ptp4l[8383.727]: port 1: FAULTY to LISTENING on INIT_COMPLETE ptp4l[8387.099]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES ptp4l[8387.099]: selected local clock f6cd9d.fffe.e6dc36 as best master ptp4l[8387.099]: port 1: assuming the grand master role ptp4l[8388.357]: port 1: new foreign master d63d87.fffe.60a9eb-1 ptp4l[8390.357]: selected best master clock d63d87.fffe.60a9eb ptp4l[8390.357]: port 1: MASTER to UNCALIBRATED on RS_SLAVE ptp4l[8390.981]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[8391.607]: rms 24333463708388 max 48666927416912 freq -1919 +/- 725 delay 101 +/- 0 ptp4l[8392.607]: rms 2 max 6 freq -2194 +/- 3 delay 101 +/- 0 ptp4l[8393.607]: rms 5 max 10 freq -2192 +/- 7 delay 101 +/- 0 ptp4l[8394.607]: rms 4 max 5 freq -2195 +/- 5 delay 100 +/- 0 ptp4l[8395.607]: rms 4 max 9 freq -2198 +/- 4 delay 100 +/- 0 ptp4l[8396.607]: rms 5 max 9 freq -2201 +/- 6 delay 100 +/- 0 ptp4l[8397.607]: rms 6 max 8 freq -2196 +/- 8 delay 101 +/- 0 ptp4l[8398.607]: rms 5 max 9 freq -2195 +/- 7 delay 102 +/- 0 ptp4l[8399.607]: rms 7 max 13 freq -2199 +/- 9 delay 102 +/- 0 ptp4l[8400.608]: rms 6 max 14 freq -2198 +/- 8 delay 101 +/- 0 ptp4l[8401.608]: rms 8 max 10 freq -2195 +/- 10 delay 101 +/- 0 ######################################################################### ############################ PCH TSN #################################### > cat gPTP.conf [global] gmCapable 1 priority1 248 priority2 248 logAnnounceInterval 0 logSyncInterval -3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 assume_two_step 1 path_trace_enabled 1 follow_up_info 1 transportSpecific 0x1 ptp_dst_mac 01:80:C2:00:00:0E network_transport L2 delay_mechanism P2P ingressLatency 503 egressLatency 275 tx_timestamp_timeout 50 > /usr/local/sbin/ptp4l -v 3.1 ################################# # Start ptp4l eth2 [verbose mode] ################################# > /usr/local/sbin/ptp4l -P2Hi eth2 -f gPTP.conf --step_threshold=1 -m ptp4l[8526.902]: selected /dev/ptp2 as PTP clock ptp4l[8526.957]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8526.957]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[8526.957]: port 1: link down ptp4l[8526.957]: port 1: LISTENING to FAULTY on FAULT_DETECTED (FT_UNSPECIFIED) ptp4l[8526.978]: selected local clock 7ab054.fffe.8aaa86 as best master ptp4l[8526.979]: port 1: assuming the grand master role ptp4l[8528.026]: port 1: link up ptp4l[8528.058]: port 1: FAULTY to LISTENING on INIT_COMPLETE ptp4l[8531.070]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES ptp4l[8531.070]: selected local clock 7ab054.fffe.8aaa86 as best master ptp4l[8531.070]: port 1: assuming the grand master role ptp4l[8532.878]: port 1: new foreign master 5ee86b.fffe.dd4586-1 ptp4l[8534.878]: selected best master clock 5ee86b.fffe.dd4586 ptp4l[8534.878]: port 1: MASTER to UNCALIBRATED on RS_SLAVE ptp4l[8535.387]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED ptp4l[8536.012]: rms 24333477164408 max 48666954328964 freq -1980 +/- 749 delay 224 +/- 0 ptp4l[8537.012]: rms 48 max 61 freq -2195 +/- 13 delay 221 +/- 0 ptp4l[8538.012]: rms 29 max 43 freq -2182 +/- 6 delay 221 +/- 0 ptp4l[8539.012]: rms 13 max 27 freq -2192 +/- 14 delay 221 +/- 0 ptp4l[8540.012]: rms 8 max 13 freq -2205 +/- 10 delay 221 +/- 0 ptp4l[8541.013]: rms 12 max 20 freq -2217 +/- 13 delay 224 +/- 0 ptp4l[8542.013]: rms 7 max 17 freq -2214 +/- 10 delay 221 +/- 0 ptp4l[8543.013]: rms 7 max 11 freq -2208 +/- 10 delay 221 +/- 0 ptp4l[8544.013]: rms 8 max 16 freq -2214 +/- 10 delay 220 +/- 0 ######################################################################### Thanks Boon Leong Wong, Vee Khee (1): stmmac: intel: Add PSE and PCH PTP clock source selection .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 46 +++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 7 +++ .../net/ethernet/stmicro/stmmac/stmmac_ptp.c | 3 ++ include/linux/stmmac.h | 1 + 4 files changed, 57 insertions(+) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH net-next 1/1] stmmac: intel: Add PSE and PCH PTP clock source selection 2021-03-17 1:32 ` Ong Boon Leong @ 2021-03-17 1:32 ` Ong Boon Leong -1 siblings, 0 replies; 6+ messages in thread From: Ong Boon Leong @ 2021-03-17 1:32 UTC (permalink / raw) To: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S . Miller, Jakub Kicinski Cc: Maxime Coquelin, netdev, linux-stm32, linux-arm-kernel, linux-kernel, Ong Boon Leong, Voon Weifeng, Wong Vee Khee From: "Wong, Vee Khee" <vee.khee.wong@intel.com> Intel mGbE variant implemented in EHL and TGL can be set to select different clock frequency based on GPO bits in MAC_GPIO_STATUS register. We introduce a new "void (*ptp_clk_freq_config)(void *priv)" in platform data so that if a platform is required to configure the frequency of clock source, in this case Intel mGBE does, the platform-specific configuration of the PTP clock setting is done when stmmac_ptp_register() is called. Signed-off-by: Wong, Vee Khee <vee.khee.wong@intel.com> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Co-developed-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 46 +++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 7 +++ .../net/ethernet/stmicro/stmmac/stmmac_ptp.c | 3 ++ include/linux/stmmac.h | 1 + 4 files changed, 57 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index c49646773871..763b549e3c2d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -12,8 +12,18 @@ #define INTEL_MGBE_ADHOC_ADDR 0x15 #define INTEL_MGBE_XPCS_ADDR 0x16 +/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */ +#define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3) +#define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) +#define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3) +#define PSE_PTP_CLK_FREQ_256MHZ (0) +#define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0) +#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) +#define PCH_PTP_CLK_FREQ_200MHZ (0) + struct intel_priv_data { int mdio_adhoc_addr; /* mdio address for serdes & etc */ + bool is_pse; }; /* This struct is used to associate PCI Function of MAC controller on a board, @@ -204,6 +214,32 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) } } +/* Program PTP Clock Frequency for different variant of + * Intel mGBE that has slightly different GPO mapping + */ +static void intel_mgbe_ptp_clk_freq_config(void *npriv) +{ + struct stmmac_priv *priv = (struct stmmac_priv *)npriv; + struct intel_priv_data *intel_priv; + u32 gpio_value; + + intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; + + gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); + + if (intel_priv->is_pse) { + /* For PSE GbE, use 200MHz */ + gpio_value &= ~PSE_PTP_CLK_FREQ_MASK; + gpio_value |= PSE_PTP_CLK_FREQ_200MHZ; + } else { + /* For PCH GbE, use 200MHz */ + gpio_value &= ~PCH_PTP_CLK_FREQ_MASK; + gpio_value |= PCH_PTP_CLK_FREQ_200MHZ; + } + + writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); +} + static void common_default_data(struct plat_stmmacenet_data *plat) { plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ @@ -322,6 +358,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, return ret; } + plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; + /* Set default value for multicast hash bins */ plat->multicast_filter_bins = HASH_TABLE_SIZE; @@ -391,8 +429,12 @@ static struct stmmac_pci_info ehl_rgmii1g_info = { static int ehl_pse0_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + + intel_priv->is_pse = true; plat->bus_id = 2; plat->addr64 = 32; + return ehl_common_data(pdev, plat); } @@ -423,8 +465,12 @@ static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { static int ehl_pse1_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + + intel_priv->is_pse = true; plat->bus_id = 3; plat->addr64 = 32; + return ehl_common_data(pdev, plat); } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 82df91c130f7..ef8502d2b6e6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -42,6 +42,7 @@ #define GMAC_HW_FEATURE3 0x00000128 #define GMAC_MDIO_ADDR 0x00000200 #define GMAC_MDIO_DATA 0x00000204 +#define GMAC_GPIO_STATUS 0x0000020C #define GMAC_ARP_ADDR 0x00000210 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) @@ -278,6 +279,12 @@ enum power_event { #define GMAC_HW_FEAT_DVLAN BIT(5) #define GMAC_HW_FEAT_NRVF GENMASK(2, 0) +/* GMAC GPIO Status reg */ +#define GMAC_GPO0 BIT(16) +#define GMAC_GPO1 BIT(17) +#define GMAC_GPO2 BIT(18) +#define GMAC_GPO3 BIT(19) + /* MAC HW ADDR regs */ #define GMAC_HI_DCS GENMASK(18, 16) #define GMAC_HI_DCS_SHIFT 16 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c index 0989e2bb6ee3..8b10fd10446f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c @@ -192,6 +192,9 @@ void stmmac_ptp_register(struct stmmac_priv *priv) { int i; + if (priv->plat->ptp_clk_freq_config) + priv->plat->ptp_clk_freq_config(priv); + for (i = 0; i < priv->dma_cap.pps_out_num; i++) { if (i >= STMMAC_PPS_MAX) break; diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 51004ebd0540..10abc80b601e 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -181,6 +181,7 @@ struct plat_stmmacenet_data { void (*fix_mac_speed)(void *priv, unsigned int speed); int (*serdes_powerup)(struct net_device *ndev, void *priv); void (*serdes_powerdown)(struct net_device *ndev, void *priv); + void (*ptp_clk_freq_config)(void *priv); int (*init)(struct platform_device *pdev, void *priv); void (*exit)(struct platform_device *pdev, void *priv); struct mac_device_info *(*setup)(void *priv); -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH net-next 1/1] stmmac: intel: Add PSE and PCH PTP clock source selection @ 2021-03-17 1:32 ` Ong Boon Leong 0 siblings, 0 replies; 6+ messages in thread From: Ong Boon Leong @ 2021-03-17 1:32 UTC (permalink / raw) To: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, David S . Miller, Jakub Kicinski Cc: Maxime Coquelin, netdev, linux-stm32, linux-arm-kernel, linux-kernel, Ong Boon Leong, Voon Weifeng, Wong Vee Khee From: "Wong, Vee Khee" <vee.khee.wong@intel.com> Intel mGbE variant implemented in EHL and TGL can be set to select different clock frequency based on GPO bits in MAC_GPIO_STATUS register. We introduce a new "void (*ptp_clk_freq_config)(void *priv)" in platform data so that if a platform is required to configure the frequency of clock source, in this case Intel mGBE does, the platform-specific configuration of the PTP clock setting is done when stmmac_ptp_register() is called. Signed-off-by: Wong, Vee Khee <vee.khee.wong@intel.com> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Co-developed-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 46 +++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 7 +++ .../net/ethernet/stmicro/stmmac/stmmac_ptp.c | 3 ++ include/linux/stmmac.h | 1 + 4 files changed, 57 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index c49646773871..763b549e3c2d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -12,8 +12,18 @@ #define INTEL_MGBE_ADHOC_ADDR 0x15 #define INTEL_MGBE_XPCS_ADDR 0x16 +/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */ +#define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3) +#define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) +#define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3) +#define PSE_PTP_CLK_FREQ_256MHZ (0) +#define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0) +#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0) +#define PCH_PTP_CLK_FREQ_200MHZ (0) + struct intel_priv_data { int mdio_adhoc_addr; /* mdio address for serdes & etc */ + bool is_pse; }; /* This struct is used to associate PCI Function of MAC controller on a board, @@ -204,6 +214,32 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) } } +/* Program PTP Clock Frequency for different variant of + * Intel mGBE that has slightly different GPO mapping + */ +static void intel_mgbe_ptp_clk_freq_config(void *npriv) +{ + struct stmmac_priv *priv = (struct stmmac_priv *)npriv; + struct intel_priv_data *intel_priv; + u32 gpio_value; + + intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; + + gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); + + if (intel_priv->is_pse) { + /* For PSE GbE, use 200MHz */ + gpio_value &= ~PSE_PTP_CLK_FREQ_MASK; + gpio_value |= PSE_PTP_CLK_FREQ_200MHZ; + } else { + /* For PCH GbE, use 200MHz */ + gpio_value &= ~PCH_PTP_CLK_FREQ_MASK; + gpio_value |= PCH_PTP_CLK_FREQ_200MHZ; + } + + writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); +} + static void common_default_data(struct plat_stmmacenet_data *plat) { plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ @@ -322,6 +358,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, return ret; } + plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; + /* Set default value for multicast hash bins */ plat->multicast_filter_bins = HASH_TABLE_SIZE; @@ -391,8 +429,12 @@ static struct stmmac_pci_info ehl_rgmii1g_info = { static int ehl_pse0_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + + intel_priv->is_pse = true; plat->bus_id = 2; plat->addr64 = 32; + return ehl_common_data(pdev, plat); } @@ -423,8 +465,12 @@ static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { static int ehl_pse1_common_data(struct pci_dev *pdev, struct plat_stmmacenet_data *plat) { + struct intel_priv_data *intel_priv = plat->bsp_priv; + + intel_priv->is_pse = true; plat->bus_id = 3; plat->addr64 = 32; + return ehl_common_data(pdev, plat); } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 82df91c130f7..ef8502d2b6e6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -42,6 +42,7 @@ #define GMAC_HW_FEATURE3 0x00000128 #define GMAC_MDIO_ADDR 0x00000200 #define GMAC_MDIO_DATA 0x00000204 +#define GMAC_GPIO_STATUS 0x0000020C #define GMAC_ARP_ADDR 0x00000210 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) @@ -278,6 +279,12 @@ enum power_event { #define GMAC_HW_FEAT_DVLAN BIT(5) #define GMAC_HW_FEAT_NRVF GENMASK(2, 0) +/* GMAC GPIO Status reg */ +#define GMAC_GPO0 BIT(16) +#define GMAC_GPO1 BIT(17) +#define GMAC_GPO2 BIT(18) +#define GMAC_GPO3 BIT(19) + /* MAC HW ADDR regs */ #define GMAC_HI_DCS GENMASK(18, 16) #define GMAC_HI_DCS_SHIFT 16 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c index 0989e2bb6ee3..8b10fd10446f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c @@ -192,6 +192,9 @@ void stmmac_ptp_register(struct stmmac_priv *priv) { int i; + if (priv->plat->ptp_clk_freq_config) + priv->plat->ptp_clk_freq_config(priv); + for (i = 0; i < priv->dma_cap.pps_out_num; i++) { if (i >= STMMAC_PPS_MAX) break; diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 51004ebd0540..10abc80b601e 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -181,6 +181,7 @@ struct plat_stmmacenet_data { void (*fix_mac_speed)(void *priv, unsigned int speed); int (*serdes_powerup)(struct net_device *ndev, void *priv); void (*serdes_powerdown)(struct net_device *ndev, void *priv); + void (*ptp_clk_freq_config)(void *priv); int (*init)(struct platform_device *pdev, void *priv); void (*exit)(struct platform_device *pdev, void *priv); struct mac_device_info *(*setup)(void *priv); -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH net-next 0/1] stmmac: add PCH and PSE PTP clock setting 2021-03-17 1:32 ` Ong Boon Leong @ 2021-03-19 2:20 ` patchwork-bot+netdevbpf -1 siblings, 0 replies; 6+ messages in thread From: patchwork-bot+netdevbpf @ 2021-03-19 2:20 UTC (permalink / raw) To: Ong Boon Leong Cc: peppe.cavallaro, alexandre.torgue, joabreu, davem, kuba, mcoquelin.stm32, netdev, linux-stm32, linux-arm-kernel, linux-kernel, weifeng.voon, vee.khee.wong Hello: This patch was applied to netdev/net-next.git (refs/heads/master): On Wed, 17 Mar 2021 09:32:46 +0800 you wrote: > Hi, > > Intel mGBE controllers that are integrated into EHL, TGL SoC have > different clock source selection. This patch adds the required setting for > running linuxptp time-sync. > > The patch has been tested on both PSE (/dev/ptp0) and PCH TSN(/dev/ptp2) > and the results for the time sync looks correct. > > [...] Here is the summary with links: - [net-next,1/1] stmmac: intel: Add PSE and PCH PTP clock source selection https://git.kernel.org/netdev/net-next/c/76da35dc99af You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net-next 0/1] stmmac: add PCH and PSE PTP clock setting @ 2021-03-19 2:20 ` patchwork-bot+netdevbpf 0 siblings, 0 replies; 6+ messages in thread From: patchwork-bot+netdevbpf @ 2021-03-19 2:20 UTC (permalink / raw) To: Ong Boon Leong Cc: peppe.cavallaro, alexandre.torgue, joabreu, davem, kuba, mcoquelin.stm32, netdev, linux-stm32, linux-arm-kernel, linux-kernel, weifeng.voon, vee.khee.wong Hello: This patch was applied to netdev/net-next.git (refs/heads/master): On Wed, 17 Mar 2021 09:32:46 +0800 you wrote: > Hi, > > Intel mGBE controllers that are integrated into EHL, TGL SoC have > different clock source selection. This patch adds the required setting for > running linuxptp time-sync. > > The patch has been tested on both PSE (/dev/ptp0) and PCH TSN(/dev/ptp2) > and the results for the time sync looks correct. > > [...] Here is the summary with links: - [net-next,1/1] stmmac: intel: Add PSE and PCH PTP clock source selection https://git.kernel.org/netdev/net-next/c/76da35dc99af You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-19 2:22 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-17 1:32 [PATCH net-next 0/1] stmmac: add PCH and PSE PTP clock setting Ong Boon Leong 2021-03-17 1:32 ` Ong Boon Leong 2021-03-17 1:32 ` [PATCH net-next 1/1] stmmac: intel: Add PSE and PCH PTP clock source selection Ong Boon Leong 2021-03-17 1:32 ` Ong Boon Leong 2021-03-19 2:20 ` [PATCH net-next 0/1] stmmac: add PCH and PSE PTP clock setting patchwork-bot+netdevbpf 2021-03-19 2:20 ` patchwork-bot+netdevbpf
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