* [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core
@ 2021-03-23 8:35 Green Wan
2021-03-23 8:35 ` [RFC PATCH v2 2/2] board: sifive: unmatched: clear feature disable CSR Green Wan
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Green Wan @ 2021-03-23 8:35 UTC (permalink / raw)
To: u-boot
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the calback, they must be able
to run the same setup.
Signed-off-by: Green Wan <green.wan@sifive.com>
---
arch/riscv/cpu/start.S | 5 +++++
arch/riscv/lib/spl.c | 4 ++++
2 files changed, 9 insertions(+)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..5c7d4da9e2 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,11 @@ call_board_init_f_0:
mv sp, a0
#endif
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+call_riscv_hart_early_init:
+ jal riscv_hart_early_init
+#endif
+
#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index 8baee07bea..e5b1affbfc 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -14,6 +14,10 @@
DECLARE_GLOBAL_DATA_PTR;
+__weak void riscv_hart_early_init(void)
+{
+}
+
__weak int spl_board_init_f(void)
{
return 0;
--
2.31.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC PATCH v2 2/2] board: sifive: unmatched: clear feature disable CSR
2021-03-23 8:35 [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core Green Wan
@ 2021-03-23 8:35 ` Green Wan
2021-03-24 0:32 ` Sean Anderson
2021-03-24 0:27 ` [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core Sean Anderson
2021-03-26 1:22 ` Leo Liang
2 siblings, 1 reply; 9+ messages in thread
From: Green Wan @ 2021-03-23 8:35 UTC (permalink / raw)
To: u-boot
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
Signed-off-by: Green Wan <green.wan@sifive.com>
---
board/sifive/unmatched/spl.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 5e1333b09a..d09d129dc9 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -22,6 +22,19 @@
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
+void riscv_hart_early_init(void)
+{
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ /*
+ * Feature Disable CSR
+ *
+ * Clear feature disable CSR to '0' to turn on all features for
+ * each core. This operatioin must be in m-mode.
+ */
+ asm volatile ("csrwi 0x7c1, 0");
+#endif
+}
+
int spl_board_init_f(void)
{
int ret;
--
2.31.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core
2021-03-23 8:35 [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core Green Wan
2021-03-23 8:35 ` [RFC PATCH v2 2/2] board: sifive: unmatched: clear feature disable CSR Green Wan
@ 2021-03-24 0:27 ` Sean Anderson
2021-03-26 1:22 ` Leo Liang
2 siblings, 0 replies; 9+ messages in thread
From: Sean Anderson @ 2021-03-24 0:27 UTC (permalink / raw)
To: u-boot
On 3/23/21 4:35 AM, Green Wan wrote:
> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> allow different riscv hart perform setup code for each hart as early
> as possible. Since all the harts enter the calback, they must be able
nit: callback
> to run the same setup.
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> ---
> arch/riscv/cpu/start.S | 5 +++++
> arch/riscv/lib/spl.c | 4 ++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 8589509e01..5c7d4da9e2 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -117,6 +117,11 @@ call_board_init_f_0:
> mv sp, a0
> #endif
>
> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> +call_riscv_hart_early_init:
> + jal riscv_hart_early_init
> +#endif
> +
> #ifndef CONFIG_XIP
> /*
> * Pick hart to initialize global data and run U-Boot. The other harts
> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
> index 8baee07bea..e5b1affbfc 100644
> --- a/arch/riscv/lib/spl.c
> +++ b/arch/riscv/lib/spl.c
> @@ -14,6 +14,10 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +__weak void riscv_hart_early_init(void)
> +{
> +}
> +
Can you add some documentation for what the purpose of this function is
and what the limitations are? In particular, this function cannot access
gd.
--Sean
> __weak int spl_board_init_f(void)
> {
> return 0;
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC PATCH v2 2/2] board: sifive: unmatched: clear feature disable CSR
2021-03-23 8:35 ` [RFC PATCH v2 2/2] board: sifive: unmatched: clear feature disable CSR Green Wan
@ 2021-03-24 0:32 ` Sean Anderson
0 siblings, 0 replies; 9+ messages in thread
From: Sean Anderson @ 2021-03-24 0:32 UTC (permalink / raw)
To: u-boot
On 3/23/21 4:35 AM, Green Wan wrote:
> Clear feature disable CSR to turn on all features of hart. The detail
> is specified at section, 'SiFive Feature Disable CSR', in user manual
>
> https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> ---
> board/sifive/unmatched/spl.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
> index 5e1333b09a..d09d129dc9 100644
> --- a/board/sifive/unmatched/spl.c
> +++ b/board/sifive/unmatched/spl.c
> @@ -22,6 +22,19 @@
> #define MODE_SELECT_SD 0xb
> #define MODE_SELECT_MASK GENMASK(3, 0)
>
> +void riscv_hart_early_init(void)
> +{
> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
use
if (CONFIG_IS_ENABLED(RISCV_MMODE)
please
> + /*
> + * Feature Disable CSR
> + *
> + * Clear feature disable CSR to '0' to turn on all features for
> + * each core. This operatioin must be in m-mode.
nit: operation
> + */
> + asm volatile ("csrwi 0x7c1, 0");
Perhaps
#define CSR_U74_FEATURE_DISABLE 0x7c1
csr_write(CSR_U74_FEATURE_DISABLE, 0);
> +#endif
> +}
> +
> int spl_board_init_f(void)
> {
> int ret;
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core
2021-03-23 8:35 [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core Green Wan
2021-03-23 8:35 ` [RFC PATCH v2 2/2] board: sifive: unmatched: clear feature disable CSR Green Wan
2021-03-24 0:27 ` [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core Sean Anderson
@ 2021-03-26 1:22 ` Leo Liang
2021-03-26 1:34 ` Sean Anderson
2 siblings, 1 reply; 9+ messages in thread
From: Leo Liang @ 2021-03-26 1:22 UTC (permalink / raw)
To: u-boot
Hi Green,
On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote:
> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> allow different riscv hart perform setup code for each hart as early
> as possible. Since all the harts enter the calback, they must be able
> to run the same setup.
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> ---
> arch/riscv/cpu/start.S | 5 +++++
> arch/riscv/lib/spl.c | 4 ++++
This patch fails to compile for some defconfigs.
(CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results)
Maybe we should come up with a better place to add this function.
Best regards,
Leo
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 8589509e01..5c7d4da9e2 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -117,6 +117,11 @@ call_board_init_f_0:
> mv sp, a0
> #endif
>
> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> +call_riscv_hart_early_init:
> + jal riscv_hart_early_init
> +#endif
> +
> #ifndef CONFIG_XIP
> /*
> * Pick hart to initialize global data and run U-Boot. The other harts
> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
> index 8baee07bea..e5b1affbfc 100644
> --- a/arch/riscv/lib/spl.c
> +++ b/arch/riscv/lib/spl.c
> @@ -14,6 +14,10 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +__weak void riscv_hart_early_init(void)
> +{
> +}
> +
> __weak int spl_board_init_f(void)
> {
> return 0;
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core
2021-03-26 1:22 ` Leo Liang
@ 2021-03-26 1:34 ` Sean Anderson
2021-03-26 9:03 ` Green Wan
0 siblings, 1 reply; 9+ messages in thread
From: Sean Anderson @ 2021-03-26 1:34 UTC (permalink / raw)
To: u-boot
On 3/25/21 9:22 PM, Leo Liang wrote:
> Hi Green,
>
> On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote:
>> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
>> allow different riscv hart perform setup code for each hart as early
>> as possible. Since all the harts enter the calback, they must be able
>> to run the same setup.
>>
>> Signed-off-by: Green Wan <green.wan@sifive.com>
>> ---
>> arch/riscv/cpu/start.S | 5 +++++
>> arch/riscv/lib/spl.c | 4 ++++
>
> This patch fails to compile for some defconfigs.
> (CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results)
>
> Maybe we should come up with a better place to add this function.
arch/riscv/cpu/cpu.c is a good candidate.
--Sean
>
> Best regards,
> Leo
>
>> 2 files changed, 9 insertions(+)
>>
>> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
>> index 8589509e01..5c7d4da9e2 100644
>> --- a/arch/riscv/cpu/start.S
>> +++ b/arch/riscv/cpu/start.S
>> @@ -117,6 +117,11 @@ call_board_init_f_0:
>> mv sp, a0
>> #endif
>>
>> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
>> +call_riscv_hart_early_init:
>> + jal riscv_hart_early_init
>> +#endif
>> +
>> #ifndef CONFIG_XIP
>> /*
>> * Pick hart to initialize global data and run U-Boot. The other harts
>> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
>> index 8baee07bea..e5b1affbfc 100644
>> --- a/arch/riscv/lib/spl.c
>> +++ b/arch/riscv/lib/spl.c
>> @@ -14,6 +14,10 @@
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> +__weak void riscv_hart_early_init(void)
>> +{
>> +}
>> +
>> __weak int spl_board_init_f(void)
>> {
>> return 0;
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core
2021-03-26 1:34 ` Sean Anderson
@ 2021-03-26 9:03 ` Green Wan
2021-03-29 2:23 ` [RFC PATCH v3 " Leo Liang
0 siblings, 1 reply; 9+ messages in thread
From: Green Wan @ 2021-03-26 9:03 UTC (permalink / raw)
To: u-boot
On Fri, Mar 26, 2021 at 9:34 AM Sean Anderson <seanga2@gmail.com> wrote:
>
> On 3/25/21 9:22 PM, Leo Liang wrote:
> > Hi Green,
> >
> > On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote:
> >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> >> allow different riscv hart perform setup code for each hart as early
> >> as possible. Since all the harts enter the calback, they must be able
> >> to run the same setup.
> >>
> >> Signed-off-by: Green Wan <green.wan@sifive.com>
> >> ---
> >> arch/riscv/cpu/start.S | 5 +++++
> >> arch/riscv/lib/spl.c | 4 ++++
> >
> > This patch fails to compile for some defconfigs.
> > (CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results)
> >
> > Maybe we should come up with a better place to add this function.
>
> arch/riscv/cpu/cpu.c is a good candidate.
Hi Leo,
Thanks for reporting the result. Looks like the test doesn't use
"CONFIG_SPL_BUILD"? Thanks to Sean's suggestion, I will move dummy
riscv_hart_early_init() from ./arch/riscv/lib/spl.c to
./arch/riscv/cpu/cpu.c to create the next patch.
BTW, it's nice if you can share the .config file or CONFIG_* related
to CPU? I'd like to check around whether there are other possibilities
to break the code building? Thanks,
-- Green
>
> --Sean
>
> >
> > Best regards,
> > Leo
> >
> >> 2 files changed, 9 insertions(+)
> >>
> >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> >> index 8589509e01..5c7d4da9e2 100644
> >> --- a/arch/riscv/cpu/start.S
> >> +++ b/arch/riscv/cpu/start.S
> >> @@ -117,6 +117,11 @@ call_board_init_f_0:
> >> mv sp, a0
> >> #endif
> >>
> >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> >> +call_riscv_hart_early_init:
> >> + jal riscv_hart_early_init
> >> +#endif
> >> +
> >> #ifndef CONFIG_XIP
> >> /*
> >> * Pick hart to initialize global data and run U-Boot. The other harts
> >> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
> >> index 8baee07bea..e5b1affbfc 100644
> >> --- a/arch/riscv/lib/spl.c
> >> +++ b/arch/riscv/lib/spl.c
> >> @@ -14,6 +14,10 @@
> >>
> >> DECLARE_GLOBAL_DATA_PTR;
> >>
> >> +__weak void riscv_hart_early_init(void)
> >> +{
> >> +}
> >> +
> >> __weak int spl_board_init_f(void)
> >> {
> >> return 0;
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC PATCH v3 1/2] arch: riscv: cpu: Add callback to init each core
2021-03-26 9:03 ` Green Wan
@ 2021-03-29 2:23 ` Leo Liang
2021-03-29 2:32 ` Green Wan
0 siblings, 1 reply; 9+ messages in thread
From: Leo Liang @ 2021-03-29 2:23 UTC (permalink / raw)
To: u-boot
On Fri, Mar 26, 2021 at 05:03:54PM +0800, Green Wan wrote:
> On Fri, Mar 26, 2021 at 9:34 AM Sean Anderson <seanga2@gmail.com> wrote:
> >
> > On 3/25/21 9:22 PM, Leo Liang wrote:
> > > Hi Green,
> > >
> > > On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote:
> > >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> > >> allow different riscv hart perform setup code for each hart as early
> > >> as possible. Since all the harts enter the calback, they must be able
> > >> to run the same setup.
> > >>
> > >> Signed-off-by: Green Wan <green.wan@sifive.com>
> > >> ---
> > >> arch/riscv/cpu/start.S | 5 +++++
> > >> arch/riscv/lib/spl.c | 4 ++++
> > >
> > > This patch fails to compile for some defconfigs.
> > > (CI result: https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results)
> > >
> > > Maybe we should come up with a better place to add this function.
> >
> > arch/riscv/cpu/cpu.c is a good candidate.
>
> Hi Leo,
>
> Thanks for reporting the result. Looks like the test doesn't use
> "CONFIG_SPL_BUILD"? Thanks to Sean's suggestion, I will move dummy
> riscv_hart_early_init() from ./arch/riscv/lib/spl.c to
> ./arch/riscv/cpu/cpu.c to create the next patch.
>
> BTW, it's nice if you can share the .config file or CONFIG_* related
> to CPU? I'd like to check around whether there are other possibilities
> to break the code building? Thanks,
>
> -- Green
>
Hi Green,
Sorry for the late reply.
It seems that this v2 patch would fail to compile with but not limited to the following configs.
qemu-riscv[32|64]_defconfig, ae350_rv[32|64]_defconfig...
The v3 patch seems to fix the compile error, thanks!
Best regards,
Leo
>
> >
> > --Sean
> >
> > >
> > > Best regards,
> > > Leo
> > >
> > >> 2 files changed, 9 insertions(+)
> > >>
> > >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > >> index 8589509e01..5c7d4da9e2 100644
> > >> --- a/arch/riscv/cpu/start.S
> > >> +++ b/arch/riscv/cpu/start.S
> > >> @@ -117,6 +117,11 @@ call_board_init_f_0:
> > >> mv sp, a0
> > >> #endif
> > >>
> > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> > >> +call_riscv_hart_early_init:
> > >> + jal riscv_hart_early_init
> > >> +#endif
> > >> +
> > >> #ifndef CONFIG_XIP
> > >> /*
> > >> * Pick hart to initialize global data and run U-Boot. The other harts
> > >> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
> > >> index 8baee07bea..e5b1affbfc 100644
> > >> --- a/arch/riscv/lib/spl.c
> > >> +++ b/arch/riscv/lib/spl.c
> > >> @@ -14,6 +14,10 @@
> > >>
> > >> DECLARE_GLOBAL_DATA_PTR;
> > >>
> > >> +__weak void riscv_hart_early_init(void)
> > >> +{
> > >> +}
> > >> +
> > >> __weak int spl_board_init_f(void)
> > >> {
> > >> return 0;
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC PATCH v3 1/2] arch: riscv: cpu: Add callback to init each core
2021-03-29 2:23 ` [RFC PATCH v3 " Leo Liang
@ 2021-03-29 2:32 ` Green Wan
0 siblings, 0 replies; 9+ messages in thread
From: Green Wan @ 2021-03-29 2:32 UTC (permalink / raw)
To: u-boot
Oaky, thanks for sharing the defconfig info.
-
Green
Leo Liang <ycliang@andestech.com>? 2021?3?29? ?????10:24???
> On Fri, Mar 26, 2021 at 05:03:54PM +0800, Green Wan wrote:
> > On Fri, Mar 26, 2021 at 9:34 AM Sean Anderson <seanga2@gmail.com> wrote:
> > >
> > > On 3/25/21 9:22 PM, Leo Liang wrote:
> > > > Hi Green,
> > > >
> > > > On Tue, Mar 23, 2021 at 01:35:38AM -0700, Green Wan wrote:
> > > >> Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S
> to
> > > >> allow different riscv hart perform setup code for each hart as early
> > > >> as possible. Since all the harts enter the calback, they must be
> able
> > > >> to run the same setup.
> > > >>
> > > >> Signed-off-by: Green Wan <green.wan@sifive.com>
> > > >> ---
> > > >> arch/riscv/cpu/start.S | 5 +++++
> > > >> arch/riscv/lib/spl.c | 4 ++++
> > > >
> > > > This patch fails to compile for some defconfigs.
> > > > (CI result:
> https://dev.azure.com/ycliang-tw/u-boot-riscv/_build/results?buildId=15&view=results
> )
> > > >
> > > > Maybe we should come up with a better place to add this function.
> > >
> > > arch/riscv/cpu/cpu.c is a good candidate.
> >
> > Hi Leo,
> >
> > Thanks for reporting the result. Looks like the test doesn't use
> > "CONFIG_SPL_BUILD"? Thanks to Sean's suggestion, I will move dummy
> > riscv_hart_early_init() from ./arch/riscv/lib/spl.c to
> > ./arch/riscv/cpu/cpu.c to create the next patch.
> >
> > BTW, it's nice if you can share the .config file or CONFIG_* related
> > to CPU? I'd like to check around whether there are other possibilities
> > to break the code building? Thanks,
> >
> > -- Green
> >
> Hi Green,
>
> Sorry for the late reply.
> It seems that this v2 patch would fail to compile with but not limited to
> the following configs.
> qemu-riscv[32|64]_defconfig, ae350_rv[32|64]_defconfig...
>
> The v3 patch seems to fix the compile error, thanks!
>
> Best regards,
> Leo
> >
> > >
> > > --Sean
> > >
> > > >
> > > > Best regards,
> > > > Leo
> > > >
> > > >> 2 files changed, 9 insertions(+)
> > > >>
> > > >> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > > >> index 8589509e01..5c7d4da9e2 100644
> > > >> --- a/arch/riscv/cpu/start.S
> > > >> +++ b/arch/riscv/cpu/start.S
> > > >> @@ -117,6 +117,11 @@ call_board_init_f_0:
> > > >> mv sp, a0
> > > >> #endif
> > > >>
> > > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE)
> > > >> +call_riscv_hart_early_init:
> > > >> + jal riscv_hart_early_init
> > > >> +#endif
> > > >> +
> > > >> #ifndef CONFIG_XIP
> > > >> /*
> > > >> * Pick hart to initialize global data and run U-Boot. The
> other harts
> > > >> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
> > > >> index 8baee07bea..e5b1affbfc 100644
> > > >> --- a/arch/riscv/lib/spl.c
> > > >> +++ b/arch/riscv/lib/spl.c
> > > >> @@ -14,6 +14,10 @@
> > > >>
> > > >> DECLARE_GLOBAL_DATA_PTR;
> > > >>
> > > >> +__weak void riscv_hart_early_init(void)
> > > >> +{
> > > >> +}
> > > >> +
> > > >> __weak int spl_board_init_f(void)
> > > >> {
> > > >> return 0;
> > >
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-03-29 2:32 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-23 8:35 [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core Green Wan
2021-03-23 8:35 ` [RFC PATCH v2 2/2] board: sifive: unmatched: clear feature disable CSR Green Wan
2021-03-24 0:32 ` Sean Anderson
2021-03-24 0:27 ` [RFC PATCH v2 1/2] arch: riscv: cpu: Add callback to init each core Sean Anderson
2021-03-26 1:22 ` Leo Liang
2021-03-26 1:34 ` Sean Anderson
2021-03-26 9:03 ` Green Wan
2021-03-29 2:23 ` [RFC PATCH v3 " Leo Liang
2021-03-29 2:32 ` Green Wan
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