[igt-dev] [PATCH i-g-t v2 00/15] Introduce PXP Test

[igt-dev] [PATCH i-g-t v2 00/15] Introduce PXP Test

[Alan Previn]

This series adds i915_pxp tests for the new PXP subsystem currently
being reviewed at https://patchwork.freedesktop.org/series/86798/ .
This series currently includes 4 groups of tests addressing the
features and restrictions described by Daniele's series :
   1. test i915 interfaces for allocation of protected bo's
      and contexts and enforcement of UAPI rule disallowing the
      modification of parameters after it's been created.
   2. verify PXP subsystem protected sessions generate encrypted
      content on protected output buffers and decrypt protected
      inputs buffers.
   3. verify i915 PXP auto-teardown succeeds on suspend-resume
      cycles and gem-exec of stale protected assets fail. Ensure
      protected-contexts adhere to stricter invalidation
      enforcement upon teardown event.
   4. Ensure that display plane decryption works as expected with
      protected buffers with and without HDCP.

Changes from prior rev1 to now:
   v2: 
      - Addressed all rev1 review comments except these:
           1.Chris Wilson : "...have the caller do 1-3 once for its protected
             context. Call it something like intel_bb_enable_pxp(),
             intel_bb_set_pxp if it should be reversible.".
             -  This couldn't be implemented because [1] HW needs different
             instruction sequences for enabling/disabling PXP depending
             on the engine class and [2] the pair of "pxp-enable" and "pxp-
             disable" instructions need to be contained within the same batch
             that is dispatched to the hardware. That said, implementing
             internal intel_batchbuffer funtionality for this would conflict
             with how rendercopy_gen9 uses batch buffer memory by repositioing
             the pointer and consuming unused portions of the batch buffer as
             3d state offsets that batchbuffer has no visibility.
         
      - Added these additional subtests:
           1. verify that buffer sharing works across testing pxp context.
           2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
           3. verify display plane decryption of protected buffers.

Alan Previn (14):
  Sync i915_drm.h UAPI for PXP
  Add basic PXP testing of buffer and context alloc
  Perform a regular 3d copy as a control checkpoint
  Add PXP attribute support in batchbuffer and buffer_ops libs
  Add MI_SET_APPID instruction definition
  Enable protected session cmd in gen12_render_copyfunc
  Add subtest to copy raw source to protected dest
  Add test where both src and dest are protected
  Verify PXP teardown occured through suspend-resume
  Verify execbuf fails with stale PXP context after teardown
  Verify execbuf fails with stale PXP buffer after teardown
  Verify execbuf ok with stale prot-buff and regular context
  Ensure RESET_STAT reports invalidated protected context
  Verify protected surfaces are dma buffer sharable

Karthik B S (1):
  tests/i915_pxp: CRC validation for display tests.

 include/drm-uapi/i915_drm.h |   94 ++-
 lib/intel_batchbuffer.c     |   23 +-
 lib/intel_batchbuffer.h     |   30 +
 lib/intel_bufops.h          |   15 +
 lib/intel_reg.h             |    9 +
 lib/rendercopy_gen9.c       |   73 +-
 tests/Makefile.sources      |    3 +
 tests/i915/gem_pxp.c        | 1420 +++++++++++++++++++++++++++++++++++
 tests/meson.build           |    1 +
 9 files changed, 1659 insertions(+), 9 deletions(-)
 create mode 100644 tests/i915/gem_pxp.c

-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 01/15] Sync i915_drm.h UAPI for PXP

[Alan Previn]

Sync i915_drm.h UAPI for PXP

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 include/drm-uapi/i915_drm.h | 94 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 93 insertions(+), 1 deletion(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index bf9ea471..c6dd8b58 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 #define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 #define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
 #define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 #define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
 	__u32 pad;
 };
 
+struct drm_i915_gem_create_ext {
+	/**
+	 * Requested size for the object.
+	 *
+	 * The (page-aligned) allocated size for the object will be returned.
+	 */
+	__u64 size;
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+	__u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+	(-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+	__u64 extensions;
+
+};
+
 struct drm_i915_gem_pread {
 	/** Handle for the object being read. */
 	__u32 handle;
@@ -1694,11 +1716,76 @@ struct drm_i915_gem_context_param {
  * Default is 16 KiB.
  */
 #define I915_CONTEXT_PARAM_RINGSIZE	0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * Enable usage of protected content with the context. This flag can only be
+ * set at context creation time and, when set to true, must be preceded by
+ * an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE to false. This flag
+ * can't be set to true in conjunction with setting the
+ * I915_CONTEXT_PARAM_BANNABLE flag to false.
+ *
+ * Given the numerous restriction on this flag, there are several unique
+ * failure cases:
+ *
+ * -ENODEV: feature not available
+ * -EEXIST: trying to modify an existing context
+ * -EPERM: trying to mark a recoverable or not bannable context as protected
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
 /* Must be kept compact -- no holes and well documented */
 
 	__u64 value;
 };
 
+struct drm_i915_gem_object_param {
+	/* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+	__u32 handle;
+
+	/* Data pointer size */
+	__u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM  (1ull << 32)
+
+/*
+ * I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true, buffer contents is expected to be protected by PXP
+ * encryption and requires decryption for scan out and processing. This is
+ * only possible on platforms that have PXP enabled, on all other scenarios
+ * setting this flag will cause the ioctl to fail and return -ENODEV.
+ *
+ * Protected buffers can only be used with contexts created using the
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. The buffer contents are
+ * considered invalid after a PXP session teardown.
+ *
+ * Given the restriction above, the following errors are possible when
+ * submitting a protected object in an execbuf call:
+ *
+ * -ENODEV: PXP session not currently active
+ * -EIO: buffer has become invalid after a teardown event
+ * -EPERM: buffer submitted using a context not marked as protected
+ */
+#define I915_OBJECT_PARAM_PROTECTED_CONTENT  0x0
+/* Must be kept compact -- no holes and well documented */
+
+	__u64 param;
+
+	/* Data value or pointer */
+	__u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+	struct i915_user_extension base;
+	struct drm_i915_gem_object_param param;
+};
+
 /**
  * Context SSEU programming
  *
@@ -1924,6 +2011,7 @@ struct drm_i915_reg_read {
 struct drm_i915_reset_stats {
 	__u32 ctx_id;
 	__u32 flags;
+#define I915_CONTEXT_INVALIDATED 0x1
 
 	/* All resets since boot/module reload, for all contexts */
 	__u32 reset_count;
@@ -2093,7 +2181,7 @@ struct drm_i915_perf_open_param {
  * Change metrics_set captured by a stream.
  *
  * If the stream is bound to a specific context, the configuration change
- * will performed __inline__ with that context such that it takes effect before
+ * will performed inline with that context such that it takes effect before
  * the next execbuf submission.
  *
  * Returns the previously bound metrics set id, or a negative error code.
@@ -2376,6 +2464,10 @@ struct drm_i915_query_perf_config {
 	__u8 data[];
 };
 
+
+/* ID of the protected content session managed by i915 when PXP is active */
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 02/15] Add basic PXP testing of buffer and context alloc

[Alan Previn]

Test PXP capability support as well as the allocation of protected
buffers and protected contexts.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/Makefile.sources |   3 +
 tests/i915/gem_pxp.c   | 410 +++++++++++++++++++++++++++++++++++++++++
 tests/meson.build      |   1 +
 3 files changed, 414 insertions(+)
 create mode 100644 tests/i915/gem_pxp.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 4f24fb3a..05952066 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -370,6 +370,9 @@ gem_pwrite_SOURCES = i915/gem_pwrite.c
 TESTS_progs += gem_pwrite_snooped
 gem_pwrite_snooped_SOURCES = i915/gem_pwrite_snooped.c
 
+TESTS_progs += gem_pxp
+gem_pxp_SOURCES = i915/gem_pxp.c
+
 TESTS_progs += gem_read_read_speed
 gem_read_read_speed_SOURCES = i915/gem_read_read_speed.c
 
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
new file mode 100644
index 00000000..40a817b2
--- /dev/null
+++ b/tests/i915/gem_pxp.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <sys/ioctl.h>
+
+#include "igt.h"
+#include "i915/gem.h"
+
+IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
+			"that allows the handling of protected content through "
+			"the arbitration of hardware protected sessions.");
+
+/* test-configs for protected buffer creation*/
+#define BO_ALLOC_NO_HW_SUPPORT 1
+#define BO_ALLOC_PROTECT_ON 2
+#define BO_ALLOC_PROTECT_OFF 3
+
+/* test-configs for protected context creation*/
+#define CTX_ALLOC_NO_HW_SUPPORT 1
+#define CTX_ALLOC_RECOVER_OFF_PROTECT_OFF 2
+#define CTX_ALLOC_RECOVER_OFF_PROTECT_ON 3
+#define CTX_ALLOC_RECOVER_ON_PROTECT_OFF 4
+#define CTX_ALLOC_RECOVER_ON_PROTECT_ON 5
+#define CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON 6
+#define CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF 7
+#define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
+#define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
+
+static bool is_pxp_hw_supported(int i915)
+{
+	uint32_t gen;
+
+	gen = intel_gen(intel_get_drm_devid(i915));
+	if (!gen) {
+		igt_info("No device info found - assume no PXP support.\n");
+		return false;
+	}
+
+	if (gen >= 12)
+		return true;
+
+	return false;
+}
+
+static uint32_t create_protected_bo(int i915, uint32_t size,
+				    bool with_protected_param,
+				    bool protected_is_true, int expected_return)
+{
+	int ret;
+
+	struct drm_i915_gem_object_param protected_param = {
+		.param = I915_OBJECT_PARAM | I915_OBJECT_PARAM_PROTECTED_CONTENT,
+		.data = 0,
+	};
+
+	struct drm_i915_gem_create_ext_setparam setparam_protected = {
+		.base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
+		.param = protected_param,
+	};
+
+	struct drm_i915_gem_create_ext create_ext = {
+		.size = size,
+		.extensions = (uintptr_t)&setparam_protected,
+	};
+
+	if (!with_protected_param) {
+		create_ext.extensions = 0;
+	} else {
+		if (protected_is_true) {
+			protected_param.data = 1;
+			setparam_protected.param = protected_param;
+		} else {
+			protected_param.data = 0;
+			setparam_protected.param = protected_param;
+		}
+	}
+
+	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+	igt_assert_eq(ret, expected_return);
+
+	return create_ext.handle;
+}
+
+static void test_create_protected_buffer(int i915, uint32_t test_cfg)
+{
+	uint32_t bo;
+
+	switch (test_cfg) {
+	case BO_ALLOC_NO_HW_SUPPORT:
+		bo = create_protected_bo(i915, 4096, false, false, 0);
+		gem_close(i915, bo);
+		bo = create_protected_bo(i915, 4096, true, true, -ENODEV);
+		igt_assert_eq(bo, 0);
+		break;
+
+	case BO_ALLOC_PROTECT_OFF:
+		bo = create_protected_bo(i915, 4096, false, false, 0);
+		gem_close(i915, bo);
+		break;
+
+	case BO_ALLOC_PROTECT_ON:
+		bo = create_protected_bo(i915, 4096, true, true, 0);
+		gem_close(i915, bo);
+		break;
+
+	default:
+		igt_info("Skipping unknown buffer test_cfg = %d\n", test_cfg);
+		break;
+	}
+}
+
+static int create_ext_ioctl(int i915,
+			    struct drm_i915_gem_context_create_ext *arg)
+{
+	int err;
+
+	err = 0;
+	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
+		err = -errno;
+		igt_assume(err);
+	}
+
+	errno = 0;
+	return err;
+}
+
+static uint32_t create_protected_ctx(int i915, bool with_protected_param,
+				     bool protected_is_true,
+				     bool with_recoverable_param,
+				     bool recoverable_is_true,
+				     int expected_return)
+{
+	int ret;
+
+	struct drm_i915_gem_context_create_ext_setparam p_prot = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			.next_extension = 0,
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+			.value = 0,
+		}
+	};
+	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			.next_extension = 0,
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_RECOVERABLE,
+			.value = 0,
+		}
+	};
+	struct drm_i915_gem_context_create_ext create = {
+		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+		.extensions = 0,
+	};
+
+	p_prot.param.value = protected_is_true;
+	p_norecover.param.value = recoverable_is_true;
+
+	if (with_protected_param && with_recoverable_param) {
+		create.extensions = to_user_pointer(&(p_norecover.base));
+		p_norecover.base.next_extension =
+			to_user_pointer(&(p_prot.base));
+	} else if (!with_protected_param && with_recoverable_param) {
+		create.extensions = to_user_pointer(&(p_norecover.base));
+		p_norecover.base.next_extension = 0;
+	} else if (with_protected_param && !with_recoverable_param) {
+		create.extensions = to_user_pointer(&(p_prot.base));
+		p_prot.base.next_extension = 0;
+	} else if (!with_protected_param && !with_recoverable_param) {
+		create.flags = 0;
+	}
+
+	ret = create_ext_ioctl(i915, &create);
+	igt_assert_eq(ret, expected_return);
+
+	return create.ctx_id;
+}
+
+#define CHANGE_PARAM_PROTECTED 0x0001
+#define CHANGE_PARAM_RECOVERY 0x0002
+static void modify_ctx_protected_param(int i915, uint32_t ctx_id,
+				       uint32_t change_param_mask,
+				       bool param_value, int expected_return)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = 0,
+		.value = 0,
+	};
+
+	if (change_param_mask == CHANGE_PARAM_PROTECTED) {
+		ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
+		ctx_param.value = (int)param_value;
+	} else if (change_param_mask == CHANGE_PARAM_RECOVERY) {
+		ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
+		ctx_param.value = (int)param_value;
+	} else {
+		return;
+	}
+
+	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &ctx_param);
+
+	igt_assert_eq(ret, expected_return);
+}
+
+static void assert_ctx_protected_param(int i915, uint32_t ctx_id,
+				       bool is_protected)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+	};
+
+	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(ctx_param.value, (int)is_protected);
+}
+
+static void assert_ctx_recovery_param(int i915, uint32_t ctx_id,
+				      bool is_recoverable)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = I915_CONTEXT_PARAM_RECOVERABLE,
+	};
+
+	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(ctx_param.value, (int)is_recoverable);
+}
+
+static void test_create_protected_context(int i915, uint32_t test_cfg)
+{
+	uint32_t ctx;
+
+	switch (test_cfg) {
+	case CTX_ALLOC_NO_HW_SUPPORT:
+		ctx = create_protected_ctx(i915, true, true, true, false,
+					   -ENODEV);
+		igt_assert_eq(ctx, 0);
+	case CTX_ALLOC_RECOVER_OFF_PROTECT_OFF:
+		ctx = create_protected_ctx(i915, true, false, true, false, 0);
+		assert_ctx_protected_param(i915, ctx, false);
+		assert_ctx_recovery_param(i915, ctx, false);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	case CTX_ALLOC_RECOVER_OFF_PROTECT_ON:
+		ctx = create_protected_ctx(i915, true, true, true, false, 0);
+		assert_ctx_protected_param(i915, ctx, true);
+		assert_ctx_recovery_param(i915, ctx, false);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	case CTX_ALLOC_RECOVER_ON_PROTECT_OFF:
+		ctx = create_protected_ctx(i915, true, false, true, true, 0);
+		assert_ctx_protected_param(i915, ctx, false);
+		assert_ctx_recovery_param(i915, ctx, true);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	case CTX_ALLOC_RECOVER_ON_PROTECT_ON:
+		ctx = create_protected_ctx(i915, true, true, true, true,
+					   -EPERM);
+		igt_assert_eq(ctx, 0);
+		ctx = create_protected_ctx(i915, true, true, false, false,
+					   -EPERM);
+		igt_assert_eq(ctx, 0);
+		break;
+
+	case CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON:
+		ctx = create_protected_ctx(i915, true, true, true, false, 0);
+		assert_ctx_protected_param(i915, ctx, true);
+		assert_ctx_recovery_param(i915, ctx, false);
+		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
+					   true, -EPERM);
+		assert_ctx_recovery_param(i915, ctx, false);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	case CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF:
+		ctx = create_protected_ctx(i915, true, true, true, false, 0);
+		assert_ctx_protected_param(i915, ctx, true);
+		assert_ctx_recovery_param(i915, ctx, false);
+		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
+					   false, -EPERM);
+		assert_ctx_protected_param(i915, ctx, true);
+		assert_ctx_recovery_param(i915, ctx, false);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	case CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID:
+		ctx = create_protected_ctx(i915, true, true, true, false, 0);
+		assert_ctx_protected_param(i915, ctx, true);
+		assert_ctx_recovery_param(i915, ctx, false);
+		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
+					   true, -EPERM);
+		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
+					   false, -EPERM);
+		assert_ctx_protected_param(i915, ctx, true);
+		assert_ctx_recovery_param(i915, ctx, false);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	case CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID:
+		ctx = create_protected_ctx(i915, false, false, false, false, 0);
+		assert_ctx_protected_param(i915, ctx, false);
+		assert_ctx_recovery_param(i915, ctx, true);
+		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
+					   false, 0);
+		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
+					   true, -EPERM);
+		assert_ctx_protected_param(i915, ctx, false);
+		assert_ctx_recovery_param(i915, ctx, false);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	default:
+		igt_info("Skipping unknown context test_cfg = %d\n", test_cfg);
+		break;
+	}
+}
+
+igt_main
+{
+	int i915 = -1;
+	bool pxp_supported = false;
+
+	igt_fixture
+	{
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require(i915);
+		igt_require_gem(i915);
+		pxp_supported = is_pxp_hw_supported(i915);
+	}
+
+	igt_subtest_group {
+		igt_fixture {
+			igt_require((pxp_supported == 0));
+		}
+
+		igt_describe("Verify protected buffer on unsupported hw:");
+		igt_subtest("hw-rejects-pxp-buffer")
+			test_create_protected_buffer(i915,
+				BO_ALLOC_NO_HW_SUPPORT);
+		igt_describe("Verify protected context on unsupported hw:");
+		igt_subtest("hw-rejects-pxp-context")
+			test_create_protected_context(i915,
+				CTX_ALLOC_NO_HW_SUPPORT);
+	}
+
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+		}
+
+		igt_describe("Verify protected buffer on supported hw:");
+		igt_subtest("create-regular-buffer")
+			test_create_protected_buffer(i915,
+				BO_ALLOC_PROTECT_OFF);
+		igt_subtest("create-protected-buffer")
+			test_create_protected_buffer(i915, BO_ALLOC_PROTECT_ON);
+
+		igt_describe("Verify protected context on supported hw:");
+		igt_subtest("create-regular-context-1")
+			test_create_protected_context(
+				i915, CTX_ALLOC_RECOVER_OFF_PROTECT_OFF);
+		igt_subtest("create-regular-context-2")
+			test_create_protected_context(
+				i915, CTX_ALLOC_RECOVER_ON_PROTECT_OFF);
+		igt_subtest("fail-invalid-protected-context")
+			test_create_protected_context(
+				i915, CTX_ALLOC_RECOVER_ON_PROTECT_ON);
+		igt_subtest("create-valid-protected-context")
+			test_create_protected_context(
+				i915, CTX_ALLOC_RECOVER_OFF_PROTECT_ON);
+
+		igt_describe("Verify protected context integrity:");
+		igt_subtest("reject-modify-context-protection-on")
+			test_create_protected_context(
+				i915,
+				CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID);
+		igt_subtest("reject-modify-context-protection-off-1")
+			test_create_protected_context(
+				i915, CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON);
+		igt_subtest("reject-modify-context-protection-off-2")
+			test_create_protected_context(
+				i915, CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF);
+		igt_subtest("reject-modify-context-protection-off-3")
+			test_create_protected_context(
+				i915,
+				CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID);
+	}
+
+	igt_fixture {
+		close(i915);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 825e0183..e7144039 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -189,6 +189,7 @@ i915_progs = [
 	'gem_pread_after_blit',
 	'gem_pwrite',
 	'gem_pwrite_snooped',
+	'gem_pxp',
 	'gem_read_read_speed',
 	'gem_readwrite',
 	'gem_reg_read',
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 03/15] Perform a regular 3d copy as a control checkpoint

[Alan Previn]

As a control checkpoint, allocate buffers to be used
as texture and render target in the 3d engine for a
regular src to dest copy blit and verify buffer pixels.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 173 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 173 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 40a817b2..7071cd0e 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -28,6 +28,11 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 #define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
 #define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
 
+/* test-configs for protected rendering operations */
+#define COPY3D_BASELINE_SRC_TO_DST 1
+#define COPY3D_PROTECTED_SRC_TO_PROTDST 2
+#define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
+
 static bool is_pxp_hw_supported(int i915)
 {
 	uint32_t gen;
@@ -333,10 +338,164 @@ static void test_create_protected_context(int i915, uint32_t test_cfg)
 	}
 }
 
+static void fill_bo_content(int i915, uint32_t bo,
+	uint32_t size, uint32_t initcolor)
+{
+	uint32_t *ptr, *ptrtmp;
+	int loop = 0;
+
+	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_WRITE);
+	ptrtmp = ptr;
+
+	/* read and count all dword matches till size */
+	while (loop++ < (size/4)) {
+		*ptrtmp = initcolor;
+		++ptrtmp;
+	}
+
+	igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+#define COMPARE_COLOR_READIBLE     1
+#define COMPARE_COLOR_UNREADIBLE   2
+#define COMPARE_N_PIXELS_VERBOSELY 0
+static void assert_bo_content_check(int i915, uint32_t bo,
+	int compare_op, uint32_t size, uint32_t color)
+{
+	uint32_t *ptr, *ptrtmp;
+	int loop = 0, num_matches = 0;
+	uint32_t value;
+	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+
+	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
+	ptrtmp = ptr;
+
+	if (COMPARE_N_PIXELS_VERBOSELY) {
+		igt_info("--------->>>\n");
+		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
+			value = *ptrtmp;
+			igt_info("Color read = 0x%08x ", value);
+			igt_info("expected %c= 0x%08x)\n",
+				op_readible?'=':'!', color);
+			++ptrtmp;
+			++loop;
+		}
+		igt_info("<<<---------\n");
+		ptrtmp = ptr;
+		loop = 0;
+	}
+
+	/*count all pixels for matches */
+	while (loop++ < (size/4)) {
+		value = *ptrtmp;
+		if (value == color)
+			++num_matches;
+		++ptrtmp;
+	}
+
+	if (op_readible)
+		igt_assert_eq(num_matches, (size/4));
+	else
+		igt_assert_eq(num_matches, 0);
+
+	igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
+	uint32_t size, uint32_t init_color)
+{
+	uint32_t bo;
+
+	bo = create_protected_bo(i915, size,
+		protected, protected, 0);
+	igt_assert(bo);
+	fill_bo_content(i915, bo, size, init_color);
+	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
+		size, init_color);
+
+	return bo;
+}
+
+/* Rendering tests surface attributes, keep it simple:
+ * page aligned width==stride, thus, and size
+ */
+#define TSTSURF_WIDTH       1024
+#define TSTSURF_HEIGHT      128
+#define TSTSURF_BYTESPP     4
+#define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
+#define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
+#define TSTSURF_FILLCOLOR1  0xfaceface
+#define TSTSURF_INITCOLOR1  0x12341234
+
+static void test_render_protected_buffer(int i915, uint32_t test_cfg)
+{
+	uint32_t ctx, srcbo, dstbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	switch (test_cfg) {
+	case COPY3D_BASELINE_SRC_TO_DST:
+		/* Perform a regular 3d copy as a control checkpoint */
+		ctx = create_protected_ctx(i915, false, false,
+			false, false, 0);
+		assert_ctx_protected_param(i915, ctx, false);
+
+		dstbo = alloc_and_fill_dest_buff(i915, false,
+				TSTSURF_SIZE, TSTSURF_INITCOLOR1);
+		dstbuf = intel_buf_create_using_handle(bops, dstbo,
+				TSTSURF_WIDTH, TSTSURF_HEIGHT,
+				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+		srcbo = alloc_and_fill_dest_buff(i915, false,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+		srcbuf = intel_buf_create_using_handle(bops, srcbo,
+				TSTSURF_WIDTH, TSTSURF_HEIGHT,
+				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+		ibb = intel_bb_create_with_context(i915, ctx, 4096);
+		igt_assert(ibb);
+
+		gen12_render_copyfunc(ibb,
+			srcbuf, 0, 0,
+			TSTSURF_WIDTH, TSTSURF_HEIGHT,
+			dstbuf, 0, 0);
+		gem_sync(i915, dstbo);
+
+		assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
+			TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+
+		intel_bb_destroy(ibb);
+		intel_buf_destroy(srcbuf);
+		gem_close(i915, srcbo);
+		intel_buf_destroy(dstbuf);
+		gem_close(i915, dstbo);
+		gem_context_destroy(i915, ctx);
+		break;
+
+	default:
+		igt_info("Skipping unknown render test_cfg = %d\n",
+			test_cfg);
+		break;
+	}
+
+	buf_ops_destroy(bops);
+}
+
+
 igt_main
 {
 	int i915 = -1;
 	bool pxp_supported = false;
+	igt_render_copyfunc_t rendercopy = NULL;
+	uint32_t devid = 0;
 
 	igt_fixture
 	{
@@ -403,6 +562,20 @@ igt_main
 				i915,
 				CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+		}
+
+		igt_describe("Verify protected render operations:");
+		igt_subtest("regular-baseline-src-copy-readible")
+			test_render_protected_buffer(i915,
+				COPY3D_BASELINE_SRC_TO_DST);
+	}
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 04/15] Add PXP attribute support in batchbuffer and buffer_ops libs

[Alan Previn]

Eventually when we get to testing PXP rendering capability,
we shall reuse lib's rendercopy feature. Rendercopy libraries
shall retrieve information about PXP-session-enablement and
which buffers are protected from these new flags.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/intel_batchbuffer.c | 21 +++++++++++++++++++++
 lib/intel_batchbuffer.h | 28 ++++++++++++++++++++++++++++
 lib/intel_bufops.h      | 15 +++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 8118dc94..be9fc2ad 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1980,6 +1980,27 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 				  delta, offset, presumed_offset);
 }
 
+/*
+ * @intel_bb_set_pxp:
+ * @ibb: pointer to intel_bb
+ * @new_state: enable or disable pxp session
+ * @apptype: pxp session input identifies what type of session to enable
+ * @appid: pxp session input provides which appid to use
+ *
+ * This function merely stores the pxp state and session information to
+ * be retrieved and programmed later by supporting libraries such as
+ * gen12_render_copy that must program the HW within the same dispatch
+ */
+void intel_bb_set_pxp(struct intel_bb *ibb,
+			bool new_state, uint32_t apptype, uint32_t appid)
+{
+	igt_assert(ibb);
+
+	ibb->pxp.enabled = new_state;
+	ibb->pxp.apptype = new_state ? apptype : 0;
+	ibb->pxp.appid   = new_state ? appid : 0;
+}
+
 static void intel_bb_dump_execbuf(struct intel_bb *ibb,
 				  struct drm_i915_gem_execbuffer2 *execbuf)
 {
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 76989eaa..66af6e09 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -437,6 +437,12 @@ typedef void (*igt_media_spinfunc_t)(int i915,
 igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
 
 
+struct igt_pxp {
+	bool     enabled;
+	uint32_t apptype;
+	uint32_t appid;
+};
+
 /*
  * Batchbuffer without libdrm dependency
  */
@@ -459,6 +465,7 @@ struct intel_bb {
 	bool supports_48b_address;
 
 	uint32_t ctx;
+	struct igt_pxp pxp;
 
 	/* Cache */
 	void *root;
@@ -573,6 +580,27 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
 	igt_assert(intel_bb_offset(ibb) <= ibb->size);
 }
 
+void intel_bb_set_pxp(struct intel_bb *ibb,
+		bool new_state, uint32_t apptype, uint32_t appid);
+
+static inline bool intel_bb_pxp_enabled(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.enabled;
+}
+
+static inline uint32_t intel_bb_pxp_apptype(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.apptype;
+}
+
+static inline uint32_t intel_bb_pxp_appid(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.appid;
+}
+
 struct drm_i915_gem_exec_object2 *
 intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint32_t size,
 		    uint64_t offset, bool write);
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 8debe7f2..2c3a9a58 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -41,6 +41,9 @@ struct intel_buf {
 	uint32_t *ptr;
 	bool cpu_write;
 
+	/* Content Protection*/
+	bool is_protected;
+
 	/* For debugging purposes */
 	char name[INTEL_BUF_NAME_MAXSIZE + 1];
 };
@@ -138,6 +141,18 @@ struct intel_buf *intel_buf_create_using_handle(struct buf_ops *bops,
 
 void intel_buf_destroy(struct intel_buf *buf);
 
+static inline void intel_buf_set_pxp(struct intel_buf *buf, bool new_pxp_state)
+{
+	igt_assert(buf);
+	buf->is_protected = new_pxp_state;
+}
+
+static inline bool intel_buf_pxp(const struct intel_buf *buf)
+{
+	igt_assert(buf);
+	return buf->is_protected;
+}
+
 void *intel_buf_cpu_map(struct intel_buf *buf, bool write);
 void *intel_buf_device_map(struct intel_buf *buf, bool write);
 void intel_buf_unmap(struct intel_buf *buf);
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 05/15] Add MI_SET_APPID instruction definition

[Alan Previn]

Add MI_SET_APPID instruction and param definitions

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/intel_reg.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ac1fc6cb..553f4839 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
 #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
 
+#define MI_SET_APPID                    (0x0e<<23)
+#define APPID_CTXSAVE_INHIBIT           (1<<8)
+#define APPID_CTXREST_INHIBIT           (1<<9)
+#define DISPLAY_APPTYPE                 (0)
+#define TRANSCODE_APPTYPE               (1)
+#define APPTYPE(n)                      ((n & 0x1)<<7)
+#define APPID(n)                        (n & 0x7f)
+
+
 /* Dword 0 */
 #define MI_VERTEX_BUFFER		(0x17<<23)
 #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 06/15] Enable protected session cmd in gen12_render_copyfunc

[Alan Previn]

1. In _gen9_render_op, check if the incoming batchbuffer
   is marked with pxp enabled. If so, insert MI_SET_APPID
   along with PIPE_CONTROL instructions at the start and
   end of the rendering operation in the command buffer.

2. The two PIPE_CONTROLs will enable protected memory
   at the start of the batch and disabling protected
   memory at the end of it. These PIPE_CONTROLs require a
   Post-Sync operation with a write to memory for hardware
   to accept.

3. In order to satisfy #2, _gen9_render_op uses unused
   regions of the ibb buffer for the PIPE_CONTROL PostSync
   write to memory (no different from how other 3d states
   are being referenced).

4. _gen9_render_op shall check the incoming surface
   buffers for "is_protected" flag and if its set, it
   will mark the SURFACE_STATE's MOCS field accordingly.

NOTE: _gen9_render_op needs to program the HW to enable
the PXP session as part of the rendering batch buffer
because the HW requires that enabling/disabling protected
memory access must be programmed in pairs within the same
"dispatch of rendering commands" to HW.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/rendercopy_gen9.c | 73 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 66 insertions(+), 7 deletions(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index eecf73d3..7255349f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -19,7 +19,8 @@
 #include "intel_bufops.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
-#include "rendercopy.h"
+#include "igt.h"
+#include "i915/gem.h"
 #include "gen9_render.h"
 #include "intel_reg.h"
 #include "igt_aux.h"
@@ -152,6 +153,8 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
 		ss->ss0.tiled_mode = 3;
 
 	ss->ss1.memory_object_control = I915_MOCS_PTE << 1;
+	if (intel_buf_pxp(buf))
+		ss->ss1.memory_object_control |= 1;
 
 	if (buf->tiling == I915_TILING_Yf)
 		ss->ss5.trmode = 1;
@@ -873,6 +876,54 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset)
 	intel_bb_out(ibb, 0);	/* index buffer offset, ignored */
 }
 
+#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL	            (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_START                     0x1234fed0
+#define PS_OP_TAG_END                       0x5678cbaf
+static void gen12_emit_pxp_state(struct intel_bb *ibb, bool enable,
+		 uint32_t pxp_write_op_offset)
+{
+	uint32_t pipe_ctl_flags;
+	uint32_t set_app_id, ps_op_id;
+
+	if (enable) {
+		pipe_ctl_flags = PIPE_CONTROL_FLUSH_ENABLE;
+		intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+		intel_bb_out(ibb, pipe_ctl_flags);
+
+		set_app_id =  MI_SET_APPID |
+				APPTYPE(intel_bb_pxp_apptype(ibb)) |
+				APPID(intel_bb_pxp_appid(ibb));
+		intel_bb_out(ibb, set_app_id);
+
+		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_ENABLE;
+		ps_op_id = PS_OP_TAG_START;
+	} else {
+		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_DISABLE;
+		ps_op_id = PS_OP_TAG_END;
+	}
+
+	pipe_ctl_flags |= (PIPE_CONTROL_CS_STALL |
+				PIPE_CONTROL_RENDER_TARGET_FLUSH |
+				PIPE_CONTROL_DATA_CACHE_INVALIDATE |
+				PIPE_CONTROL_POST_SYNC_OP);
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+	intel_bb_out(ibb, pipe_ctl_flags);
+	intel_bb_emit_reloc(ibb, ibb->handle,
+		0, I915_GEM_DOMAIN_COMMAND,
+		(enable ? pxp_write_op_offset : (pxp_write_op_offset+8)),
+		ibb->batch_offset);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, ps_op_id);
+}
+
 /* The general rule is if it's named gen6 it is directly copied from
  * gen6_render_copyfunc.
  *
@@ -922,6 +973,7 @@ void _gen9_render_op(struct intel_bb *ibb,
 	uint32_t vertex_buffer;
 	uint32_t aux_pgtable_state;
 	bool fast_clear = !src;
+	uint32_t pxp_scratch_offset;
 
 	if (!fast_clear)
 		igt_assert(src->bpp == dst->bpp);
@@ -950,8 +1002,12 @@ void _gen9_render_op(struct intel_bb *ibb,
 	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb, aux_pgtable_buf);
 
 	/* TODO: there is other state which isn't setup */
+	pxp_scratch_offset = intel_bb_offset(ibb);
 	intel_bb_ptr_set(ibb, 0);
 
+	if (intel_bb_pxp_enabled(ibb))
+		gen12_emit_pxp_state(ibb, true, pxp_scratch_offset);
+
 	/* Start emitting the commands. The order roughly follows the mesa blorp
 	 * order */
 	intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
@@ -963,13 +1019,12 @@ void _gen9_render_op(struct intel_bb *ibb,
 		for (int i = 0; i < 4; i++) {
 			intel_bb_out(ibb, MI_STORE_DWORD_IMM);
 			intel_bb_emit_reloc(ibb, dst->handle,
-					    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                                            dst->cc.offset + i*sizeof(float),
-					    dst->addr.offset);
+					I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+					dst->cc.offset + i*sizeof(float),
+					dst->addr.offset);
 			intel_bb_out(ibb, *(uint32_t*)&clear_color[i]);
-               }
-       }
-
+		}
+	}
 
 	gen8_emit_sip(ibb);
 
@@ -1023,10 +1078,14 @@ void _gen9_render_op(struct intel_bb *ibb,
 	gen8_emit_vf_topology(ibb);
 	gen8_emit_primitive(ibb, vertex_buffer);
 
+	if (intel_bb_pxp_enabled(ibb))
+		gen12_emit_pxp_state(ibb, false, pxp_scratch_offset);
+
 	intel_bb_emit_bbe(ibb);
 	intel_bb_exec(ibb, intel_bb_offset(ibb),
 		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
 	dump_batch(ibb);
+
 	intel_bb_reset(ibb, false);
 }
 
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 07/15] Add subtest to copy raw source to protected dest

[Alan Previn]

Add subtest to 3d-copy raw source buffer (with
known readible content) to a destination buffer
marked as protected with a protected session using
default session keys. The destination buffer is
verified to be different from the source (when
read via CPU) because its encrypted.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 47 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 7071cd0e..825edbf1 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -425,7 +425,9 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
 #define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
 #define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
 #define TSTSURF_FILLCOLOR1  0xfaceface
+#define TSTSURF_FILLCOLOR2  0xdeaddead
 #define TSTSURF_INITCOLOR1  0x12341234
+#define TSTSURF_INITCOLOR2  0x56785678
 
 static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 {
@@ -480,6 +482,48 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 		gem_context_destroy(i915, ctx);
 		break;
 
+	case COPY3D_PROTECTED_SRC_TO_PROTDST:
+		/* Perform a protected render operation but only label
+		 * the dest as protected. After rendering, the content
+		 * should be encrypted
+		 */
+		ctx = create_protected_ctx(i915, true, true,
+			true, false, 0);
+		assert_ctx_protected_param(i915, ctx, true);
+
+		dstbo = alloc_and_fill_dest_buff(i915, true,
+				TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+		dstbuf = intel_buf_create_using_handle(bops, dstbo,
+				TSTSURF_WIDTH, TSTSURF_HEIGHT,
+				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+		intel_buf_set_pxp(dstbuf, true);
+
+		srcbo = alloc_and_fill_dest_buff(i915, false,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+		srcbuf = intel_buf_create_using_handle(bops, srcbo,
+				TSTSURF_WIDTH, TSTSURF_HEIGHT,
+				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+		ibb = intel_bb_create_with_context(i915, ctx, 4096);
+		igt_assert(ibb);
+
+		intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE,
+			I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+		gen12_render_copyfunc(ibb, srcbuf, 0, 0,
+			TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+		gem_sync(i915, dstbo);
+
+		assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
+			TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+
+		intel_bb_destroy(ibb);
+		intel_buf_destroy(srcbuf);
+		gem_close(i915, srcbo);
+		intel_buf_destroy(dstbuf);
+		gem_close(i915, dstbo);
+		gem_context_destroy(i915, ctx);
+		break;
 	default:
 		igt_info("Skipping unknown render test_cfg = %d\n",
 			test_cfg);
@@ -575,6 +619,9 @@ igt_main
 		igt_subtest("regular-baseline-src-copy-readible")
 			test_render_protected_buffer(i915,
 				COPY3D_BASELINE_SRC_TO_DST);
+		igt_subtest("protected-raw-src-copy-not-readible")
+			test_render_protected_buffer(i915,
+				COPY3D_PROTECTED_SRC_TO_PROTDST);
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 08/15] Add test where both src and dest are protected

[Alan Previn]

When both the source and destination surfaces are
protected, the destination pixel result of the 3d
copy operation would be the same as the source. By
appending this test case to the end of the prior
test (raw-src to protected-dest) and reusing the
previous' test destination as the current source,
we can prove that new-source was decrypted properly
as we would see the difference in results: repeating
the same render operation but with a src buffer
that is protected in this case yields matching
(but still encrypted) output rendered pixels.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 117 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 104 insertions(+), 13 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 825edbf1..e5d8e1f7 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -358,29 +358,52 @@ static void fill_bo_content(int i915, uint32_t bo,
 
 #define COMPARE_COLOR_READIBLE     1
 #define COMPARE_COLOR_UNREADIBLE   2
+#define COMPARE_BUFFER_READIBLE    3
+#define COMPARE_BUFFER_UNREADIBLE  4
+#define COPY_BUFFER                5
+
 #define COMPARE_N_PIXELS_VERBOSELY 0
 static void assert_bo_content_check(int i915, uint32_t bo,
-	int compare_op, uint32_t size, uint32_t color)
+	int compare_op, uint32_t size, uint32_t color, uint32_t *auxptr, int auxsize)
 {
-	uint32_t *ptr, *ptrtmp;
+	uint32_t *ptr, *ptrtmp, *auxtmp;
 	int loop = 0, num_matches = 0;
 	uint32_t value;
-	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+	bool op_readible = ((compare_op == COMPARE_COLOR_READIBLE) ||
+		 (compare_op == COMPARE_BUFFER_READIBLE));
+	bool chk_buff = ((compare_op == COMPARE_BUFFER_READIBLE) ||
+		 (compare_op == COMPARE_BUFFER_UNREADIBLE));
+	bool copy_buff = (compare_op == COPY_BUFFER);
 
 	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
 	ptrtmp = ptr;
 
+	if (chk_buff || copy_buff) {
+		if (auxsize < size)
+			auxptr = NULL;
+		igt_assert(auxptr);
+		auxtmp = auxptr;
+	}
+
 	if (COMPARE_N_PIXELS_VERBOSELY) {
 		igt_info("--------->>>\n");
 		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
 			value = *ptrtmp;
-			igt_info("Color read = 0x%08x ", value);
-			igt_info("expected %c= 0x%08x)\n",
-				op_readible?'=':'!', color);
+			if (chk_buff)
+				color = *auxtmp;
+			if (copy_buff)
+				igt_info("Color copy = 0x%08x\n", value);
+			else {
+				igt_info("Color read = 0x%08x ", value);
+				igt_info("expected %c= 0x%08x)\n",
+					op_readible?'=':'!', color);
+			}
+			++auxtmp;
 			++ptrtmp;
 			++loop;
 		}
 		igt_info("<<<---------\n");
+		auxtmp = auxptr;
 		ptrtmp = ptr;
 		loop = 0;
 	}
@@ -388,8 +411,25 @@ static void assert_bo_content_check(int i915, uint32_t bo,
 	/*count all pixels for matches */
 	while (loop++ < (size/4)) {
 		value = *ptrtmp;
-		if (value == color)
-			++num_matches;
+		switch (compare_op) {
+		case COMPARE_COLOR_READIBLE:
+		case COMPARE_COLOR_UNREADIBLE:
+			if (value == color)
+				++num_matches;
+			break;
+		case COMPARE_BUFFER_READIBLE:
+		case COMPARE_BUFFER_UNREADIBLE:
+			if (value == (*auxtmp))
+				++num_matches;
+			++auxtmp;
+			break;
+		case COPY_BUFFER:
+			*auxtmp = value;
+			++auxtmp;
+			break;
+		default:
+			break;
+		}
 		++ptrtmp;
 	}
 
@@ -411,7 +451,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
 	igt_assert(bo);
 	fill_bo_content(i915, bo, size, init_color);
 	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
-		size, init_color);
+		size, init_color, NULL, 0);
 
 	return bo;
 }
@@ -428,14 +468,16 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
 #define TSTSURF_FILLCOLOR2  0xdeaddead
 #define TSTSURF_INITCOLOR1  0x12341234
 #define TSTSURF_INITCOLOR2  0x56785678
+#define TSTSURF_INITCOLOR3  0xabcdabcd
 
 static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 {
-	uint32_t ctx, srcbo, dstbo;
-	struct intel_buf *srcbuf, *dstbuf;
+	uint32_t ctx, srcbo, dstbo, dstbo2;
+	struct intel_buf *srcbuf, *dstbuf, *dstbuf2;
 	struct buf_ops *bops;
 	struct intel_bb *ibb;
 	uint32_t devid;
+	uint32_t encrypted[TSTSURF_SIZE/TSTSURF_BYTESPP];
 
 	devid = intel_get_drm_devid(i915);
 	igt_assert(devid);
@@ -472,7 +514,7 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 		gem_sync(i915, dstbo);
 
 		assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
-			TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+			TSTSURF_SIZE, TSTSURF_FILLCOLOR1, NULL, 0);
 
 		intel_bb_destroy(ibb);
 		intel_buf_destroy(srcbuf);
@@ -483,6 +525,7 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 		break;
 
 	case COPY3D_PROTECTED_SRC_TO_PROTDST:
+	case COPY3D_PROTECTED_PROTSRC_TO_PROTDST:
 		/* Perform a protected render operation but only label
 		 * the dest as protected. After rendering, the content
 		 * should be encrypted
@@ -515,15 +558,60 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 		gem_sync(i915, dstbo);
 
 		assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
-			TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+			TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
+
+		if (test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST) {
+			intel_bb_destroy(ibb);
+			intel_buf_destroy(srcbuf);
+			gem_close(i915, srcbo);
+			intel_buf_destroy(dstbuf);
+			gem_close(i915, dstbo);
+			gem_context_destroy(i915, ctx);
+			break;
+		}
+
+		/* For COPY3D_PROTECTED_PROTSRC_TO_PROTDST, reuse
+		 * prior dst as the new-src and create a new dst2 as
+		 * the new-dest. Take a copy of encrypted content
+		 * from new-src for comparison after render operation.
+		 * After the rendering, we should find no difference
+		 * in content since both new-src and new-dest are
+		 * labelled as encrypted. HW should read and decrypt
+		 * new-src, perform the render and re-encrypt when
+		 * going into new-dest
+		 */
+		assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+			TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
+
+		dstbo2 = alloc_and_fill_dest_buff(i915, false,
+				TSTSURF_SIZE, TSTSURF_INITCOLOR3);
+		dstbuf2 = intel_buf_create_using_handle(bops, dstbo2,
+				TSTSURF_WIDTH, TSTSURF_HEIGHT,
+				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+		intel_buf_set_pxp(dstbuf2, true);
+
+		intel_buf_set_pxp(dstbuf, true);/*this time, src is protected*/
+
+		intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE,
+			I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+		gen12_render_copyfunc(ibb, dstbuf, 0, 0,
+			TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf2, 0, 0);
+
+		gem_sync(i915, dstbo2);
+		assert_bo_content_check(i915, dstbo2, COMPARE_BUFFER_READIBLE,
+			TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
 
 		intel_bb_destroy(ibb);
 		intel_buf_destroy(srcbuf);
 		gem_close(i915, srcbo);
 		intel_buf_destroy(dstbuf);
 		gem_close(i915, dstbo);
+		intel_buf_destroy(dstbuf2);
+		gem_close(i915, dstbo2);
 		gem_context_destroy(i915, ctx);
 		break;
+
 	default:
 		igt_info("Skipping unknown render test_cfg = %d\n",
 			test_cfg);
@@ -622,6 +710,9 @@ igt_main
 		igt_subtest("protected-raw-src-copy-not-readible")
 			test_render_protected_buffer(i915,
 				COPY3D_PROTECTED_SRC_TO_PROTDST);
+		igt_subtest("protected-encrypted-src-copy-not-readible")
+			test_render_protected_buffer(i915,
+				COPY3D_PROTECTED_PROTSRC_TO_PROTDST);
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 09/15] Verify PXP teardown occured through suspend-resume

[Alan Previn]

During a suspend-resume cycle, the hardware and driver shall
ensure the PXP session and keys are torn down and re-
established. Verify that key change did occur by repeating
the 3d rendercopy operation before and after a suspend cycle
and ensuring that the encrypted output is different.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 100 +++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 97 insertions(+), 3 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index e5d8e1f7..06bfb6ca 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -6,6 +6,8 @@
 #include <sys/ioctl.h>
 
 #include "igt.h"
+#include "igt_device.h"
+#include "igt_sysfs.h"
 #include "i915/gem.h"
 
 IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
@@ -32,6 +34,16 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 #define COPY3D_BASELINE_SRC_TO_DST 1
 #define COPY3D_PROTECTED_SRC_TO_PROTDST 2
 #define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
+#define COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED 4
+
+/* test-configs for power-management triggered protected session teardown */
+#define SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE 1
+
+/* Struct and defintions for power management. */
+struct powermgt_data {
+	int debugfsdir;
+	bool has_runtime_pm;
+};
 
 static bool is_pxp_hw_supported(int i915)
 {
@@ -469,8 +481,8 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
 #define TSTSURF_INITCOLOR1  0x12341234
 #define TSTSURF_INITCOLOR2  0x56785678
 #define TSTSURF_INITCOLOR3  0xabcdabcd
-
-static void test_render_protected_buffer(int i915, uint32_t test_cfg)
+static void __test_render_protected_buffer(int i915, uint32_t test_cfg,
+	uint32_t *outpixels, int outsize)
 {
 	uint32_t ctx, srcbo, dstbo, dstbo2;
 	struct intel_buf *srcbuf, *dstbuf, *dstbuf2;
@@ -526,6 +538,7 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 
 	case COPY3D_PROTECTED_SRC_TO_PROTDST:
 	case COPY3D_PROTECTED_PROTSRC_TO_PROTDST:
+	case COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED:
 		/* Perform a protected render operation but only label
 		 * the dest as protected. After rendering, the content
 		 * should be encrypted
@@ -560,7 +573,12 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 		assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
 			TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
 
-		if (test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST) {
+		if (test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED)
+			assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+				TSTSURF_SIZE, 0, outpixels, outsize);
+
+		if ((test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST) ||
+			(test_cfg == COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED)) {
 			intel_bb_destroy(ibb);
 			intel_buf_destroy(srcbuf);
 			gem_close(i915, srcbo);
@@ -621,11 +639,71 @@ static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 	buf_ops_destroy(bops);
 }
 
+static void test_render_protected_buffer(int i915, uint32_t test_cfg)
+{
+	__test_render_protected_buffer(i915, test_cfg, NULL, 0);
+}
+
+static void init_powermgt_resources(int i915, struct powermgt_data *pm)
+{
+	pm->debugfsdir = igt_debugfs_dir(i915);
+	igt_require(pm->debugfsdir != -1);
+	pm->has_runtime_pm = igt_setup_runtime_pm(i915);
+	igt_require(pm->has_runtime_pm);
+
+}
+
+static void trigger_powermgt_suspend_cycle(int i915,
+	struct powermgt_data *pm)
+{
+	igt_pm_enable_sata_link_power_management();
+
+
+	igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_DEVICES);
+	igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
+}
+
+static void test_protected_session_teardown(int i915, uint32_t test_cfg,
+		struct powermgt_data *pm)
+{
+	uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
+	uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
+	int matched_after_keychange = 0, loop = 0;
+
+	switch (test_cfg) {
+	case SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE:
+		__test_render_protected_buffer(i915,
+			COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED,
+			encrypted_pixels_b4, TSTSURF_SIZE);
+
+		trigger_powermgt_suspend_cycle(i915, pm);
+
+		__test_render_protected_buffer(i915,
+			COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED,
+			encrypted_pixels_aft, TSTSURF_SIZE);
+
+		while (loop < (TSTSURF_SIZE/TSTSURF_BYTESPP)) {
+			if (encrypted_pixels_b4[loop] ==
+				encrypted_pixels_aft[loop])
+				++matched_after_keychange;
+			++loop;
+		}
+		igt_assert_eq(matched_after_keychange, 0);
+		break;
+
+
+	default:
+		igt_info("Skipping unknown power-mgt test_cfg = %d\n",
+			test_cfg);
+		break;
+	}
+}
 
 igt_main
 {
 	int i915 = -1;
 	bool pxp_supported = false;
+	struct powermgt_data pm = {0};
 	igt_render_copyfunc_t rendercopy = NULL;
 	uint32_t devid = 0;
 
@@ -714,6 +792,22 @@ igt_main
 			test_render_protected_buffer(i915,
 				COPY3D_PROTECTED_PROTSRC_TO_PROTDST);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+			init_powermgt_resources(i915, &pm);
+		}
+		igt_describe("Verify suspend-resume teardown management:");
+		igt_subtest("verify-pxp-key-change-after-suspend-resume") {
+			test_protected_session_teardown(i915,
+				SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE,
+				&pm);
+		}
+	}
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 10/15] Verify execbuf fails with stale PXP context after teardown

[Alan Previn]

Add a subtest to verify that reusing a stale protected context
in a gem_execbuff after a teardown (triggered by suspend-resume
cycle) shall fail with -EIO error.

NOTE: The end-to-end architecture requirement includes that
any break in the links of the PXP sessions needs to trigger a
full teardown and the application needs to be made aware of that
allowing it to re-establish the end-to-end pipeline of buffers,
contexts and renders again if it chooses to. This stricter
behavior targets only contexts created with PXP enabled.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/intel_batchbuffer.c |   2 +-
 lib/intel_batchbuffer.h |   2 +
 tests/i915/gem_pxp.c    | 115 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 118 insertions(+), 1 deletion(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index be9fc2ad..fa5e0e2f 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2133,7 +2133,7 @@ static void update_offsets(struct intel_bb *ibb,
  * Note: In this step execobj for bb is allocated and inserted to the objects
  * array.
 */
-static int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 			   uint64_t flags, bool sync)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 66af6e09..c838f38b 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -653,6 +653,8 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 					 uint32_t offset,
 					 uint64_t presumed_offset);
 
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+		   uint64_t flags, bool sync);
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 		   uint64_t flags, bool sync);
 
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 06bfb6ca..0cb37177 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -38,6 +38,7 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 
 /* test-configs for power-management triggered protected session teardown */
 #define SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE 1
+#define SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC 2
 
 /* Struct and defintions for power management. */
 struct powermgt_data {
@@ -663,12 +664,88 @@ static void trigger_powermgt_suspend_cycle(int i915,
 	igt_wait_for_pm_status(IGT_RUNTIME_PM_STATUS_SUSPENDED);
 }
 
+#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL	            (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_BEFORE                    0x1234fed0
+#define PS_OP_TAG_AFTER                     0x5678cbaf
+static void emit_pipectrl(struct intel_bb *ibb,
+		 struct intel_buf *fenceb, bool before)
+{
+	uint32_t pipe_ctl_flags = 0;
+	uint32_t ps_op_id;
+
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+	intel_bb_out(ibb, pipe_ctl_flags);
+
+	if (before)
+		ps_op_id = PS_OP_TAG_BEFORE;
+	else
+		ps_op_id = PS_OP_TAG_AFTER;
+
+	pipe_ctl_flags = (PIPE_CONTROL_FLUSH_ENABLE |
+				PIPE_CONTROL_CS_STALL |
+				PIPE_CONTROL_POST_SYNC_OP);
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+	intel_bb_out(ibb, pipe_ctl_flags);
+	intel_bb_emit_reloc(ibb, fenceb->handle,
+		0, I915_GEM_DOMAIN_COMMAND,
+		(before?0:8), fenceb->addr.offset);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, MI_NOOP);
+	intel_bb_out(ibb, MI_NOOP);
+}
+
+static void assert_pipectl_storedw_done(int i915, uint32_t bo)
+{
+	uint32_t *ptr;
+	uint32_t success_mask = 0x0;
+
+	ptr = gem_mmap__device_coherent(i915, bo, 0, 4096, PROT_READ);
+
+	if (ptr[0] == PS_OP_TAG_BEFORE && ptr[1] == PS_OP_TAG_BEFORE)
+		success_mask |= 0x1;
+
+	igt_assert_eq(success_mask, 0x1);
+	igt_assert(gem_munmap(ptr, 4096) == 0);
+}
+
+static void gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb,
+	uint32_t ctx, struct intel_buf *fence, int expected_gemexec_response)
+{
+	int execret;
+
+	intel_bb_ptr_set(ibb, 0);
+	intel_bb_add_intel_buf(ibb, fence, true);
+	emit_pipectrl(ibb, fence, true);
+	intel_bb_emit_bbe(ibb);
+	execret = __intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
+
+	igt_assert_eq(execret, expected_gemexec_response);
+	if (expected_gemexec_response == 0) {
+		gem_sync(ibb->i915, fence->handle);
+		assert_pipectl_storedw_done(i915, fence->handle);
+	}
+}
+
 static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 		struct powermgt_data *pm)
 {
 	uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
 	uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
 	int matched_after_keychange = 0, loop = 0;
+	uint32_t ctx, fencebo;
+	struct intel_buf *fencebuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
 
 	switch (test_cfg) {
 	case SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE:
@@ -691,6 +768,39 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 		igt_assert_eq(matched_after_keychange, 0);
 		break;
 
+	case SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC:
+		ctx = create_protected_ctx(i915, true, true,
+			true, false, 0);
+		assert_ctx_protected_param(i915, ctx, true);
+
+		/* use normal buffers for testing for invalidation
+		 * of protected contexts to ensure kernel is catching
+		 * the invalidated context (not buffer)
+		 */
+		fencebo = alloc_and_fill_dest_buff(i915, false,
+				4096, 0);
+
+		ibb = intel_bb_create_with_context(i915, ctx, 4096);
+		igt_assert(ibb);
+
+		bops = buf_ops_create(i915);
+		igt_assert(bops);
+
+		fencebuf = intel_buf_create_using_handle(bops, fencebo,
+				256, 4,	32, 0, I915_TILING_NONE, 0);
+		intel_bb_add_intel_buf(ibb, fencebuf, true);
+
+		gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, 0);
+		trigger_powermgt_suspend_cycle(i915, pm);
+
+		gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+
+		intel_bb_destroy(ibb);
+		intel_buf_destroy(fencebuf);
+		gem_close(i915, fencebo);
+		gem_context_destroy(i915, ctx);
+		buf_ops_destroy(bops);
+		break;
 
 	default:
 		igt_info("Skipping unknown power-mgt test_cfg = %d\n",
@@ -807,6 +917,11 @@ igt_main
 				SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE,
 				&pm);
 		}
+		igt_subtest("reject-old-prot-context-execution-after-suspend-resume") {
+			test_protected_session_teardown(i915,
+				SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC,
+				&pm);
+		}
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 11/15] Verify execbuf fails with stale PXP buffer after teardown

[Alan Previn]

Add a subtest to verify that reusing a stale protected buffer
in a gem_execbuff (with a protected context) after a teardown
(triggered by suspend-resume cycle) shall fail with -EIO error.

NOTE: The end-to-end architecture requirement includes that
any break in the links of the PXP sessions needs to trigger a
full teardown and the application needs to be made aware of that
allowing it to re-establish the end-to-end pipeline of buffers,
contexts and renders again if it chooses to. This stricter
behavior targets only contexts created with PXP enabled.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 47 +++++++++++++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 9 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 0cb37177..bf6a8ef1 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -39,6 +39,7 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 /* test-configs for power-management triggered protected session teardown */
 #define SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE 1
 #define SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC 2
+#define SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC 3
 
 /* Struct and defintions for power management. */
 struct powermgt_data {
@@ -742,10 +743,10 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 	uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
 	uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
 	int matched_after_keychange = 0, loop = 0;
-	uint32_t ctx, fencebo;
+	uint32_t ctx, ctx2, fencebo;
 	struct intel_buf *fencebuf;
 	struct buf_ops *bops;
-	struct intel_bb *ibb;
+	struct intel_bb *ibb, *ibb2;
 
 	switch (test_cfg) {
 	case SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE:
@@ -769,16 +770,22 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 		break;
 
 	case SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC:
+	case SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC:
 		ctx = create_protected_ctx(i915, true, true,
 			true, false, 0);
 		assert_ctx_protected_param(i915, ctx, true);
 
-		/* use normal buffers for testing for invalidation
-		 * of protected contexts to ensure kernel is catching
-		 * the invalidated context (not buffer)
-		 */
-		fencebo = alloc_and_fill_dest_buff(i915, false,
-				4096, 0);
+		if (test_cfg == SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC) {
+			/* use normal buffers for testing for invalidation
+			 * of protected contexts to ensure kernel is catching
+			 * the invalidated context
+			 */
+			fencebo = alloc_and_fill_dest_buff(i915, false,
+					4096, 0);
+		} else {
+			fencebo = alloc_and_fill_dest_buff(i915, true,
+					4096, 0);
+		}
 
 		ibb = intel_bb_create_with_context(i915, ctx, 4096);
 		igt_assert(ibb);
@@ -793,12 +800,29 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 		gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, 0);
 		trigger_powermgt_suspend_cycle(i915, pm);
 
-		gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+		if (test_cfg == SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC) {
+			/* after teardown, alloc new assets for everything
+			 * except the bo to ensure the kernel is catching
+			 * the invalidated bo
+			 */
+			ctx2 = create_protected_ctx(i915, true, true,
+				true, false, 0);
+			assert_ctx_protected_param(i915, ctx2, true);
+			ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
+			igt_assert(ibb2);
+			gem_execbuf_flush_store_dw(i915, ibb2, ctx2, fencebuf, -EIO);
+		} else {
+			gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+		}
 
 		intel_bb_destroy(ibb);
 		intel_buf_destroy(fencebuf);
 		gem_close(i915, fencebo);
 		gem_context_destroy(i915, ctx);
+		if (test_cfg == SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC) {
+			intel_bb_destroy(ibb2);
+			gem_context_destroy(i915, ctx2);
+		}
 		buf_ops_destroy(bops);
 		break;
 
@@ -922,6 +946,11 @@ igt_main
 				SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC,
 				&pm);
 		}
+		igt_subtest("reject-old-prot-buffer-execution-after-suspend-resume") {
+			test_protected_session_teardown(i915,
+				SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC,
+				&pm);
+		}
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 12/15] Verify execbuf ok with stale prot-buff and regular context

[Alan Previn]

Add a subtest to verify that reusing a stale protected
buffer in a gem_execbuff call, but using a regular (not-
protcted) context will succeed despite after a teardown
(triggered by suspend-resume cycle).

This ensures that user space applications that choose
not to opt-in for strict PXP teardown awareness (by
using a regular context) wont suffer gem_execbuff
failures if a protected buffer was among the assets
used in any of its rendering operations.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index bf6a8ef1..4e50262b 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -40,6 +40,7 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 #define SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE 1
 #define SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC 2
 #define SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC 3
+#define SESSION_PMSUSPEND_STALECTX_STALEPROTBO_EXEC_OK 4
 
 /* Struct and defintions for power management. */
 struct powermgt_data {
@@ -771,9 +772,18 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 
 	case SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC:
 	case SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC:
-		ctx = create_protected_ctx(i915, true, true,
-			true, false, 0);
-		assert_ctx_protected_param(i915, ctx, true);
+	case SESSION_PMSUSPEND_STALECTX_STALEPROTBO_EXEC_OK:
+
+		if (test_cfg == SESSION_PMSUSPEND_STALECTX_STALEPROTBO_EXEC_OK) {
+			ctx = create_protected_ctx(i915, false, false,
+				false, false, 0);
+			assert_ctx_protected_param(i915, ctx, false);
+
+		} else {
+			ctx = create_protected_ctx(i915, true, true,
+				true, false, 0);
+			assert_ctx_protected_param(i915, ctx, true);
+		}
 
 		if (test_cfg == SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC) {
 			/* use normal buffers for testing for invalidation
@@ -812,7 +822,10 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 			igt_assert(ibb2);
 			gem_execbuf_flush_store_dw(i915, ibb2, ctx2, fencebuf, -EIO);
 		} else {
-			gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+			if (test_cfg == SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC)
+				gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, -EIO);
+			else if (test_cfg == SESSION_PMSUSPEND_STALECTX_STALEPROTBO_EXEC_OK)
+				gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, 0);
 		}
 
 		intel_bb_destroy(ibb);
@@ -951,6 +964,11 @@ igt_main
 				SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC,
 				&pm);
 		}
+		igt_subtest("allow-regular-ctx-old-prot-buff-execution-after-suspend-resume") {
+			test_protected_session_teardown(i915,
+				SESSION_PMSUSPEND_STALECTX_STALEPROTBO_EXEC_OK,
+				&pm);
+		}
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 13/15] Ensure RESET_STAT reports invalidated protected context

[Alan Previn]

When protected contexts are created but get invalidated
due to PXP session teardown (such as after a suspend-resume
cycle), RESET_STAT ioctl for said context will report it
as I915_CONTEXT_INVALIDATED.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 4e50262b..05083ac9 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -41,6 +41,7 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 #define SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC 2
 #define SESSION_PMSUSPEND_STALEPROTBO_BAN_EXEC 3
 #define SESSION_PMSUSPEND_STALECTX_STALEPROTBO_EXEC_OK 4
+#define SESSION_PMSUSPEND_STALEPROTCTX_IN_RESETSTAT 5
 
 /* Struct and defintions for power management. */
 struct powermgt_data {
@@ -738,6 +739,25 @@ static void gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb,
 	}
 }
 
+static void check_context_invalid_state(int i915,
+		uint32_t ctx, bool is_expected_invalid)
+{
+	struct drm_i915_reset_stats rs;
+	bool ctx_is_invalid = false;
+	int ret;
+
+	memset(&rs, 0, sizeof(rs));
+	rs.ctx_id = ctx;
+
+	ret = drmIoctl(i915, DRM_IOCTL_I915_GET_RESET_STATS, &rs);
+	igt_assert(ret == 0);
+
+	if (rs.flags & I915_CONTEXT_INVALIDATED)
+		ctx_is_invalid = true;
+	igt_assert_eq(is_expected_invalid, ctx_is_invalid);
+
+}
+
 static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 		struct powermgt_data *pm)
 {
@@ -839,6 +859,29 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 		buf_ops_destroy(bops);
 		break;
 
+	case SESSION_PMSUSPEND_STALEPROTCTX_IN_RESETSTAT:
+		ctx = create_protected_ctx(i915, true, true,
+			true, false, 0);
+		assert_ctx_protected_param(i915, ctx, true);
+
+		ibb = intel_bb_create_with_context(i915, ctx, 4096);
+		igt_assert(ibb);
+
+		bops = buf_ops_create(i915);
+		igt_assert(bops);
+
+		fencebuf = intel_buf_create_using_handle(bops, fencebo,
+				256, 4,	32, 0, I915_TILING_NONE, 0);
+		intel_bb_add_intel_buf(ibb, fencebuf, true);
+
+		gem_execbuf_flush_store_dw(i915, ibb, ctx, fencebuf, 0);
+
+		check_context_invalid_state(i915, ctx, false);
+
+		trigger_powermgt_suspend_cycle(i915, pm);
+		check_context_invalid_state(i915, ctx, true);
+		break;
+
 	default:
 		igt_info("Skipping unknown power-mgt test_cfg = %d\n",
 			test_cfg);
@@ -969,6 +1012,11 @@ igt_main
 				SESSION_PMSUSPEND_STALECTX_STALEPROTBO_EXEC_OK,
 				&pm);
 		}
+		igt_subtest("old-prot-context-reports-reset-stat-after-suspend-resume") {
+			test_protected_session_teardown(i915,
+				SESSION_PMSUSPEND_STALEPROTCTX_IN_RESETSTAT,
+				&pm);
+		}
 	}
 
 	igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 14/15] Verify protected surfaces are dma buffer sharable

[Alan Previn]

Verify we can export a protected surface from
protected context A into protected context B (with
different client driver handles) and protected
rendering is successful even after prior file
handle is closed (i.e. pxp specific refcounting
works).

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 tests/i915/gem_pxp.c | 119 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 05083ac9..583983f2 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -4,6 +4,7 @@
  */
 
 #include <sys/ioctl.h>
+#include <fcntl.h>
 
 #include "igt.h"
 #include "igt_device.h"
@@ -36,6 +37,9 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 #define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
 #define COPY3D_PROTECTED_SRC_TO_PROTDST_SAMPLED 4
 
+/* test-configs for protected rendering with dma-buffer sharing */
+#define BUFSHARED_PROTDST_DUAL_CTX_REFCOUNT 1
+
 /* test-configs for power-management triggered protected session teardown */
 #define SESSION_PMSUSPEND_TEARDOWN_KEY_CHANGE 1
 #define SESSION_PMSUSPEND_STALEPROTCTX_BAN_EXEC 2
@@ -643,6 +647,118 @@ static void __test_render_protected_buffer(int i915, uint32_t test_cfg,
 	buf_ops_destroy(bops);
 }
 
+static int export_handle(int fd, uint32_t handle, int *outfd)
+{
+	struct drm_prime_handle args;
+	int ret;
+
+	args.handle = handle;
+	args.flags = DRM_CLOEXEC;
+	args.fd = -1;
+
+	ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
+	if (ret)
+		ret = errno;
+	*outfd = args.fd;
+
+	return ret;
+}
+
+static void test_sharing_protected_asssets(uint32_t test_cfg)
+{
+	uint32_t ctx[2], sbo[2], dbo[2];
+	struct intel_buf *sbuf[2], *dbuf[2];
+	struct buf_ops *bops[2];
+	struct intel_bb *ibb[2];
+	int fd[2], dmabuf_fd = 0, ret, n, num_matches = 0;
+	uint32_t encrypted[2][TSTSURF_SIZE/TSTSURF_BYTESPP];
+
+	switch (test_cfg) {
+	case BUFSHARED_PROTDST_DUAL_CTX_REFCOUNT:
+		/* First, create the client driver handles and
+		 * protected dest buffer (is exported via dma-buff
+		 * from first handle and imported to the second).
+		 */
+		for (n = 0; n < 2; ++n) {
+			fd[n] = drm_open_driver(DRIVER_INTEL);
+			igt_require(fd[n]);
+			if (n == 0) {
+				dbo[0] = alloc_and_fill_dest_buff(fd[0], true,
+					TSTSURF_SIZE, TSTSURF_INITCOLOR1);
+			} else {
+				ret = export_handle(fd[0], dbo[0], &dmabuf_fd);
+				igt_assert(ret == 0);
+				dbo[1] = prime_fd_to_handle(fd[1], dmabuf_fd);
+				igt_assert(dbo[1]);
+			}
+		}
+		/* Repeat twice: Create a full set of assets to perform
+		 * a protected 3D session but using the same dest buffer
+		 * from above.
+		 */
+		for (n = 0; n < 2; ++n) {
+			ctx[n] = create_protected_ctx(fd[n],
+				true, true, true, false, 0);
+			assert_ctx_protected_param(fd[n],
+				ctx[n], true);
+			bops[n] = buf_ops_create(fd[n]);
+			if (n == 1)
+				fill_bo_content(fd[1], dbo[1],
+					TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+			dbuf[n] = intel_buf_create_using_handle(bops[n],
+					dbo[n], TSTSURF_WIDTH, TSTSURF_HEIGHT,
+					TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+			intel_buf_set_pxp(dbuf[n], true);
+
+			sbo[n] = alloc_and_fill_dest_buff(fd[n], false,
+					TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+			sbuf[n] = intel_buf_create_using_handle(bops[n],
+					sbo[n], TSTSURF_WIDTH, TSTSURF_HEIGHT,
+					TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+			ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
+			intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
+				I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+			gen12_render_copyfunc(ibb[n], sbuf[n], 0, 0,
+				TSTSURF_WIDTH, TSTSURF_HEIGHT, dbuf[n], 0, 0);
+			gem_sync(fd[n], dbo[n]);
+
+			assert_bo_content_check(fd[n], dbo[n],
+				COMPARE_COLOR_UNREADIBLE, TSTSURF_SIZE,
+				TSTSURF_FILLCOLOR1, NULL, 0);
+			assert_bo_content_check(fd[n], dbo[n], COPY_BUFFER,
+				TSTSURF_SIZE, 0, encrypted[n], TSTSURF_SIZE);
+
+			/* free up all assets except the dest buffer to
+			 * verify dma buff refcounting is performed on
+			 * the protected dest buffer on the 2nd loop with
+			 * successful reuse in another protected render.
+			 */
+			intel_bb_destroy(ibb[n]);
+			intel_buf_destroy(sbuf[n]);
+			intel_buf_destroy(dbuf[n]);
+			gem_close(fd[n], sbo[n]);
+			gem_close(fd[n], dbo[n]);
+			gem_context_destroy(fd[n], ctx[n]);
+			close(fd[n]);
+		}
+		/* Verify that encrypted output across loops were equal */
+		for (n = 0; n < (TSTSURF_SIZE/4); ++n)
+			if (encrypted[0][n] == encrypted[1][n])
+				++num_matches;
+		igt_assert(num_matches == (TSTSURF_SIZE/4));
+
+		break;
+
+	default:
+		igt_info("Skipping unknown asset test_cfg = %d\n",
+			test_cfg);
+		break;
+	}
+
+}
+
 static void test_render_protected_buffer(int i915, uint32_t test_cfg)
 {
 	__test_render_protected_buffer(i915, test_cfg, NULL, 0);
@@ -981,6 +1097,9 @@ igt_main
 		igt_subtest("protected-encrypted-src-copy-not-readible")
 			test_render_protected_buffer(i915,
 				COPY3D_PROTECTED_PROTSRC_TO_PROTDST);
+		igt_subtest("dmabuf-shared-protected-dst-is-context-refcounted")
+			test_sharing_protected_asssets(
+				BUFSHARED_PROTDST_DUAL_CTX_REFCOUNT);
 	}
 	igt_subtest_group {
 		igt_fixture {
-- 
2.25.1

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[igt-dev] [PATCH i-g-t v2 15/15] tests/i915_pxp: CRC validation for display tests.

[Alan Previn]

From: Karthik B S <karthik.b.s@intel.com>

Added subtests to validate pxp using CRC validation.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
---
 tests/i915/gem_pxp.c | 276 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 276 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 583983f2..dfc0e15b 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -10,6 +10,7 @@
 #include "igt_device.h"
 #include "igt_sysfs.h"
 #include "i915/gem.h"
+#include <fcntl.h>
 
 IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
 			"that allows the handling of protected content through "
@@ -383,6 +384,7 @@ static void fill_bo_content(int i915, uint32_t bo,
 #define COPY_BUFFER                5
 
 #define COMPARE_N_PIXELS_VERBOSELY 0
+
 static void assert_bo_content_check(int i915, uint32_t bo,
 	int compare_op, uint32_t size, uint32_t color, uint32_t *auxptr, int auxsize)
 {
@@ -489,6 +491,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
 #define TSTSURF_INITCOLOR1  0x12341234
 #define TSTSURF_INITCOLOR2  0x56785678
 #define TSTSURF_INITCOLOR3  0xabcdabcd
+#define TSTSURF_GREENCOLOR  0xFF00FF00
 static void __test_render_protected_buffer(int i915, uint32_t test_cfg,
 	uint32_t *outpixels, int outsize)
 {
@@ -1005,6 +1008,262 @@ static void test_protected_session_teardown(int i915, uint32_t test_cfg,
 	}
 }
 
+static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, uint32_t ctx)
+{
+	int err;
+	uint32_t srcbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	igt_render_copyfunc_t rendercopy;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	rendercopy = igt_get_render_copyfunc(devid);
+	igt_assert(rendercopy);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	igt_init_fb(fb, i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
+		    IGT_COLOR_YCBCR_BT709, IGT_COLOR_YCBCR_LIMITED_RANGE);
+
+	igt_calc_fb_size(i915, width, height, DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE, &fb->size, &fb->strides[0]);
+
+	fb->gem_handle = create_protected_bo(i915, fb->size, true, true, 0);
+	err = __gem_set_tiling(i915, fb->gem_handle,
+			       igt_fb_mod_to_tiling(fb->modifier), fb->strides[0]);
+	igt_assert(err == 0 || err == -EOPNOTSUPP);
+
+	do_or_die(__kms_addfb(fb->fd, fb->gem_handle,fb->width, fb->height, fb->drm_format,
+			      fb->modifier, fb->strides, fb->offsets, fb->num_planes,
+			      LOCAL_DRM_MODE_FB_MODIFIERS, &fb->fb_id));
+
+	dstbuf = intel_buf_create_using_handle(bops, fb->gem_handle,
+					       fb->width, fb->height,
+					       fb->plane_bpp[0], 0, igt_fb_mod_to_tiling(fb->modifier), 0);
+	dstbuf->is_protected = true;
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, fb->size,
+					 TSTSURF_GREENCOLOR);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo,
+					       fb->width, fb->height,
+					       fb->plane_bpp[0], 0, igt_fb_mod_to_tiling(fb->modifier), 0);
+
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+
+	ibb->pxp.enabled = true;
+	ibb->pxp.apptype = DISPLAY_APPTYPE;
+	ibb->pxp.appid = I915_PROTECTED_CONTENT_DEFAULT_SESSION;
+
+	gen12_render_copyfunc(ibb,
+			      srcbuf, 0, 0,
+			      fb->width, fb->height,
+			      dstbuf, 0, 0);
+
+	gem_sync(i915, fb->gem_handle);
+	assert_bo_content_check(i915, fb->gem_handle, COMPARE_COLOR_UNREADIBLE, fb->size, TSTSURF_GREENCOLOR, NULL, 0);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+}
+
+static void __debugfs_read(int fd, const char *param, char *buf, int len)
+{
+	len = igt_debugfs_simple_read(fd, param, buf, len);
+	if (len < 0)
+		igt_assert_eq(len, -ENODEV);
+}
+
+#define debugfs_read(fd, p, arr) __debugfs_read(fd, p, arr, sizeof(arr))
+#define MAX_SINK_HDCP_CAP_BUF_LEN	5000
+
+#define CP_UNDESIRED				0
+#define CP_DESIRED				1
+#define CP_ENABLED				2
+
+#define KERNEL_AUTH_TIME_ALLOWED_MSEC		(3 *  6 * 1000)
+#define KERNEL_DISABLE_TIME_ALLOWED_MSEC	(1 * 1000)
+
+static bool
+wait_for_prop_value(igt_output_t *output, uint64_t expected,
+		    uint32_t timeout_mSec)
+{
+	uint64_t val;
+	int i;
+
+	for (i = 0; i < timeout_mSec; i++) {
+		val = igt_output_get_prop(output, IGT_CONNECTOR_CONTENT_PROTECTION);
+		if (val == expected)
+			return true;
+		usleep(1000);
+	}
+
+	igt_info("prop_value mismatch %" PRId64 " != %" PRId64 "\n", val, expected);
+
+	return false;
+}
+
+static bool sink_hdcp_capable(int i915, igt_output_t *output)
+{
+	char buf[MAX_SINK_HDCP_CAP_BUF_LEN];
+	int fd;
+
+	fd = igt_debugfs_connector_dir(i915, output->name, O_RDONLY);
+	if (fd < 0)
+		return false;
+
+	if (is_i915_device(i915))
+		debugfs_read(fd, "i915_hdcp_sink_capability", buf);
+	else
+		debugfs_read(fd, "hdcp_sink_capability", buf);
+
+	close(fd);
+
+	igt_debug("Sink capability: %s\n", buf);
+
+	return strstr(buf, "HDCP1.4");
+}
+
+static bool output_hdcp_capable(int i915, igt_output_t *output, bool content_type)
+{
+	if (!output->props[IGT_CONNECTOR_CONTENT_PROTECTION])
+		return false;
+	if (!output->props[IGT_CONNECTOR_HDCP_CONTENT_TYPE] && content_type)
+		return false;
+	if (!sink_hdcp_capable(i915, output))
+		return false;
+
+	return true;
+}
+
+static void test_display_protected_crc(int i915, igt_display_t *display, bool hdcp)
+{
+	igt_output_t *output;
+	drmModeModeInfo *mode;
+	igt_fb_t ref_fb, protected_fb;
+	igt_plane_t *plane;
+	igt_pipe_t *pipe;
+	igt_pipe_crc_t *pipe_crc;
+	igt_crc_t ref_crc, new_crc;
+	int width = 0, height = 0, i = 0, ret, count, valid_outputs = 0;
+	uint32_t ctx;
+	igt_output_t *hdcp_output[IGT_MAX_PIPES];
+
+	ctx = create_protected_ctx(i915, true, true,
+				   true, false, 0);
+
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+
+		width = max(width, mode->hdisplay);
+		height = max(height, mode->vdisplay);
+
+		if (!output_hdcp_capable(i915, output, 0))
+			continue;
+
+		hdcp_output[valid_outputs++] = output;
+	}
+
+	if (hdcp)
+		igt_require_f(valid_outputs > 0,
+			      "No HDCP capable connector found\n");
+
+	igt_create_color_fb(i915, width, height, DRM_FORMAT_XRGB8888,
+			    LOCAL_DRM_FORMAT_MOD_NONE, 0, 1, 0, &ref_fb);
+
+	/* Do a modeset on all outputs */
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+		pipe = &display->pipes[i];
+		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
+		igt_require(igt_pipe_connector_valid(i, output));
+		igt_output_set_pipe(output, i);
+
+		igt_plane_set_fb(plane, &ref_fb);
+		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		i++;
+	}
+
+	if (hdcp) {
+		/* Enable HDCP on all the valid connectors */
+		for (count = 0; count < valid_outputs; count++) {
+			igt_output_set_prop_value(hdcp_output[count], IGT_CONNECTOR_CONTENT_PROTECTION, CP_DESIRED);
+			if (output->props[IGT_CONNECTOR_HDCP_CONTENT_TYPE])
+				igt_output_set_prop_value(hdcp_output[count], IGT_CONNECTOR_HDCP_CONTENT_TYPE, 0);
+		}
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+
+		/*Verify that HDCP is enabled on all valid connectors */
+		for (count = 0; count < valid_outputs; count++) {
+			ret = wait_for_prop_value(hdcp_output[count], CP_ENABLED, KERNEL_AUTH_TIME_ALLOWED_MSEC);
+			igt_assert_f(ret, "Content Protection not enabled on %s\n", hdcp_output[count]->name);
+		}
+	}
+
+	setup_protected_fb(i915, width, height, &protected_fb, ctx);
+
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+		pipe = &display->pipes[output->pending_pipe];
+		pipe_crc = igt_pipe_crc_new(i915, pipe->pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
+		igt_require(igt_pipe_connector_valid(pipe->pipe, output));
+		igt_output_set_pipe(output, pipe->pipe);
+
+		igt_plane_set_fb(plane, &ref_fb);
+		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(pipe_crc, &ref_crc);
+
+		igt_plane_set_fb(plane, &protected_fb);
+		igt_fb_set_size(&protected_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
+		igt_assert_crc_equal(&ref_crc, &new_crc);
+
+		if (hdcp) {
+			/* Disable HDCP and collect CRC */
+			igt_output_set_prop_value(hdcp_output[0], IGT_CONNECTOR_CONTENT_PROTECTION,
+						  CP_UNDESIRED);
+			igt_display_commit2(display, COMMIT_ATOMIC);
+			ret = wait_for_prop_value(hdcp_output[0], CP_UNDESIRED,
+						  KERNEL_DISABLE_TIME_ALLOWED_MSEC);
+			igt_assert_f(ret, "Content Protection not cleared\n");
+
+			igt_plane_set_fb(plane, &protected_fb);
+			igt_fb_set_size(&protected_fb, plane, mode->hdisplay, mode->vdisplay);
+			igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+			igt_display_commit2(display, COMMIT_ATOMIC);
+			igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
+			igt_assert_f(!igt_check_crc_equal(&ref_crc, &new_crc),
+				     "CRC's are expected to be different after HDCP is disabled\n");
+		}
+		/*
+		 * Testing with one pipe-output combination is sufficient.
+		 * So break the loop.
+		 */
+		break;
+	}
+
+	gem_context_destroy(i915, ctx);
+	igt_remove_fb(i915, &ref_fb);
+	igt_remove_fb(i915, &protected_fb);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -1012,6 +1271,7 @@ igt_main
 	struct powermgt_data pm = {0};
 	igt_render_copyfunc_t rendercopy = NULL;
 	uint32_t devid = 0;
+	igt_display_t display;
 
 	igt_fixture
 	{
@@ -1137,7 +1397,23 @@ igt_main
 				&pm);
 		}
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
 
+			igt_require_pipe_crc(i915);
+			igt_display_require(&display, i915);
+		}
+		igt_describe("Test the display CRC");
+		igt_subtest("display-protected-crc-without-hdcp")
+			test_display_protected_crc(i915, &display, 0);
+		igt_subtest("display-protected-crc-with-hdcp")
+			test_display_protected_crc(i915, &display, 1);
+	}
 	igt_fixture {
 		close(i915);
 	}
-- 
2.25.1

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[igt-dev] ✓ Fi.CI.BAT: success for Introduce PXP Test (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 5057 bytes --]

== Series Details ==

Series: Introduce PXP Test (rev2)
URL   : https://patchwork.freedesktop.org/series/87570/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9892 -> IGTPW_5660
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/index.html

Known issues
------------

  Here are the changes found in IGTPW_5660 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bsw-nick:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html

  * igt@gem_render_tiled_blits@basic:
    - fi-tgl-y:           [PASS][2] -> [DMESG-WARN][3] ([i915#402])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/fi-tgl-y/igt@gem_render_tiled_blits@basic.html

  * igt@runner@aborted:
    - fi-bdw-5557u:       NOTRUN -> [FAIL][4] ([i915#1602] / [i915#2029])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/fi-bdw-5557u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-y:           [DMESG-WARN][5] ([i915#2411] / [i915#402]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_flink_basic@bad-open:
    - fi-tgl-y:           [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/fi-tgl-y/igt@gem_flink_basic@bad-open.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/fi-tgl-y/igt@gem_flink_basic@bad-open.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [INCOMPLETE][9] ([i915#2782] / [i915#2940]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@hangcheck:
    - {fi-hsw-gt1}:       [DMESG-WARN][11] -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (47 -> 42)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-dg1-1 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6046 -> IGTPW_5660

  CI-20190529: 20190529
  CI_DRM_9892: 928f83ba052b80754da4bebdd37a1b17c1157f1b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5660: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/index.html
  IGT_6046: e76039273b1524147c43dba061756f06003d56ae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_pxp@allow-regular-ctx-old-prot-buff-execution-after-suspend-resume
+igt@gem_pxp@create-protected-buffer
+igt@gem_pxp@create-regular-buffer
+igt@gem_pxp@create-regular-context-1
+igt@gem_pxp@create-regular-context-2
+igt@gem_pxp@create-valid-protected-context
+igt@gem_pxp@display-protected-crc-without-hdcp
+igt@gem_pxp@display-protected-crc-with-hdcp
+igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted
+igt@gem_pxp@fail-invalid-protected-context
+igt@gem_pxp@hw-rejects-pxp-buffer
+igt@gem_pxp@hw-rejects-pxp-context
+igt@gem_pxp@old-prot-context-reports-reset-stat-after-suspend-resume
+igt@gem_pxp@protected-encrypted-src-copy-not-readible
+igt@gem_pxp@protected-raw-src-copy-not-readible
+igt@gem_pxp@regular-baseline-src-copy-readible
+igt@gem_pxp@reject-modify-context-protection-off-1
+igt@gem_pxp@reject-modify-context-protection-off-2
+igt@gem_pxp@reject-modify-context-protection-off-3
+igt@gem_pxp@reject-modify-context-protection-on
+igt@gem_pxp@reject-old-prot-buffer-execution-after-suspend-resume
+igt@gem_pxp@reject-old-prot-context-execution-after-suspend-resume
+igt@gem_pxp@verify-pxp-key-change-after-suspend-resume

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/index.html

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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✗ Fi.CI.IGT: failure for Introduce PXP Test (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30233 bytes --]

== Series Details ==

Series: Introduce PXP Test (rev2)
URL   : https://patchwork.freedesktop.org/series/87570/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9892_full -> IGTPW_5660_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_5660_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_5660_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_5660_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@gem_pxp@create-regular-context-1} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1] +24 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb5/igt@gem_pxp@create-regular-context-1.html

  * {igt@gem_pxp@hw-rejects-pxp-context} (NEW):
    - shard-glk:          NOTRUN -> [FAIL][2] +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk5/igt@gem_pxp@hw-rejects-pxp-context.html
    - shard-iclb:         NOTRUN -> [FAIL][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb7/igt@gem_pxp@hw-rejects-pxp-context.html

  * {igt@gem_pxp@regular-baseline-src-copy-readible} (NEW):
    - shard-tglb:         NOTRUN -> [FAIL][4] +17 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb6/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_userptr_blits@set-cache-level:
    - shard-snb:          NOTRUN -> [FAIL][5] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-snb5/igt@gem_userptr_blits@set-cache-level.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [INCOMPLETE][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl8/igt@gem_userptr_blits@vma-merge.html
    - shard-iclb:         NOTRUN -> [INCOMPLETE][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb6/igt@gem_userptr_blits@vma-merge.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk2/igt@gem_userptr_blits@vma-merge.html
    - shard-tglb:         NOTRUN -> [INCOMPLETE][9]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb5/igt@gem_userptr_blits@vma-merge.html

  * igt@gen9_exec_parse@bb-large:
    - shard-kbl:          NOTRUN -> [FAIL][10] +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl4/igt@gen9_exec_parse@bb-large.html

  * igt@sysfs_clients@fair-3:
    - shard-tglb:         NOTRUN -> [SKIP][11] +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb3/igt@sysfs_clients@fair-3.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@i915_pm_dc@dc9-dpms}:
    - shard-iclb:         NOTRUN -> [FAIL][12]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html

  * {igt@kms_cursor_crc@pipe-d-cursor-32x10-onscreen}:
    - shard-tglb:         NOTRUN -> [SKIP][13]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-32x10-onscreen.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9892_full and IGTPW_5660_full:

### New IGT tests (23) ###

  * igt@gem_pxp@allow-regular-ctx-old-prot-buff-execution-after-suspend-resume:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@create-protected-buffer:
    - Statuses : 1 pass(s) 4 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@create-regular-buffer:
    - Statuses : 1 pass(s) 5 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@create-regular-context-1:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@create-regular-context-2:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@create-valid-protected-context:
    - Statuses : 1 fail(s) 2 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@display-protected-crc-with-hdcp:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@display-protected-crc-without-hdcp:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.02] s

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.05] s

  * igt@gem_pxp@fail-invalid-protected-context:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - Statuses : 4 fail(s) 1 skip(s)
    - Exec time: [0.0, 0.15] s

  * igt@gem_pxp@hw-rejects-pxp-context:
    - Statuses : 3 fail(s) 1 skip(s)
    - Exec time: [0.0, 0.10] s

  * igt@gem_pxp@old-prot-context-reports-reset-stat-after-suspend-resume:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - Statuses : 1 fail(s) 3 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@reject-modify-context-protection-off-2:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.02] s

  * igt@gem_pxp@reject-modify-context-protection-on:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_pxp@reject-old-prot-buffer-execution-after-suspend-resume:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.04] s

  * igt@gem_pxp@reject-old-prot-context-execution-after-suspend-resume:
    - Statuses : 1 fail(s) 5 skip(s)
    - Exec time: [0.0, 0.02] s

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - Statuses : 1 fail(s) 4 skip(s)
    - Exec time: [0.0, 0.04] s

  

Known issues
------------

  Here are the changes found in IGTPW_5660_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@idempotent:
    - shard-snb:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +4 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-snb5/igt@gem_ctx_persistence@idempotent.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [PASS][15] -> [FAIL][16] ([i915#2846])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][17] ([i915#2842])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [PASS][20] -> [FAIL][21] ([i915#2842]) +4 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-iclb:         NOTRUN -> [SKIP][22] ([fdo#109283])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb3/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][23] ([i915#2389])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb1/igt@gem_exec_reloc@basic-many-active@vcs1.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#2190])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][25] ([i915#2658]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl6/igt@gem_pread@exhaustion.html
    - shard-snb:          NOTRUN -> [WARN][26] ([i915#2658])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-snb6/igt@gem_pread@exhaustion.html

  * {igt@gem_pxp@reject-old-prot-context-execution-after-suspend-resume} (NEW):
    - shard-apl:          NOTRUN -> [SKIP][27] ([fdo#109271]) +257 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl8/igt@gem_pxp@reject-old-prot-context-execution-after-suspend-resume.html

  * igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#768])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb3/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +3 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen7_exec_parse@cmd-crossing-page:
    - shard-tglb:         NOTRUN -> [SKIP][31] ([fdo#109289]) +3 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb8/igt@gen7_exec_parse@cmd-crossing-page.html

  * igt@gen7_exec_parse@oacontrol-tracking:
    - shard-glk:          NOTRUN -> [SKIP][32] ([fdo#109271]) +55 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk7/igt@gen7_exec_parse@oacontrol-tracking.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-iclb:         NOTRUN -> [SKIP][33] ([fdo#112306])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb6/igt@gen9_exec_parse@bb-start-out.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-apl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#1937])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         NOTRUN -> [WARN][35] ([i915#2684])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_query@query-topology-unsupported:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109302])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb6/igt@i915_query@query-topology-unsupported.html

  * igt@kms_async_flips@test-time-stamp:
    - shard-tglb:         [PASS][37] -> [FAIL][38] ([i915#2597])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb7/igt@kms_async_flips@test-time-stamp.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-iclb:         NOTRUN -> [SKIP][39] ([i915#1769])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#1769])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@edp-1-pipe-b:
    - shard-iclb:         [PASS][41] -> [FAIL][42] ([i915#3168])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-iclb6/igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@edp-1-pipe-b.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb4/igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@edp-1-pipe-b.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][43] ([fdo#111614])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb6/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#110725] / [fdo#111614]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb7/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo:
    - shard-snb:          NOTRUN -> [SKIP][45] ([fdo#109271]) +392 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-snb2/igt@kms_ccs@pipe-a-ccs-on-another-bo.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +25 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl2/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-audio-edid:
    - shard-kbl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl2/igt@kms_chamelium@hdmi-audio-edid.html

  * igt@kms_chamelium@hdmi-hpd:
    - shard-glk:          NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk8/igt@kms_chamelium@hdmi-hpd.html
    - shard-tglb:         NOTRUN -> [SKIP][49] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb5/igt@kms_chamelium@hdmi-hpd.html

  * igt@kms_chamelium@vga-hpd-with-enabled-mode:
    - shard-iclb:         NOTRUN -> [SKIP][50] ([fdo#109284] / [fdo#111827]) +6 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb4/igt@kms_chamelium@vga-hpd-with-enabled-mode.html

  * igt@kms_color@pipe-d-degamma:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109278] / [i915#1149]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb4/igt@kms_color@pipe-d-degamma.html
    - shard-tglb:         NOTRUN -> [FAIL][52] ([i915#1149])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb7/igt@kms_color@pipe-d-degamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][53] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
    - shard-snb:          NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +20 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-snb7/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][55] ([fdo#109278] / [fdo#109279]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb5/igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x170-random:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([fdo#109279]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-random.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][57] -> [FAIL][58] ([i915#72])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109274] / [fdo#109278]) +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
    - shard-apl:          NOTRUN -> [DMESG-FAIL][60] ([IGT#6])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - shard-glk:          [PASS][61] -> [FAIL][62] ([i915#52] / [i915#54]) +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-glk2/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk7/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([fdo#109274]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb3/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-tglb:         NOTRUN -> [SKIP][64] ([fdo#111825]) +14 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb8/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-apl:          NOTRUN -> [FAIL][65] ([i915#2641])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-apl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2672])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-tglb:         NOTRUN -> [SKIP][67] ([i915#2587])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2642])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
    - shard-glk:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2642])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_flip_tiling@flip-changes-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([fdo#111615])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb6/igt@kms_flip_tiling@flip-changes-tiling-yf.html

  * igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][71] ([fdo#109280]) +18 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-tglb:         [PASS][72] -> [SKIP][73] ([i915#433])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-tglb6/igt@kms_hdmi_inject@inject-audio.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb1/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][75] ([i915#180])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#533])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-apl:          NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][78] ([i915#265])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-d-coverage-vs-premult-vs-constant:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([fdo#109278]) +12 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb2/igt@kms_plane_alpha_blend@pipe-d-coverage-vs-premult-vs-constant.html

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
    - shard-kbl:          NOTRUN -> [SKIP][80] ([fdo#109271]) +84 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl6/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2733])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
    - shard-kbl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2733])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl4/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
    - shard-glk:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2733])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk9/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +4 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
    - shard-iclb:         NOTRUN -> [SKIP][85] ([i915#658]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
    - shard-glk:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#658])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-kbl:          NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][88] -> [SKIP][89] ([fdo#109441]) +1 similar issue
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb7/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_psr@psr2_primary_render:
    - shard-iclb:         NOTRUN -> [SKIP][90] ([fdo#109441])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb5/igt@kms_psr@psr2_primary_render.html

  * igt@kms_setmode@basic:
    - shard-snb:          NOTRUN -> [FAIL][91] ([i915#31])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-snb5/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][92] -> [DMESG-WARN][93] ([i915#180] / [i915#295])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-glk:          NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#533])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk9/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-apl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2437])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl6/igt@kms_writeback@writeback-pixel-formats.html

  * igt@nouveau_crc@pipe-b-source-rg:
    - shard-iclb:         NOTRUN -> [SKIP][96] ([i915#2530]) +1 similar issue
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb7/igt@nouveau_crc@pipe-b-source-rg.html
    - shard-tglb:         NOTRUN -> [SKIP][97] ([i915#2530]) +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb2/igt@nouveau_crc@pipe-b-source-rg.html

  * igt@perf@polling-parameterized:
    - shard-iclb:         [PASS][98] -> [FAIL][99] ([i915#1542])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-iclb7/igt@perf@polling-parameterized.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb2/igt@perf@polling-parameterized.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-iclb:         NOTRUN -> [SKIP][100] ([fdo#109289]) +3 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb1/igt@perf@unprivileged-single-ctx-counters.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-tglb:         NOTRUN -> [SKIP][101] ([fdo#109291]) +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb1/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@prime_nv_test@nv_i915_sharing:
    - shard-iclb:         NOTRUN -> [SKIP][102] ([fdo#109291]) +2 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb6/igt@prime_nv_test@nv_i915_sharing.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-glk:          [TIMEOUT][103] ([i915#2918]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-glk3/igt@gem_ctx_persistence@close-replace-race.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk8/igt@gem_ctx_persistence@close-replace-race.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-apl:          [FAIL][105] ([i915#2842]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][107] ([i915#2849]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_whisper@basic-fds-priority-all:
    - shard-glk:          [DMESG-WARN][109] ([i915#118] / [i915#95]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-glk1/igt@gem_exec_whisper@basic-fds-priority-all.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk2/igt@gem_exec_whisper@basic-fds-priority-all.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-iclb:         [INCOMPLETE][111] ([i915#1895] / [i915#2405]) -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-iclb4/igt@gem_exec_whisper@basic-queues-forked.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-iclb7/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][113] ([i915#2190]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb5/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@big-copy:
    - shard-glk:          [FAIL][115] ([i915#307]) -> [PASS][116] +1 similar issue
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-glk3/igt@gem_mmap_gtt@big-copy.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-glk6/igt@gem_mmap_gtt@big-copy.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][117] ([i915#180]) -> [PASS][118] +1 similar issue
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-tglb:         [FAIL][119] ([i915#2346]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9892/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/shard-tglb1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
    - shard-glk:

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5660/index.html

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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t v2 02/15] Add basic PXP testing of buffer and context alloc

[Rodrigo Vivi]

On Wed, Mar 24, 2021 at 10:45:36PM -0700, Alan Previn wrote:
> Test PXP capability support as well as the allocation of protected
> buffers and protected contexts.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  tests/Makefile.sources |   3 +
>  tests/i915/gem_pxp.c   | 410 +++++++++++++++++++++++++++++++++++++++++
>  tests/meson.build      |   1 +
>  3 files changed, 414 insertions(+)
>  create mode 100644 tests/i915/gem_pxp.c
> 
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 4f24fb3a..05952066 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -370,6 +370,9 @@ gem_pwrite_SOURCES = i915/gem_pwrite.c
>  TESTS_progs += gem_pwrite_snooped
>  gem_pwrite_snooped_SOURCES = i915/gem_pwrite_snooped.c
>  
> +TESTS_progs += gem_pxp
> +gem_pxp_SOURCES = i915/gem_pxp.c
> +
>  TESTS_progs += gem_read_read_speed
>  gem_read_read_speed_SOURCES = i915/gem_read_read_speed.c
>  
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> new file mode 100644
> index 00000000..40a817b2
> --- /dev/null
> +++ b/tests/i915/gem_pxp.c
> @@ -0,0 +1,410 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include <sys/ioctl.h>
> +
> +#include "igt.h"
> +#include "i915/gem.h"
> +
> +IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
> +			"that allows the handling of protected content through "
> +			"the arbitration of hardware protected sessions.");
> +
> +/* test-configs for protected buffer creation*/

                                                ^ missing space

> +#define BO_ALLOC_NO_HW_SUPPORT 1
> +#define BO_ALLOC_PROTECT_ON 2
> +#define BO_ALLOC_PROTECT_OFF 3
> +
> +/* test-configs for protected context creation*/

                                                 ^ missing space

> +#define CTX_ALLOC_NO_HW_SUPPORT 1
> +#define CTX_ALLOC_RECOVER_OFF_PROTECT_OFF 2
> +#define CTX_ALLOC_RECOVER_OFF_PROTECT_ON 3
> +#define CTX_ALLOC_RECOVER_ON_PROTECT_OFF 4
> +#define CTX_ALLOC_RECOVER_ON_PROTECT_ON 5
> +#define CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON 6
> +#define CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF 7
> +#define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
> +#define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
> +
> +static bool is_pxp_hw_supported(int i915)
> +{
> +	uint32_t gen;
> +
> +	gen = intel_gen(intel_get_drm_devid(i915));
> +	if (!gen) {
> +		igt_info("No device info found - assume no PXP support.\n");
> +		return false;
> +	}
> +
> +	if (gen >= 12)
> +		return true;
> +
> +	return false;
> +}
> +
> +static uint32_t create_protected_bo(int i915, uint32_t size,
> +				    bool with_protected_param,
> +				    bool protected_is_true, int expected_return)

why do you need both with_protected_param and protected_is_true?
I searched the series and it looks like they always match, so why not simply

static uint32_t create_bo(int i915, uint32_t size, bool protected, int return_assert)

?

> +{
> +	int ret;
> +
> +	struct drm_i915_gem_object_param protected_param = {
> +		.param = I915_OBJECT_PARAM | I915_OBJECT_PARAM_PROTECTED_CONTENT,
> +		.data = 0,
> +	};
> +
> +	struct drm_i915_gem_create_ext_setparam setparam_protected = {
> +		.base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
> +		.param = protected_param,
> +	};
> +
> +	struct drm_i915_gem_create_ext create_ext = {
> +		.size = size,
> +		.extensions = (uintptr_t)&setparam_protected,
> +	};
> +
> +	if (!with_protected_param) {
> +		create_ext.extensions = 0;
> +	} else {
> +		if (protected_is_true) {
> +			protected_param.data = 1;
> +			setparam_protected.param = protected_param;
> +		} else {
> +			protected_param.data = 0;
> +			setparam_protected.param = protected_param;
> +		}
> +	}
> +
> +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
> +	igt_assert_eq(ret, expected_return);
> +
> +	return create_ext.handle;
> +}
> +
> +static void test_create_protected_buffer(int i915, uint32_t test_cfg)
> +{
> +	uint32_t bo;
> +
> +	switch (test_cfg) {
> +	case BO_ALLOC_NO_HW_SUPPORT:
> +		bo = create_protected_bo(i915, 4096, false, false, 0);
> +		gem_close(i915, bo);
> +		bo = create_protected_bo(i915, 4096, true, true, -ENODEV);
> +		igt_assert_eq(bo, 0);
> +		break;
> +
> +	case BO_ALLOC_PROTECT_OFF:
> +		bo = create_protected_bo(i915, 4096, false, false, 0);
> +		gem_close(i915, bo);
> +		break;
> +
> +	case BO_ALLOC_PROTECT_ON:
> +		bo = create_protected_bo(i915, 4096, true, true, 0);
> +		gem_close(i915, bo);
> +		break;
> +
> +	default:
> +		igt_info("Skipping unknown buffer test_cfg = %d\n", test_cfg);
> +		break;
> +	}
> +}
> +
> +static int create_ext_ioctl(int i915,
> +			    struct drm_i915_gem_context_create_ext *arg)
> +{
> +	int err;
> +
> +	err = 0;
> +	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
> +		err = -errno;
> +		igt_assume(err);
> +	}
> +
> +	errno = 0;
> +	return err;
> +}
> +
> +static uint32_t create_protected_ctx(int i915, bool with_protected_param,
> +				     bool protected_is_true,
> +				     bool with_recoverable_param,
> +				     bool recoverable_is_true,
> +				     int expected_return)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_create_ext_setparam p_prot = {
> +		.base = {
> +			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> +			.next_extension = 0,
> +		},
> +		.param = {
> +			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
> +			.value = 0,
> +		}
> +	};
> +	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
> +		.base = {
> +			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> +			.next_extension = 0,
> +		},
> +		.param = {
> +			.param = I915_CONTEXT_PARAM_RECOVERABLE,
> +			.value = 0,
> +		}
> +	};
> +	struct drm_i915_gem_context_create_ext create = {
> +		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> +		.extensions = 0,
> +	};
> +
> +	p_prot.param.value = protected_is_true;
> +	p_norecover.param.value = recoverable_is_true;
> +
> +	if (with_protected_param && with_recoverable_param) {
> +		create.extensions = to_user_pointer(&(p_norecover.base));
> +		p_norecover.base.next_extension =
> +			to_user_pointer(&(p_prot.base));
> +	} else if (!with_protected_param && with_recoverable_param) {
> +		create.extensions = to_user_pointer(&(p_norecover.base));
> +		p_norecover.base.next_extension = 0;
> +	} else if (with_protected_param && !with_recoverable_param) {
> +		create.extensions = to_user_pointer(&(p_prot.base));
> +		p_prot.base.next_extension = 0;
> +	} else if (!with_protected_param && !with_recoverable_param) {
> +		create.flags = 0;
> +	}
> +
> +	ret = create_ext_ioctl(i915, &create);
> +	igt_assert_eq(ret, expected_return);
> +
> +	return create.ctx_id;
> +}
> +
> +#define CHANGE_PARAM_PROTECTED 0x0001
> +#define CHANGE_PARAM_RECOVERY 0x0002
> +static void modify_ctx_protected_param(int i915, uint32_t ctx_id,
> +				       uint32_t change_param_mask,
> +				       bool param_value, int expected_return)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.ctx_id = ctx_id,
> +		.param = 0,
> +		.value = 0,
> +	};
> +
> +	if (change_param_mask == CHANGE_PARAM_PROTECTED) {
> +		ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
> +		ctx_param.value = (int)param_value;
> +	} else if (change_param_mask == CHANGE_PARAM_RECOVERY) {
> +		ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
> +		ctx_param.value = (int)param_value;
> +	} else {
> +		return;
> +	}
> +
> +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &ctx_param);
> +
> +	igt_assert_eq(ret, expected_return);
> +}
> +
> +static void assert_ctx_protected_param(int i915, uint32_t ctx_id,
> +				       bool is_protected)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.ctx_id = ctx_id,
> +		.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
> +	};
> +
> +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_eq(ctx_param.value, (int)is_protected);
> +}
> +
> +static void assert_ctx_recovery_param(int i915, uint32_t ctx_id,
> +				      bool is_recoverable)
> +{
> +	int ret;
> +
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.ctx_id = ctx_id,
> +		.param = I915_CONTEXT_PARAM_RECOVERABLE,
> +	};
> +
> +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_eq(ctx_param.value, (int)is_recoverable);
> +}
> +
> +static void test_create_protected_context(int i915, uint32_t test_cfg)
> +{
> +	uint32_t ctx;
> +
> +	switch (test_cfg) {
> +	case CTX_ALLOC_NO_HW_SUPPORT:
> +		ctx = create_protected_ctx(i915, true, true, true, false,
> +					   -ENODEV);
> +		igt_assert_eq(ctx, 0);
> +	case CTX_ALLOC_RECOVER_OFF_PROTECT_OFF:
> +		ctx = create_protected_ctx(i915, true, false, true, false, 0);
> +		assert_ctx_protected_param(i915, ctx, false);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	case CTX_ALLOC_RECOVER_OFF_PROTECT_ON:
> +		ctx = create_protected_ctx(i915, true, true, true, false, 0);
> +		assert_ctx_protected_param(i915, ctx, true);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	case CTX_ALLOC_RECOVER_ON_PROTECT_OFF:
> +		ctx = create_protected_ctx(i915, true, false, true, true, 0);
> +		assert_ctx_protected_param(i915, ctx, false);
> +		assert_ctx_recovery_param(i915, ctx, true);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	case CTX_ALLOC_RECOVER_ON_PROTECT_ON:
> +		ctx = create_protected_ctx(i915, true, true, true, true,
> +					   -EPERM);
> +		igt_assert_eq(ctx, 0);
> +		ctx = create_protected_ctx(i915, true, true, false, false,
> +					   -EPERM);
> +		igt_assert_eq(ctx, 0);
> +		break;
> +
> +	case CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON:
> +		ctx = create_protected_ctx(i915, true, true, true, false, 0);
> +		assert_ctx_protected_param(i915, ctx, true);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
> +					   true, -EPERM);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	case CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF:
> +		ctx = create_protected_ctx(i915, true, true, true, false, 0);
> +		assert_ctx_protected_param(i915, ctx, true);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
> +					   false, -EPERM);
> +		assert_ctx_protected_param(i915, ctx, true);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	case CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID:
> +		ctx = create_protected_ctx(i915, true, true, true, false, 0);
> +		assert_ctx_protected_param(i915, ctx, true);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
> +					   true, -EPERM);
> +		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
> +					   false, -EPERM);
> +		assert_ctx_protected_param(i915, ctx, true);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	case CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID:
> +		ctx = create_protected_ctx(i915, false, false, false, false, 0);
> +		assert_ctx_protected_param(i915, ctx, false);
> +		assert_ctx_recovery_param(i915, ctx, true);
> +		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_RECOVERY,
> +					   false, 0);
> +		modify_ctx_protected_param(i915, ctx, CHANGE_PARAM_PROTECTED,
> +					   true, -EPERM);
> +		assert_ctx_protected_param(i915, ctx, false);
> +		assert_ctx_recovery_param(i915, ctx, false);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	default:
> +		igt_info("Skipping unknown context test_cfg = %d\n", test_cfg);
> +		break;
> +	}
> +}
> +
> +igt_main
> +{
> +	int i915 = -1;
> +	bool pxp_supported = false;
> +
> +	igt_fixture
> +	{
> +		i915 = drm_open_driver(DRIVER_INTEL);
> +		igt_require(i915);
> +		igt_require_gem(i915);
> +		pxp_supported = is_pxp_hw_supported(i915);
> +	}
> +
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require((pxp_supported == 0));
> +		}
> +
> +		igt_describe("Verify protected buffer on unsupported hw:");
> +		igt_subtest("hw-rejects-pxp-buffer")
> +			test_create_protected_buffer(i915,
> +				BO_ALLOC_NO_HW_SUPPORT);
> +		igt_describe("Verify protected context on unsupported hw:");
> +		igt_subtest("hw-rejects-pxp-context")
> +			test_create_protected_context(i915,
> +				CTX_ALLOC_NO_HW_SUPPORT);
> +	}
> +
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require(pxp_supported);
> +		}
> +
> +		igt_describe("Verify protected buffer on supported hw:");
> +		igt_subtest("create-regular-buffer")
> +			test_create_protected_buffer(i915,
> +				BO_ALLOC_PROTECT_OFF);
> +		igt_subtest("create-protected-buffer")
> +			test_create_protected_buffer(i915, BO_ALLOC_PROTECT_ON);
> +
> +		igt_describe("Verify protected context on supported hw:");
> +		igt_subtest("create-regular-context-1")
> +			test_create_protected_context(
> +				i915, CTX_ALLOC_RECOVER_OFF_PROTECT_OFF);
> +		igt_subtest("create-regular-context-2")
> +			test_create_protected_context(
> +				i915, CTX_ALLOC_RECOVER_ON_PROTECT_OFF);
> +		igt_subtest("fail-invalid-protected-context")
> +			test_create_protected_context(
> +				i915, CTX_ALLOC_RECOVER_ON_PROTECT_ON);
> +		igt_subtest("create-valid-protected-context")
> +			test_create_protected_context(
> +				i915, CTX_ALLOC_RECOVER_OFF_PROTECT_ON);
> +
> +		igt_describe("Verify protected context integrity:");
> +		igt_subtest("reject-modify-context-protection-on")
> +			test_create_protected_context(
> +				i915,
> +				CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID);
> +		igt_subtest("reject-modify-context-protection-off-1")
> +			test_create_protected_context(
> +				i915, CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON);
> +		igt_subtest("reject-modify-context-protection-off-2")
> +			test_create_protected_context(
> +				i915, CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF);
> +		igt_subtest("reject-modify-context-protection-off-3")
> +			test_create_protected_context(
> +				i915,
> +				CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID);
> +	}
> +
> +	igt_fixture {
> +		close(i915);
> +	}
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 825e0183..e7144039 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -189,6 +189,7 @@ i915_progs = [
>  	'gem_pread_after_blit',
>  	'gem_pwrite',
>  	'gem_pwrite_snooped',
> +	'gem_pxp',
>  	'gem_read_read_speed',
>  	'gem_readwrite',
>  	'gem_reg_read',
> -- 
> 2.25.1
> 
> _______________________________________________
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v2 01/15] Sync i915_drm.h UAPI for PXP

[Rodrigo Vivi]

On Wed, Mar 24, 2021 at 10:45:35PM -0700, Alan Previn wrote:
> Sync i915_drm.h UAPI for PXP
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  include/drm-uapi/i915_drm.h | 94 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 93 insertions(+), 1 deletion(-)
> 
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index bf9ea471..c6dd8b58 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
>  #define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
>  #define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
>  #define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
>  #define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
>  #define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
>  #define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> @@ -729,6 +730,27 @@ struct drm_i915_gem_create {
>  	__u32 pad;
>  };
>  
> +struct drm_i915_gem_create_ext {
> +	/**
> +	 * Requested size for the object.
> +	 *
> +	 * The (page-aligned) allocated size for the object will be returned.
> +	 */
> +	__u64 size;
> +	/**
> +	 * Returned handle for the object.
> +	 *
> +	 * Object handles are nonzero.
> +	 */
> +	__u32 handle;
> +	__u32 pad;
> +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
> +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
> +	(-(I915_GEM_CREATE_EXT_SETPARAM << 1))
> +	__u64 extensions;
> +
> +};
> +
>  struct drm_i915_gem_pread {
>  	/** Handle for the object being read. */
>  	__u32 handle;
> @@ -1694,11 +1716,76 @@ struct drm_i915_gem_context_param {
>   * Default is 16 KiB.
>   */
>  #define I915_CONTEXT_PARAM_RINGSIZE	0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * Enable usage of protected content with the context. This flag can only be
> + * set at context creation time and, when set to true, must be preceded by
> + * an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE to false. This flag
> + * can't be set to true in conjunction with setting the
> + * I915_CONTEXT_PARAM_BANNABLE flag to false.
> + *
> + * Given the numerous restriction on this flag, there are several unique
> + * failure cases:
> + *
> + * -ENODEV: feature not available
> + * -EEXIST: trying to modify an existing context
> + * -EPERM: trying to mark a recoverable or not bannable context as protected
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
>  /* Must be kept compact -- no holes and well documented */
>  
>  	__u64 value;
>  };
>  
> +struct drm_i915_gem_object_param {
> +	/* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
> +	__u32 handle;
> +
> +	/* Data pointer size */
> +	__u32 size;
> +
> +/*
> + * I915_OBJECT_PARAM:
> + *
> + * Select object namespace for the param.
> + */
> +#define I915_OBJECT_PARAM  (1ull << 32)
> +
> +/*
> + * I915_OBJECT_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true, buffer contents is expected to be protected by PXP
> + * encryption and requires decryption for scan out and processing. This is
> + * only possible on platforms that have PXP enabled, on all other scenarios
> + * setting this flag will cause the ioctl to fail and return -ENODEV.
> + *
> + * Protected buffers can only be used with contexts created using the
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. The buffer contents are
> + * considered invalid after a PXP session teardown.
> + *
> + * Given the restriction above, the following errors are possible when
> + * submitting a protected object in an execbuf call:
> + *
> + * -ENODEV: PXP session not currently active
> + * -EIO: buffer has become invalid after a teardown event
> + * -EPERM: buffer submitted using a context not marked as protected
> + */
> +#define I915_OBJECT_PARAM_PROTECTED_CONTENT  0x0
> +/* Must be kept compact -- no holes and well documented */
> +
> +	__u64 param;
> +
> +	/* Data value or pointer */
> +	__u64 data;
> +};
> +
> +struct drm_i915_gem_create_ext_setparam {
> +	struct i915_user_extension base;
> +	struct drm_i915_gem_object_param param;
> +};
> +
>  /**
>   * Context SSEU programming
>   *
> @@ -1924,6 +2011,7 @@ struct drm_i915_reg_read {
>  struct drm_i915_reset_stats {
>  	__u32 ctx_id;
>  	__u32 flags;
> +#define I915_CONTEXT_INVALIDATED 0x1
>  
>  	/* All resets since boot/module reload, for all contexts */
>  	__u32 reset_count;
> @@ -2093,7 +2181,7 @@ struct drm_i915_perf_open_param {
>   * Change metrics_set captured by a stream.
>   *
>   * If the stream is bound to a specific context, the configuration change
> - * will performed __inline__ with that context such that it takes effect before
> + * will performed inline with that context such that it takes effect before
>   * the next execbuf submission.
>   *
>   * Returns the previously bound metrics set id, or a negative error code.
> @@ -2376,6 +2464,10 @@ struct drm_i915_query_perf_config {
>  	__u8 data[];
>  };
>  
> +
> +/* ID of the protected content session managed by i915 when PXP is active */
> +#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> -- 
> 2.25.1
> 
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v2 03/15] Perform a regular 3d copy as a control checkpoint

[Rodrigo Vivi]

On Wed, Mar 24, 2021 at 10:45:37PM -0700, Alan Previn wrote:
> As a control checkpoint, allocate buffers to be used
> as texture and render target in the 3d engine for a
> regular src to dest copy blit and verify buffer pixels.

the content of the patch is great. only a few bikesheding on the style

> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  tests/i915/gem_pxp.c | 173 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 173 insertions(+)
> 
> diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> index 40a817b2..7071cd0e 100644
> --- a/tests/i915/gem_pxp.c
> +++ b/tests/i915/gem_pxp.c
> @@ -28,6 +28,11 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
>  #define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
>  #define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
>  
> +/* test-configs for protected rendering operations */
> +#define COPY3D_BASELINE_SRC_TO_DST 1
> +#define COPY3D_PROTECTED_SRC_TO_PROTDST 2
> +#define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
> +
>  static bool is_pxp_hw_supported(int i915)
>  {
>  	uint32_t gen;
> @@ -333,10 +338,164 @@ static void test_create_protected_context(int i915, uint32_t test_cfg)
>  	}
>  }
>  
> +static void fill_bo_content(int i915, uint32_t bo,
> +	uint32_t size, uint32_t initcolor)
> +{
> +	uint32_t *ptr, *ptrtmp;
> +	int loop = 0;
> +
> +	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_WRITE);
> +	ptrtmp = ptr;
> +
> +	/* read and count all dword matches till size */
> +	while (loop++ < (size/4)) {
> +		*ptrtmp = initcolor;
> +		++ptrtmp;
> +	}
> +
> +	igt_assert(gem_munmap(ptr, size) == 0);
> +}
> +
> +#define COMPARE_COLOR_READIBLE     1
> +#define COMPARE_COLOR_UNREADIBLE   2
> +#define COMPARE_N_PIXELS_VERBOSELY 0
> +static void assert_bo_content_check(int i915, uint32_t bo,
> +	int compare_op, uint32_t size, uint32_t color)

not just here, but everywhere, the chosen point for line break and
the indentation after it look strange to my ODC

static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
       	    			    uint32_t size, uint32_t color)


> +{
> +	uint32_t *ptr, *ptrtmp;
> +	int loop = 0, num_matches = 0;
> +	uint32_t value;
> +	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
> +
> +	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
> +	ptrtmp = ptr;
> +
> +	if (COMPARE_N_PIXELS_VERBOSELY) {
> +		igt_info("--------->>>\n");
> +		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
> +			value = *ptrtmp;
> +			igt_info("Color read = 0x%08x ", value);
> +			igt_info("expected %c= 0x%08x)\n",
> +				op_readible?'=':'!', color);
> +			++ptrtmp;
> +			++loop;
> +		}
> +		igt_info("<<<---------\n");
> +		ptrtmp = ptr;
> +		loop = 0;
> +	}
> +
> +	/*count all pixels for matches */
          ^space


> +	while (loop++ < (size/4)) {
> +		value = *ptrtmp;
> +		if (value == color)
> +			++num_matches;
> +		++ptrtmp;
> +	}
> +
> +	if (op_readible)
> +		igt_assert_eq(num_matches, (size/4));
> +	else
> +		igt_assert_eq(num_matches, 0);
> +
> +	igt_assert(gem_munmap(ptr, size) == 0);
> +}
> +
> +static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
> +	uint32_t size, uint32_t init_color)
> +{
> +	uint32_t bo;
> +
> +	bo = create_protected_bo(i915, size,
> +		protected, protected, 0);

(again not just here, but picking another random example on where line
break is not needed)

	bo = create_protected_bo(i915, size, protected, protected, 0);


> +	igt_assert(bo);
> +	fill_bo_content(i915, bo, size, init_color);
> +	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
> +		size, init_color);

(or this, where it could align the arguments)

	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
				size, init_color);

> +
> +	return bo;
> +}
> +
> +/* Rendering tests surface attributes, keep it simple:

/*
 * Rendering...

> + * page aligned width==stride, thus, and size
> + */
> +#define TSTSURF_WIDTH       1024
> +#define TSTSURF_HEIGHT      128
> +#define TSTSURF_BYTESPP     4
> +#define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
> +#define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
> +#define TSTSURF_FILLCOLOR1  0xfaceface
> +#define TSTSURF_INITCOLOR1  0x12341234
> +
> +static void test_render_protected_buffer(int i915, uint32_t test_cfg)
> +{
> +	uint32_t ctx, srcbo, dstbo;
> +	struct intel_buf *srcbuf, *dstbuf;
> +	struct buf_ops *bops;
> +	struct intel_bb *ibb;
> +	uint32_t devid;
> +
> +	devid = intel_get_drm_devid(i915);
> +	igt_assert(devid);
> +
> +	bops = buf_ops_create(i915);
> +	igt_assert(bops);
> +
> +	switch (test_cfg) {
> +	case COPY3D_BASELINE_SRC_TO_DST:
> +		/* Perform a regular 3d copy as a control checkpoint */
> +		ctx = create_protected_ctx(i915, false, false,
> +			false, false, 0);
> +		assert_ctx_protected_param(i915, ctx, false);
> +
> +		dstbo = alloc_and_fill_dest_buff(i915, false,
> +				TSTSURF_SIZE, TSTSURF_INITCOLOR1);
> +		dstbuf = intel_buf_create_using_handle(bops, dstbo,
> +				TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +
> +		srcbo = alloc_and_fill_dest_buff(i915, false,
> +				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> +		srcbuf = intel_buf_create_using_handle(bops, srcbo,
> +				TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
> +
> +		ibb = intel_bb_create_with_context(i915, ctx, 4096);
> +		igt_assert(ibb);
> +
> +		gen12_render_copyfunc(ibb,
> +			srcbuf, 0, 0,
> +			TSTSURF_WIDTH, TSTSURF_HEIGHT,
> +			dstbuf, 0, 0);
> +		gem_sync(i915, dstbo);
> +
> +		assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
> +			TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> +
> +		intel_bb_destroy(ibb);
> +		intel_buf_destroy(srcbuf);
> +		gem_close(i915, srcbo);
> +		intel_buf_destroy(dstbuf);
> +		gem_close(i915, dstbo);
> +		gem_context_destroy(i915, ctx);
> +		break;
> +
> +	default:
> +		igt_info("Skipping unknown render test_cfg = %d\n",
> +			test_cfg);
> +		break;
> +	}
> +
> +	buf_ops_destroy(bops);
> +}
> +
> +
>  igt_main
>  {
>  	int i915 = -1;
>  	bool pxp_supported = false;
> +	igt_render_copyfunc_t rendercopy = NULL;
> +	uint32_t devid = 0;
>  
>  	igt_fixture
>  	{
> @@ -403,6 +562,20 @@ igt_main
>  				i915,
>  				CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID);
>  	}
> +	igt_subtest_group {
> +		igt_fixture {
> +			igt_require(pxp_supported);
> +			devid = intel_get_drm_devid(i915);
> +			igt_assert(devid);
> +			rendercopy = igt_get_render_copyfunc(devid);
> +			igt_require(rendercopy);
> +		}
> +
> +		igt_describe("Verify protected render operations:");
> +		igt_subtest("regular-baseline-src-copy-readible")
> +			test_render_protected_buffer(i915,
> +				COPY3D_BASELINE_SRC_TO_DST);
> +	}
>  
>  	igt_fixture {
>  		close(i915);
> -- 
> 2.25.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v2 01/15] Sync i915_drm.h UAPI for PXP

[Petri Latvala]

On Wed, Mar 24, 2021 at 10:45:35PM -0700, Alan Previn wrote:
> Sync i915_drm.h UAPI for PXP
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  include/drm-uapi/i915_drm.h | 94 ++++++++++++++++++++++++++++++++++++-

State in the commit message which kernel commit this is copied from.

-- 
Petri Latvala
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Re: [igt-dev] [PATCH i-g-t v2 05/15] Add MI_SET_APPID instruction definition

[Rodrigo Vivi]

On Wed, Mar 24, 2021 at 10:45:39PM -0700, Alan Previn wrote:
> Add MI_SET_APPID instruction and param definitions
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  lib/intel_reg.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index ac1fc6cb..553f4839 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
>  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
>  
> +#define MI_SET_APPID                    (0x0e<<23)

The trend is to add the new ones with space (0x0E << 23)

> +#define APPID_CTXSAVE_INHIBIT           (1<<8)
> +#define APPID_CTXREST_INHIBIT           (1<<9)
> +#define DISPLAY_APPTYPE                 (0)
> +#define TRANSCODE_APPTYPE               (1)
> +#define APPTYPE(n)                      ((n & 0x1)<<7)

please remove the useless & 0x1

with that

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> +#define APPID(n)                        (n & 0x7f)
> +
> +
>  /* Dword 0 */
>  #define MI_VERTEX_BUFFER		(0x17<<23)
>  #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
> -- 
> 2.25.1
> 
> _______________________________________________
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v2 01/15] Sync i915_drm.h UAPI for PXP

[Teres Alexis, Alan Previn]

On Wed, 2021-04-21 at 13:33 +0300, Petri Latvala wrote:
> On Wed, Mar 24, 2021 at 10:45:35PM -0700, Alan Previn wrote:
> > Sync i915_drm.h UAPI for PXP
> > 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  include/drm-uapi/i915_drm.h | 94
> > ++++++++++++++++++++++++++++++++++++-
> 
> State in the commit message which kernel commit this is copied from.
> 
Will do - thanks.
...alan
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Re: [igt-dev] [PATCH i-g-t v2 03/15] Perform a regular 3d copy as a control checkpoint

[Teres Alexis, Alan Previn]

Thanks Rodrigo, will make those changes.

...alan

On Wed, 2021-04-21 at 06:28 -0400, Rodrigo Vivi wrote:
> On Wed, Mar 24, 2021 at 10:45:37PM -0700, Alan Previn wrote:
> > As a control checkpoint, allocate buffers to be used
> > as texture and render target in the 3d engine for a
> > regular src to dest copy blit and verify buffer pixels.
> 
> the content of the patch is great. only a few bikesheding on the
> style
> 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  tests/i915/gem_pxp.c | 173
> > +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 173 insertions(+)
> > 
> > diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> > index 40a817b2..7071cd0e 100644
> > --- a/tests/i915/gem_pxp.c
> > +++ b/tests/i915/gem_pxp.c
> > @@ -28,6 +28,11 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe
> > Path), which is the component "
> >  #define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
> >  #define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
> >  
> > +/* test-configs for protected rendering operations */
> > +#define COPY3D_BASELINE_SRC_TO_DST 1
> > +#define COPY3D_PROTECTED_SRC_TO_PROTDST 2
> > +#define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
> > +
> >  static bool is_pxp_hw_supported(int i915)
> >  {
> >  	uint32_t gen;
> > @@ -333,10 +338,164 @@ static void
> > test_create_protected_context(int i915, uint32_t test_cfg)
> >  	}
> >  }
> >  
> > +static void fill_bo_content(int i915, uint32_t bo,
> > +	uint32_t size, uint32_t initcolor)
> > +{
> > +	uint32_t *ptr, *ptrtmp;
> > +	int loop = 0;
> > +
> > +	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_WRITE);
> > +	ptrtmp = ptr;
> > +
> > +	/* read and count all dword matches till size */
> > +	while (loop++ < (size/4)) {
> > +		*ptrtmp = initcolor;
> > +		++ptrtmp;
> > +	}
> > +
> > +	igt_assert(gem_munmap(ptr, size) == 0);
> > +}
> > +
> > +#define COMPARE_COLOR_READIBLE     1
> > +#define COMPARE_COLOR_UNREADIBLE   2
> > +#define COMPARE_N_PIXELS_VERBOSELY 0
> > +static void assert_bo_content_check(int i915, uint32_t bo,
> > +	int compare_op, uint32_t size, uint32_t color)
> 
> not just here, but everywhere, the chosen point for line break and
> the indentation after it look strange to my ODC
> 
> static void assert_bo_content_check(int i915, uint32_t bo, int
> compare_op,
>        	    			    uint32_t size, uint32_t
> color)
> 
> 
> > +{
> > +	uint32_t *ptr, *ptrtmp;
> > +	int loop = 0, num_matches = 0;
> > +	uint32_t value;
> > +	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
> > +
> > +	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
> > +	ptrtmp = ptr;
> > +
> > +	if (COMPARE_N_PIXELS_VERBOSELY) {
> > +		igt_info("--------->>>\n");
> > +		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop <
> > (size/4)) {
> > +			value = *ptrtmp;
> > +			igt_info("Color read = 0x%08x ", value);
> > +			igt_info("expected %c= 0x%08x)\n",
> > +				op_readible?'=':'!', color);
> > +			++ptrtmp;
> > +			++loop;
> > +		}
> > +		igt_info("<<<---------\n");
> > +		ptrtmp = ptr;
> > +		loop = 0;
> > +	}
> > +
> > +	/*count all pixels for matches */
>           ^space
> 
> 
> > +	while (loop++ < (size/4)) {
> > +		value = *ptrtmp;
> > +		if (value == color)
> > +			++num_matches;
> > +		++ptrtmp;
> > +	}
> > +
> > +	if (op_readible)
> > +		igt_assert_eq(num_matches, (size/4));
> > +	else
> > +		igt_assert_eq(num_matches, 0);
> > +
> > +	igt_assert(gem_munmap(ptr, size) == 0);
> > +}
> > +
> > +static uint32_t alloc_and_fill_dest_buff(int i915, bool protected,
> > +	uint32_t size, uint32_t init_color)
> > +{
> > +	uint32_t bo;
> > +
> > +	bo = create_protected_bo(i915, size,
> > +		protected, protected, 0);
> 
> (again not just here, but picking another random example on where
> line
> break is not needed)
> 
> 	bo = create_protected_bo(i915, size, protected, protected, 0);
> 
> 
> > +	igt_assert(bo);
> > +	fill_bo_content(i915, bo, size, init_color);
> > +	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
> > +		size, init_color);
> 
> (or this, where it could align the arguments)
> 
> 	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
> 				size, init_color);
> 
> > +
> > +	return bo;
> > +}
> > +
> > +/* Rendering tests surface attributes, keep it simple:
> 
> /*
>  * Rendering...
> 
> > + * page aligned width==stride, thus, and size
> > + */
> > +#define TSTSURF_WIDTH       1024
> > +#define TSTSURF_HEIGHT      128
> > +#define TSTSURF_BYTESPP     4
> > +#define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
> > +#define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
> > +#define TSTSURF_FILLCOLOR1  0xfaceface
> > +#define TSTSURF_INITCOLOR1  0x12341234
> > +
> > +static void test_render_protected_buffer(int i915, uint32_t
> > test_cfg)
> > +{
> > +	uint32_t ctx, srcbo, dstbo;
> > +	struct intel_buf *srcbuf, *dstbuf;
> > +	struct buf_ops *bops;
> > +	struct intel_bb *ibb;
> > +	uint32_t devid;
> > +
> > +	devid = intel_get_drm_devid(i915);
> > +	igt_assert(devid);
> > +
> > +	bops = buf_ops_create(i915);
> > +	igt_assert(bops);
> > +
> > +	switch (test_cfg) {
> > +	case COPY3D_BASELINE_SRC_TO_DST:
> > +		/* Perform a regular 3d copy as a control checkpoint */
> > +		ctx = create_protected_ctx(i915, false, false,
> > +			false, false, 0);
> > +		assert_ctx_protected_param(i915, ctx, false);
> > +
> > +		dstbo = alloc_and_fill_dest_buff(i915, false,
> > +				TSTSURF_SIZE, TSTSURF_INITCOLOR1);
> > +		dstbuf = intel_buf_create_using_handle(bops, dstbo,
> > +				TSTSURF_WIDTH, TSTSURF_HEIGHT,
> > +				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE,
> > 0);
> > +
> > +		srcbo = alloc_and_fill_dest_buff(i915, false,
> > +				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> > +		srcbuf = intel_buf_create_using_handle(bops, srcbo,
> > +				TSTSURF_WIDTH, TSTSURF_HEIGHT,
> > +				TSTSURF_BYTESPP*8, 0, I915_TILING_NONE,
> > 0);
> > +
> > +		ibb = intel_bb_create_with_context(i915, ctx, 4096);
> > +		igt_assert(ibb);
> > +
> > +		gen12_render_copyfunc(ibb,
> > +			srcbuf, 0, 0,
> > +			TSTSURF_WIDTH, TSTSURF_HEIGHT,
> > +			dstbuf, 0, 0);
> > +		gem_sync(i915, dstbo);
> > +
> > +		assert_bo_content_check(i915, dstbo,
> > COMPARE_COLOR_READIBLE,
> > +			TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
> > +
> > +		intel_bb_destroy(ibb);
> > +		intel_buf_destroy(srcbuf);
> > +		gem_close(i915, srcbo);
> > +		intel_buf_destroy(dstbuf);
> > +		gem_close(i915, dstbo);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	default:
> > +		igt_info("Skipping unknown render test_cfg = %d\n",
> > +			test_cfg);
> > +		break;
> > +	}
> > +
> > +	buf_ops_destroy(bops);
> > +}
> > +
> > +
> >  igt_main
> >  {
> >  	int i915 = -1;
> >  	bool pxp_supported = false;
> > +	igt_render_copyfunc_t rendercopy = NULL;
> > +	uint32_t devid = 0;
> >  
> >  	igt_fixture
> >  	{
> > @@ -403,6 +562,20 @@ igt_main
> >  				i915,
> >  				CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVA
> > LID);
> >  	}
> > +	igt_subtest_group {
> > +		igt_fixture {
> > +			igt_require(pxp_supported);
> > +			devid = intel_get_drm_devid(i915);
> > +			igt_assert(devid);
> > +			rendercopy = igt_get_render_copyfunc(devid);
> > +			igt_require(rendercopy);
> > +		}
> > +
> > +		igt_describe("Verify protected render operations:");
> > +		igt_subtest("regular-baseline-src-copy-readible")
> > +			test_render_protected_buffer(i915,
> > +				COPY3D_BASELINE_SRC_TO_DST);
> > +	}
> >  
> >  	igt_fixture {
> >  		close(i915);
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v2 05/15] Add MI_SET_APPID instruction definition

[Teres Alexis, Alan Previn]

Thanks - will fix those up.
...alan

On Wed, 2021-04-21 at 08:30 -0400, Rodrigo Vivi wrote:
> On Wed, Mar 24, 2021 at 10:45:39PM -0700, Alan Previn wrote:
> > Add MI_SET_APPID instruction and param definitions
> > 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  lib/intel_reg.h | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> > index ac1fc6cb..553f4839 100644
> > --- a/lib/intel_reg.h
> > +++ b/lib/intel_reg.h
> > @@ -2546,6 +2546,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> > SOFTWARE.
> >  #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
> >  #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
> >  
> > +#define MI_SET_APPID                    (0x0e<<23)
> 
> The trend is to add the new ones with space (0x0E << 23)
> 
> > +#define APPID_CTXSAVE_INHIBIT           (1<<8)
> > +#define APPID_CTXREST_INHIBIT           (1<<9)
> > +#define DISPLAY_APPTYPE                 (0)
> > +#define TRANSCODE_APPTYPE               (1)
> > +#define APPTYPE(n)                      ((n & 0x1)<<7)
> 
> please remove the useless & 0x1
> 
> with that
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> 
> 
> > +#define APPID(n)                        (n & 0x7f)
> > +
> > +
> >  /* Dword 0 */
> >  #define MI_VERTEX_BUFFER		(0x17<<23)
> >  #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t v2 02/15] Add basic PXP testing of buffer and context alloc

[Teres Alexis, Alan Previn]

Thanks Rodrigo - I will fix the buffer allocation as per your
suggestion. Apologies on the delay as some internal alignment was also
happening about future user-space needs.

...alan 

On Wed, 2021-04-21 at 06:09 -0400, Rodrigo Vivi wrote:
> On Wed, Mar 24, 2021 at 10:45:36PM -0700, Alan Previn wrote:
> > Test PXP capability support as well as the allocation of protected
> > buffers and protected contexts.
> > 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> > ---
> >  tests/Makefile.sources |   3 +
> >  tests/i915/gem_pxp.c   | 410
> > +++++++++++++++++++++++++++++++++++++++++
> >  tests/meson.build      |   1 +
> >  3 files changed, 414 insertions(+)
> >  create mode 100644 tests/i915/gem_pxp.c
> > 
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 4f24fb3a..05952066 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -370,6 +370,9 @@ gem_pwrite_SOURCES = i915/gem_pwrite.c
> >  TESTS_progs += gem_pwrite_snooped
> >  gem_pwrite_snooped_SOURCES = i915/gem_pwrite_snooped.c
> >  
> > +TESTS_progs += gem_pxp
> > +gem_pxp_SOURCES = i915/gem_pxp.c
> > +
> >  TESTS_progs += gem_read_read_speed
> >  gem_read_read_speed_SOURCES = i915/gem_read_read_speed.c
> >  
> > diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
> > new file mode 100644
> > index 00000000..40a817b2
> > --- /dev/null
> > +++ b/tests/i915/gem_pxp.c
> > @@ -0,0 +1,410 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2021 Intel Corporation
> > + */
> > +
> > +#include <sys/ioctl.h>
> > +
> > +#include "igt.h"
> > +#include "i915/gem.h"
> > +
> > +IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the
> > component "
> > +			"that allows the handling of protected content
> > through "
> > +			"the arbitration of hardware protected
> > sessions.");
> > +
> > +/* test-configs for protected buffer creation*/
> 
>                                                 ^ missing space
> 
> > +#define BO_ALLOC_NO_HW_SUPPORT 1
> > +#define BO_ALLOC_PROTECT_ON 2
> > +#define BO_ALLOC_PROTECT_OFF 3
> > +
> > +/* test-configs for protected context creation*/
> 
>                                                  ^ missing space
> 
> > +#define CTX_ALLOC_NO_HW_SUPPORT 1
> > +#define CTX_ALLOC_RECOVER_OFF_PROTECT_OFF 2
> > +#define CTX_ALLOC_RECOVER_OFF_PROTECT_ON 3
> > +#define CTX_ALLOC_RECOVER_ON_PROTECT_OFF 4
> > +#define CTX_ALLOC_RECOVER_ON_PROTECT_ON 5
> > +#define CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON 6
> > +#define CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF 7
> > +#define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
> > +#define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
> > +
> > +static bool is_pxp_hw_supported(int i915)
> > +{
> > +	uint32_t gen;
> > +
> > +	gen = intel_gen(intel_get_drm_devid(i915));
> > +	if (!gen) {
> > +		igt_info("No device info found - assume no PXP
> > support.\n");
> > +		return false;
> > +	}
> > +
> > +	if (gen >= 12)
> > +		return true;
> > +
> > +	return false;
> > +}
> > +
> > +static uint32_t create_protected_bo(int i915, uint32_t size,
> > +				    bool with_protected_param,
> > +				    bool protected_is_true, int
> > expected_return)
> 
> why do you need both with_protected_param and protected_is_true?
> I searched the series and it looks like they always match, so why not
> simply
> 
> static uint32_t create_bo(int i915, uint32_t size, bool protected,
> int return_assert)
> 
> ?
> 
> > +{
> > +	int ret;
> > +
> > +	struct drm_i915_gem_object_param protected_param = {
> > +		.param = I915_OBJECT_PARAM |
> > I915_OBJECT_PARAM_PROTECTED_CONTENT,
> > +		.data = 0,
> > +	};
> > +
> > +	struct drm_i915_gem_create_ext_setparam setparam_protected = {
> > +		.base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
> > +		.param = protected_param,
> > +	};
> > +
> > +	struct drm_i915_gem_create_ext create_ext = {
> > +		.size = size,
> > +		.extensions = (uintptr_t)&setparam_protected,
> > +	};
> > +
> > +	if (!with_protected_param) {
> > +		create_ext.extensions = 0;
> > +	} else {
> > +		if (protected_is_true) {
> > +			protected_param.data = 1;
> > +			setparam_protected.param = protected_param;
> > +		} else {
> > +			protected_param.data = 0;
> > +			setparam_protected.param = protected_param;
> > +		}
> > +	}
> > +
> > +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
> > +	igt_assert_eq(ret, expected_return);
> > +
> > +	return create_ext.handle;
> > +}
> > +
> > +static void test_create_protected_buffer(int i915, uint32_t
> > test_cfg)
> > +{
> > +	uint32_t bo;
> > +
> > +	switch (test_cfg) {
> > +	case BO_ALLOC_NO_HW_SUPPORT:
> > +		bo = create_protected_bo(i915, 4096, false, false, 0);
> > +		gem_close(i915, bo);
> > +		bo = create_protected_bo(i915, 4096, true, true,
> > -ENODEV);
> > +		igt_assert_eq(bo, 0);
> > +		break;
> > +
> > +	case BO_ALLOC_PROTECT_OFF:
> > +		bo = create_protected_bo(i915, 4096, false, false, 0);
> > +		gem_close(i915, bo);
> > +		break;
> > +
> > +	case BO_ALLOC_PROTECT_ON:
> > +		bo = create_protected_bo(i915, 4096, true, true, 0);
> > +		gem_close(i915, bo);
> > +		break;
> > +
> > +	default:
> > +		igt_info("Skipping unknown buffer test_cfg = %d\n",
> > test_cfg);
> > +		break;
> > +	}
> > +}
> > +
> > +static int create_ext_ioctl(int i915,
> > +			    struct drm_i915_gem_context_create_ext
> > *arg)
> > +{
> > +	int err;
> > +
> > +	err = 0;
> > +	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT,
> > arg)) {
> > +		err = -errno;
> > +		igt_assume(err);
> > +	}
> > +
> > +	errno = 0;
> > +	return err;
> > +}
> > +
> > +static uint32_t create_protected_ctx(int i915, bool
> > with_protected_param,
> > +				     bool protected_is_true,
> > +				     bool with_recoverable_param,
> > +				     bool recoverable_is_true,
> > +				     int expected_return)
> > +{
> > +	int ret;
> > +
> > +	struct drm_i915_gem_context_create_ext_setparam p_prot = {
> > +		.base = {
> > +			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> > +			.next_extension = 0,
> > +		},
> > +		.param = {
> > +			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
> > +			.value = 0,
> > +		}
> > +	};
> > +	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
> > +		.base = {
> > +			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> > +			.next_extension = 0,
> > +		},
> > +		.param = {
> > +			.param = I915_CONTEXT_PARAM_RECOVERABLE,
> > +			.value = 0,
> > +		}
> > +	};
> > +	struct drm_i915_gem_context_create_ext create = {
> > +		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> > +		.extensions = 0,
> > +	};
> > +
> > +	p_prot.param.value = protected_is_true;
> > +	p_norecover.param.value = recoverable_is_true;
> > +
> > +	if (with_protected_param && with_recoverable_param) {
> > +		create.extensions =
> > to_user_pointer(&(p_norecover.base));
> > +		p_norecover.base.next_extension =
> > +			to_user_pointer(&(p_prot.base));
> > +	} else if (!with_protected_param && with_recoverable_param) {
> > +		create.extensions =
> > to_user_pointer(&(p_norecover.base));
> > +		p_norecover.base.next_extension = 0;
> > +	} else if (with_protected_param && !with_recoverable_param) {
> > +		create.extensions = to_user_pointer(&(p_prot.base));
> > +		p_prot.base.next_extension = 0;
> > +	} else if (!with_protected_param && !with_recoverable_param) {
> > +		create.flags = 0;
> > +	}
> > +
> > +	ret = create_ext_ioctl(i915, &create);
> > +	igt_assert_eq(ret, expected_return);
> > +
> > +	return create.ctx_id;
> > +}
> > +
> > +#define CHANGE_PARAM_PROTECTED 0x0001
> > +#define CHANGE_PARAM_RECOVERY 0x0002
> > +static void modify_ctx_protected_param(int i915, uint32_t ctx_id,
> > +				       uint32_t change_param_mask,
> > +				       bool param_value, int
> > expected_return)
> > +{
> > +	int ret;
> > +
> > +	struct drm_i915_gem_context_param ctx_param = {
> > +		.ctx_id = ctx_id,
> > +		.param = 0,
> > +		.value = 0,
> > +	};
> > +
> > +	if (change_param_mask == CHANGE_PARAM_PROTECTED) {
> > +		ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
> > +		ctx_param.value = (int)param_value;
> > +	} else if (change_param_mask == CHANGE_PARAM_RECOVERY) {
> > +		ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
> > +		ctx_param.value = (int)param_value;
> > +	} else {
> > +		return;
> > +	}
> > +
> > +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
> > &ctx_param);
> > +
> > +	igt_assert_eq(ret, expected_return);
> > +}
> > +
> > +static void assert_ctx_protected_param(int i915, uint32_t ctx_id,
> > +				       bool is_protected)
> > +{
> > +	int ret;
> > +
> > +	struct drm_i915_gem_context_param ctx_param = {
> > +		.ctx_id = ctx_id,
> > +		.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
> > +	};
> > +
> > +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM,
> > &ctx_param);
> > +	igt_assert_eq(ret, 0);
> > +	igt_assert_eq(ctx_param.value, (int)is_protected);
> > +}
> > +
> > +static void assert_ctx_recovery_param(int i915, uint32_t ctx_id,
> > +				      bool is_recoverable)
> > +{
> > +	int ret;
> > +
> > +	struct drm_i915_gem_context_param ctx_param = {
> > +		.ctx_id = ctx_id,
> > +		.param = I915_CONTEXT_PARAM_RECOVERABLE,
> > +	};
> > +
> > +	ret = ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM,
> > &ctx_param);
> > +	igt_assert_eq(ret, 0);
> > +	igt_assert_eq(ctx_param.value, (int)is_recoverable);
> > +}
> > +
> > +static void test_create_protected_context(int i915, uint32_t
> > test_cfg)
> > +{
> > +	uint32_t ctx;
> > +
> > +	switch (test_cfg) {
> > +	case CTX_ALLOC_NO_HW_SUPPORT:
> > +		ctx = create_protected_ctx(i915, true, true, true,
> > false,
> > +					   -ENODEV);
> > +		igt_assert_eq(ctx, 0);
> > +	case CTX_ALLOC_RECOVER_OFF_PROTECT_OFF:
> > +		ctx = create_protected_ctx(i915, true, false, true,
> > false, 0);
> > +		assert_ctx_protected_param(i915, ctx, false);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	case CTX_ALLOC_RECOVER_OFF_PROTECT_ON:
> > +		ctx = create_protected_ctx(i915, true, true, true,
> > false, 0);
> > +		assert_ctx_protected_param(i915, ctx, true);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	case CTX_ALLOC_RECOVER_ON_PROTECT_OFF:
> > +		ctx = create_protected_ctx(i915, true, false, true,
> > true, 0);
> > +		assert_ctx_protected_param(i915, ctx, false);
> > +		assert_ctx_recovery_param(i915, ctx, true);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	case CTX_ALLOC_RECOVER_ON_PROTECT_ON:
> > +		ctx = create_protected_ctx(i915, true, true, true,
> > true,
> > +					   -EPERM);
> > +		igt_assert_eq(ctx, 0);
> > +		ctx = create_protected_ctx(i915, true, true, false,
> > false,
> > +					   -EPERM);
> > +		igt_assert_eq(ctx, 0);
> > +		break;
> > +
> > +	case CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON:
> > +		ctx = create_protected_ctx(i915, true, true, true,
> > false, 0);
> > +		assert_ctx_protected_param(i915, ctx, true);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		modify_ctx_protected_param(i915, ctx,
> > CHANGE_PARAM_RECOVERY,
> > +					   true, -EPERM);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	case CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF:
> > +		ctx = create_protected_ctx(i915, true, true, true,
> > false, 0);
> > +		assert_ctx_protected_param(i915, ctx, true);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		modify_ctx_protected_param(i915, ctx,
> > CHANGE_PARAM_PROTECTED,
> > +					   false, -EPERM);
> > +		assert_ctx_protected_param(i915, ctx, true);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	case CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID:
> > +		ctx = create_protected_ctx(i915, true, true, true,
> > false, 0);
> > +		assert_ctx_protected_param(i915, ctx, true);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		modify_ctx_protected_param(i915, ctx,
> > CHANGE_PARAM_RECOVERY,
> > +					   true, -EPERM);
> > +		modify_ctx_protected_param(i915, ctx,
> > CHANGE_PARAM_PROTECTED,
> > +					   false, -EPERM);
> > +		assert_ctx_protected_param(i915, ctx, true);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	case CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID:
> > +		ctx = create_protected_ctx(i915, false, false, false,
> > false, 0);
> > +		assert_ctx_protected_param(i915, ctx, false);
> > +		assert_ctx_recovery_param(i915, ctx, true);
> > +		modify_ctx_protected_param(i915, ctx,
> > CHANGE_PARAM_RECOVERY,
> > +					   false, 0);
> > +		modify_ctx_protected_param(i915, ctx,
> > CHANGE_PARAM_PROTECTED,
> > +					   true, -EPERM);
> > +		assert_ctx_protected_param(i915, ctx, false);
> > +		assert_ctx_recovery_param(i915, ctx, false);
> > +		gem_context_destroy(i915, ctx);
> > +		break;
> > +
> > +	default:
> > +		igt_info("Skipping unknown context test_cfg = %d\n",
> > test_cfg);
> > +		break;
> > +	}
> > +}
> > +
> > +igt_main
> > +{
> > +	int i915 = -1;
> > +	bool pxp_supported = false;
> > +
> > +	igt_fixture
> > +	{
> > +		i915 = drm_open_driver(DRIVER_INTEL);
> > +		igt_require(i915);
> > +		igt_require_gem(i915);
> > +		pxp_supported = is_pxp_hw_supported(i915);
> > +	}
> > +
> > +	igt_subtest_group {
> > +		igt_fixture {
> > +			igt_require((pxp_supported == 0));
> > +		}
> > +
> > +		igt_describe("Verify protected buffer on unsupported
> > hw:");
> > +		igt_subtest("hw-rejects-pxp-buffer")
> > +			test_create_protected_buffer(i915,
> > +				BO_ALLOC_NO_HW_SUPPORT);
> > +		igt_describe("Verify protected context on unsupported
> > hw:");
> > +		igt_subtest("hw-rejects-pxp-context")
> > +			test_create_protected_context(i915,
> > +				CTX_ALLOC_NO_HW_SUPPORT);
> > +	}
> > +
> > +	igt_subtest_group {
> > +		igt_fixture {
> > +			igt_require(pxp_supported);
> > +		}
> > +
> > +		igt_describe("Verify protected buffer on supported
> > hw:");
> > +		igt_subtest("create-regular-buffer")
> > +			test_create_protected_buffer(i915,
> > +				BO_ALLOC_PROTECT_OFF);
> > +		igt_subtest("create-protected-buffer")
> > +			test_create_protected_buffer(i915,
> > BO_ALLOC_PROTECT_ON);
> > +
> > +		igt_describe("Verify protected context on supported
> > hw:");
> > +		igt_subtest("create-regular-context-1")
> > +			test_create_protected_context(
> > +				i915,
> > CTX_ALLOC_RECOVER_OFF_PROTECT_OFF);
> > +		igt_subtest("create-regular-context-2")
> > +			test_create_protected_context(
> > +				i915,
> > CTX_ALLOC_RECOVER_ON_PROTECT_OFF);
> > +		igt_subtest("fail-invalid-protected-context")
> > +			test_create_protected_context(
> > +				i915, CTX_ALLOC_RECOVER_ON_PROTECT_ON);
> > +		igt_subtest("create-valid-protected-context")
> > +			test_create_protected_context(
> > +				i915,
> > CTX_ALLOC_RECOVER_OFF_PROTECT_ON);
> > +
> > +		igt_describe("Verify protected context integrity:");
> > +		igt_subtest("reject-modify-context-protection-on")
> > +			test_create_protected_context(
> > +				i915,
> > +				CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VA
> > LID);
> > +		igt_subtest("reject-modify-context-protection-off-1")
> > +			test_create_protected_context(
> > +				i915,
> > CTX_MODIFY_PROTECTED_RECOVER_OFF_TO_ON);
> > +		igt_subtest("reject-modify-context-protection-off-2")
> > +			test_create_protected_context(
> > +				i915,
> > CTX_MODIFY_PROTECTED_PROTECT_ON_TO_OFF);
> > +		igt_subtest("reject-modify-context-protection-off-3")
> > +			test_create_protected_context(
> > +				i915,
> > +				CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVA
> > LID);
> > +	}
> > +
> > +	igt_fixture {
> > +		close(i915);
> > +	}
> > +}
> > diff --git a/tests/meson.build b/tests/meson.build
> > index 825e0183..e7144039 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -189,6 +189,7 @@ i915_progs = [
> >  	'gem_pread_after_blit',
> >  	'gem_pwrite',
> >  	'gem_pwrite_snooped',
> > +	'gem_pxp',
> >  	'gem_read_read_speed',
> >  	'gem_readwrite',
> >  	'gem_reg_read',
> > -- 
> > 2.25.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
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