From: Thierry Reding <thierry.reding@gmail.com> To: Vinod Koul <vkoul@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kishon Vijay Abraham I <kishon@ti.com>, Mathias Nyman <mathias.nyman@intel.com>, JC Kuo <jckuo@nvidia.com>, Jon Hunter <jonathanh@nvidia.com>, linux-tegra@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Stephen Boyd <sboyd@kernel.org> Subject: [PATCH v8 02/13] clk: tegra: Don't enable PLLE HW sequencer at init Date: Thu, 25 Mar 2021 17:40:46 +0100 [thread overview] Message-ID: <20210325164057.793954-3-thierry.reding@gmail.com> (raw) In-Reply-To: <20210325164057.793954-1-thierry.reding@gmail.com> From: JC Kuo <jckuo@nvidia.com> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - val = pll_readl_misc(pll); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val = pll_readl(pll->params->aux_reg, pll); - val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags); -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com> To: Vinod Koul <vkoul@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kishon Vijay Abraham I <kishon@ti.com>, Mathias Nyman <mathias.nyman@intel.com>, JC Kuo <jckuo@nvidia.com>, Jon Hunter <jonathanh@nvidia.com>, linux-tegra@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Stephen Boyd <sboyd@kernel.org> Subject: [PATCH v8 02/13] clk: tegra: Don't enable PLLE HW sequencer at init Date: Thu, 25 Mar 2021 17:40:46 +0100 [thread overview] Message-ID: <20210325164057.793954-3-thierry.reding@gmail.com> (raw) In-Reply-To: <20210325164057.793954-1-thierry.reding@gmail.com> From: JC Kuo <jckuo@nvidia.com> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - val = pll_readl_misc(pll); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val = pll_readl(pll->params->aux_reg, pll); - val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags); -- 2.30.2 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2021-03-25 16:41 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-25 16:40 [PATCH v8 00/13] Tegra XHCI controller ELPG support Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-25 16:40 ` [PATCH v8 01/13] clk: tegra: Add PLLE HW power sequencer control Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-25 16:40 ` Thierry Reding [this message] 2021-03-25 16:40 ` [PATCH v8 02/13] clk: tegra: Don't enable PLLE HW sequencer at init Thierry Reding 2021-03-25 16:40 ` [PATCH v8 03/13] phy: tegra: xusb: Move usb3 port init for Tegra210 Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-30 14:12 ` Vinod Koul 2021-03-30 14:12 ` Vinod Koul 2021-03-31 16:32 ` Thierry Reding 2021-03-31 16:32 ` Thierry Reding 2021-04-01 5:15 ` Vinod Koul 2021-04-01 5:15 ` Vinod Koul 2021-03-25 16:40 ` [PATCH v8 04/13] phy: tegra: xusb: Rearrange UPHY init on Tegra210 Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-30 14:20 ` Vinod Koul 2021-03-30 14:20 ` Vinod Koul 2021-03-25 16:40 ` [PATCH v8 05/13] phy: tegra: xusb: Add Tegra210 lane_iddq operation Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-30 14:21 ` Vinod Koul 2021-03-30 14:21 ` Vinod Koul 2021-03-31 16:36 ` Thierry Reding 2021-03-31 16:36 ` Thierry Reding 2021-03-25 16:40 ` [PATCH v8 06/13] phy: tegra: xusb: Add sleepwalk and suspend/resume Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-30 14:23 ` Vinod Koul 2021-03-30 14:23 ` Vinod Koul 2021-03-31 16:38 ` Thierry Reding 2021-03-31 16:38 ` Thierry Reding 2021-03-31 16:45 ` Thierry Reding 2021-03-31 16:45 ` Thierry Reding 2021-03-31 16:52 ` Thierry Reding 2021-03-31 16:52 ` Thierry Reding 2021-03-25 16:40 ` [PATCH v8 07/13] soc/tegra: pmc: Provide USB sleepwalk register map Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-25 16:40 ` [PATCH v8 08/13] dt-bindings: phy: tegra-xusb: Add nvidia,pmc prop Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-25 16:40 ` [PATCH v8 09/13] phy: tegra: xusb: Add wake/sleepwalk for Tegra210 Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-25 20:26 ` Nathan Chancellor 2021-03-25 20:26 ` Nathan Chancellor 2021-03-26 12:44 ` Thierry Reding 2021-03-26 12:44 ` Thierry Reding 2021-04-01 6:45 ` Vinod Koul 2021-04-01 6:45 ` Vinod Koul 2021-04-01 10:44 ` Thierry Reding 2021-04-01 10:44 ` Thierry Reding 2021-04-01 11:05 ` [PATCH v9 " Thierry Reding 2021-04-01 11:05 ` Thierry Reding 2021-04-06 5:01 ` Vinod Koul 2021-04-06 5:01 ` Vinod Koul 2021-04-06 13:58 ` Thierry Reding 2021-04-06 13:58 ` Thierry Reding 2021-04-11 14:30 ` Vinod Koul 2021-04-11 14:30 ` Vinod Koul 2021-03-25 16:40 ` [PATCH v8 10/13] phy: tegra: xusb: Tegra210 host mode VBUS control Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-04-01 6:45 ` Vinod Koul 2021-04-01 6:45 ` Vinod Koul 2021-03-25 16:40 ` [PATCH v8 11/13] phy: tegra: xusb: Add wake/sleepwalk for Tegra186 Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-04-01 6:49 ` Vinod Koul 2021-04-01 6:49 ` Vinod Koul 2021-04-01 11:00 ` Thierry Reding 2021-04-01 11:00 ` Thierry Reding 2021-03-25 16:40 ` [PATCH v8 12/13] usb: host: xhci-tegra: Unlink power domain devices Thierry Reding 2021-03-25 16:40 ` Thierry Reding 2021-03-25 16:40 ` [PATCH v8 13/13] xhci: tegra: Enable ELPG for runtime/system PM Thierry Reding 2021-03-25 16:40 ` Thierry Reding
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