* [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
@ 2021-03-26 11:02 ` Shawn Guo
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2021-03-26 11:02 UTC (permalink / raw)
To: Adrian Hunter, Ulf Hansson
Cc: Haibo Chen, Dong Aisheng, Pengutronix Kernel Team,
NXP Linux Team, linux-mmc, linux-arm-kernel, Shawn Guo
From: Shawn Guo <shawn.guo@linaro.org>
As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some
system design may support SDR50 and DDR50 with 100mhz pin state only
(without 200mhz one). Currently the combined 100/200 MHz pinctrl state
check prevents such system from running SDR50 and DDR50. Separate the
check to support such system design.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index a20459744d21..aa45901325b9 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
* Do not advertise faster UHS modes if there are no
* pinctrl states for 100MHz/200MHz.
*/
- if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
- IS_ERR_OR_NULL(imx_data->pins_200mhz))
- val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
- | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
+ if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
+ val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+ if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
+ val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
@ 2021-03-26 11:02 ` Shawn Guo
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2021-03-26 11:02 UTC (permalink / raw)
To: Adrian Hunter, Ulf Hansson
Cc: Haibo Chen, Dong Aisheng, Pengutronix Kernel Team,
NXP Linux Team, linux-mmc, linux-arm-kernel, Shawn Guo
From: Shawn Guo <shawn.guo@linaro.org>
As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some
system design may support SDR50 and DDR50 with 100mhz pin state only
(without 200mhz one). Currently the combined 100/200 MHz pinctrl state
check prevents such system from running SDR50 and DDR50. Separate the
check to support such system design.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index a20459744d21..aa45901325b9 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
* Do not advertise faster UHS modes if there are no
* pinctrl states for 100MHz/200MHz.
*/
- if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
- IS_ERR_OR_NULL(imx_data->pins_200mhz))
- val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
- | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
+ if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
+ val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+ if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
+ val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
}
}
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
2021-03-26 11:02 ` Shawn Guo
@ 2021-03-29 1:50 ` Bough Chen
-1 siblings, 0 replies; 6+ messages in thread
From: Bough Chen @ 2021-03-29 1:50 UTC (permalink / raw)
To: Shawn Guo, Adrian Hunter, Ulf Hansson
Cc: Aisheng Dong, Pengutronix Kernel Team, dl-linux-imx, linux-mmc,
linux-arm-kernel, Shawn Guo
[-- Attachment #1: Type: text/plain, Size: 2143 bytes --]
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: 2021年3月26日 19:02
> To: Adrian Hunter <adrian.hunter@intel.com>; Ulf Hansson
> <ulf.hansson@linaro.org>
> Cc: Bough Chen <haibo.chen@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>;
> linux-mmc@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Shawn Guo
> <shawn.guo@linaro.org>
> Subject: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states
> check
>
> From: Shawn Guo <shawn.guo@linaro.org>
>
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50 require
> pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some system
> design may support SDR50 and DDR50 with 100mhz pin state only (without
> 200mhz one). Currently the combined 100/200 MHz pinctrl state check
> prevents such system from running SDR50 and DDR50. Separate the check to
> support such system design.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host,
> int reg)
> * Do not advertise faster UHS modes if there are no
> * pinctrl states for 100MHz/200MHz.
> */
> - if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> - IS_ERR_OR_NULL(imx_data->pins_200mhz))
> - val &= ~(SDHCI_SUPPORT_SDR50 |
> SDHCI_SUPPORT_DDR50
> - | SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_HS400);
> + if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> + val &= ~(SDHCI_SUPPORT_SDR50 |
> SDHCI_SUPPORT_DDR50);
> + if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> + val &= ~(SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_HS400);
> }
> }
>
> --
> 2.17.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
@ 2021-03-29 1:50 ` Bough Chen
0 siblings, 0 replies; 6+ messages in thread
From: Bough Chen @ 2021-03-29 1:50 UTC (permalink / raw)
To: Shawn Guo, Adrian Hunter, Ulf Hansson
Cc: Aisheng Dong, Pengutronix Kernel Team, dl-linux-imx, linux-mmc,
linux-arm-kernel, Shawn Guo
[-- Attachment #1.1: Type: text/plain, Size: 2143 bytes --]
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: 2021年3月26日 19:02
> To: Adrian Hunter <adrian.hunter@intel.com>; Ulf Hansson
> <ulf.hansson@linaro.org>
> Cc: Bough Chen <haibo.chen@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>;
> linux-mmc@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Shawn Guo
> <shawn.guo@linaro.org>
> Subject: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states
> check
>
> From: Shawn Guo <shawn.guo@linaro.org>
>
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50 require
> pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some system
> design may support SDR50 and DDR50 with 100mhz pin state only (without
> 200mhz one). Currently the combined 100/200 MHz pinctrl state check
> prevents such system from running SDR50 and DDR50. Separate the check to
> support such system design.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host,
> int reg)
> * Do not advertise faster UHS modes if there are no
> * pinctrl states for 100MHz/200MHz.
> */
> - if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> - IS_ERR_OR_NULL(imx_data->pins_200mhz))
> - val &= ~(SDHCI_SUPPORT_SDR50 |
> SDHCI_SUPPORT_DDR50
> - | SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_HS400);
> + if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> + val &= ~(SDHCI_SUPPORT_SDR50 |
> SDHCI_SUPPORT_DDR50);
> + if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> + val &= ~(SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_HS400);
> }
> }
>
> --
> 2.17.1
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
2021-03-26 11:02 ` Shawn Guo
@ 2021-03-30 10:44 ` Ulf Hansson
-1 siblings, 0 replies; 6+ messages in thread
From: Ulf Hansson @ 2021-03-30 10:44 UTC (permalink / raw)
To: Shawn Guo
Cc: Adrian Hunter, Haibo Chen, Dong Aisheng, Pengutronix Kernel Team,
NXP Linux Team, linux-mmc, Linux ARM, Shawn Guo
On Fri, 26 Mar 2021 at 12:02, Shawn Guo <shawnguo@kernel.org> wrote:
>
> From: Shawn Guo <shawn.guo@linaro.org>
>
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
> require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some
> system design may support SDR50 and DDR50 with 100mhz pin state only
> (without 200mhz one). Currently the combined 100/200 MHz pinctrl state
> check prevents such system from running SDR50 and DDR50. Separate the
> check to support such system design.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
> * Do not advertise faster UHS modes if there are no
> * pinctrl states for 100MHz/200MHz.
> */
> - if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> - IS_ERR_OR_NULL(imx_data->pins_200mhz))
> - val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
> - | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> + if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> + val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
> + if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> + val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> }
> }
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check
@ 2021-03-30 10:44 ` Ulf Hansson
0 siblings, 0 replies; 6+ messages in thread
From: Ulf Hansson @ 2021-03-30 10:44 UTC (permalink / raw)
To: Shawn Guo
Cc: Adrian Hunter, Haibo Chen, Dong Aisheng, Pengutronix Kernel Team,
NXP Linux Team, linux-mmc, Linux ARM, Shawn Guo
On Fri, 26 Mar 2021 at 12:02, Shawn Guo <shawnguo@kernel.org> wrote:
>
> From: Shawn Guo <shawn.guo@linaro.org>
>
> As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
> require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some
> system design may support SDR50 and DDR50 with 100mhz pin state only
> (without 200mhz one). Currently the combined 100/200 MHz pinctrl state
> check prevents such system from running SDR50 and DDR50. Separate the
> check to support such system design.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a20459744d21..aa45901325b9 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
> * Do not advertise faster UHS modes if there are no
> * pinctrl states for 100MHz/200MHz.
> */
> - if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
> - IS_ERR_OR_NULL(imx_data->pins_200mhz))
> - val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
> - | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> + if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
> + val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
> + if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
> + val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
> }
> }
>
> --
> 2.17.1
>
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-30 10:51 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-26 11:02 [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check Shawn Guo
2021-03-26 11:02 ` Shawn Guo
2021-03-29 1:50 ` Bough Chen
2021-03-29 1:50 ` Bough Chen
2021-03-30 10:44 ` Ulf Hansson
2021-03-30 10:44 ` Ulf Hansson
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