[PATCH 00/21] DC Patches March 26, 2021

[PATCH 00/21] DC Patches March 26, 2021

[Anson Jacob]

This patchset brings along following features/fixes:
    - LTTPR improvements
    - Disable MALL when SMU not present
    - Fix bug in HW that causes P-State to hang when DPG is enabled in
      certain conditions
    - Update code path for enabling DPG
    - Update display endpoint control path
    - Add dynamic link encoder selection
    - Fix debugfs MST topology to dump from the root MST node
    - Enable DP DSC Compliance automation for Linux
    - ASSR is enabled only when DPCD is supported and the display
      connected is internal
    - Added kernel trace event to print real-time refresh rate value
      to debug VRR issues

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.58

Aric Cyr (1):
  drm/amd/display: 3.2.129

Chris Park (1):
  drm/amd/display: Disable MALL when SMU not present

Eryk Brol (1):
  drm/amd/display: Fix MST topology debugfs

Jimmy Kizito (2):
  drm/amd/display: Add dynamic link encoder selection.
  drm/amd/display: Update display endpoint control path.

Krunoslav Kovac (1):
  drm/amd/display: Rename fs_params to hdr_tm_params

Leo (Hanghong) Ma (1):
  drm/amd/display: Fix static checker warnings on tracebuff_fb

Qingqing Zhuo (2):
  drm/amd/display: enable DP DSC Compliance automation
  drm/amd/display: add log for automated test

Rodrigo Siqueira (1):
  drm/amd/display: Add refresh rate trace

Stylon Wang (1):
  drm/amd/display: Guard ASSR with internal display flag

Vladimir Stempen (1):
  drm/amd/display: Fix typo for variable name

Wenjing Liu (2):
  drm/amd/display: define mod_hdcp_display_disable_option struct
  drm/amd/display: add mod hdcp interface for supporting encryption
    state query

Wesley Chalmers (6):
  drm/amd/display: BIOS LTTPR Caps Interface
  drm/amd/display: Interface for LTTPR interop
  drm/amd/display: Enumerate LTTPR modes
  drm/amd/display: LTTPR config logic
  drm/amd/display: New path for enabling DPG
  drm/amd/display: Set max TTU on DPG enable

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  14 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |   4 +
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    |   6 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_trace.h   |  19 ++
 drivers/gpu/drm/amd/display/dc/Makefile       |   5 +-
 .../drm/amd/display/dc/bios/bios_parser2.c    | 190 +++++++++++
 .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  |   7 +
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  35 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  16 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 197 +++++++++---
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 303 ++++++++++++++++++
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  24 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   7 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   2 +-
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |   6 +
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  19 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  16 +
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  15 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  10 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  27 ++
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  13 +
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |  86 +++++
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 142 ++++----
 .../amd/display/modules/color/color_gamma.c   |   6 +-
 .../amd/display/modules/color/color_gamma.h   |   4 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |  10 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   |   4 +-
 .../display/modules/hdcp/hdcp1_execution.c    |  37 ++-
 .../display/modules/hdcp/hdcp1_transition.c   |   6 +-
 .../display/modules/hdcp/hdcp2_execution.c    |  10 +-
 .../display/modules/hdcp/hdcp2_transition.c   |  10 +-
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   |  10 +
 .../drm/amd/display/modules/inc/mod_hdcp.h    |  10 +-
 drivers/gpu/drm/amd/include/atomfirmware.h    |  38 ++-
 38 files changed, 1141 insertions(+), 176 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

-- 
2.25.1

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[PATCH 01/21] drm/amd/display: BIOS LTTPR Caps Interface

[Anson Jacob]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
Some platforms will have LTTPR capabilities forced on by VBIOS flags;
the functions added here will access those flags.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../drm/amd/display/dc/bios/bios_parser2.c    | 139 ++++++++++++++++++
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |   3 +
 drivers/gpu/drm/amd/include/atomfirmware.h    |  37 ++++-
 3 files changed, 178 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index b208f06ed514..2ee0c6fc069a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -916,6 +916,143 @@ static enum bp_result bios_parser_get_soc_bb_info(
 	return result;
 }
 
+static enum bp_result get_lttpr_caps_v4_1(
+	struct bios_parser *bp,
+	uint8_t *dce_caps)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
+
+	if (!dce_caps)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
+							DATA_TABLES(dce_info));
+
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+	return result;
+}
+
+static enum bp_result get_lttpr_caps_v4_2(
+	struct bios_parser *bp,
+	uint8_t *dce_caps)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
+
+	if (!dce_caps)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
+							DATA_TABLES(dce_info));
+
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+	return result;
+}
+
+static enum bp_result get_lttpr_caps_v4_3(
+	struct bios_parser *bp,
+	uint8_t *dce_caps)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
+
+	if (!dce_caps)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
+							DATA_TABLES(dce_info));
+
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+	return result;
+}
+
+static enum bp_result get_lttpr_caps_v4_4(
+	struct bios_parser *bp,
+	uint8_t *dce_caps)
+{
+	enum bp_result result = BP_RESULT_OK;
+	struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
+
+	if (!dce_caps)
+		return BP_RESULT_BADINPUT;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_BADBIOSTABLE;
+
+	disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
+							DATA_TABLES(dce_info));
+
+	if (!disp_cntl_tbl)
+		return BP_RESULT_BADBIOSTABLE;
+
+	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+
+	return result;
+}
+
+static enum bp_result bios_parser_get_lttpr_caps(
+	struct dc_bios *dcb,
+	uint8_t *dce_caps)
+{
+	struct bios_parser *bp = BP_FROM_DCB(dcb);
+	enum bp_result result = BP_RESULT_UNSUPPORTED;
+	struct atom_common_table_header *header;
+	struct atom_data_revision tbl_revision;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_UNSUPPORTED;
+
+	header = GET_IMAGE(struct atom_common_table_header,
+						DATA_TABLES(dce_info));
+	get_atom_data_table_revision(header, &tbl_revision);
+	switch (tbl_revision.major) {
+	case 4:
+		switch (tbl_revision.minor) {
+		case 1:
+			result = get_lttpr_caps_v4_1(bp, dce_caps);
+			break;
+		case 2:
+			result = get_lttpr_caps_v4_2(bp, dce_caps);
+			break;
+		case 3:
+			result = get_lttpr_caps_v4_3(bp, dce_caps);
+			break;
+		case 4:
+			result = get_lttpr_caps_v4_4(bp, dce_caps);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+
+	return result;
+}
+
 static enum bp_result get_embedded_panel_info_v2_1(
 		struct bios_parser *bp,
 		struct embedded_panel_info *info)
@@ -2531,6 +2668,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
 	.get_soc_bb_info = bios_parser_get_soc_bb_info,
 
 	.get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
+
+	.get_lttpr_caps = bios_parser_get_lttpr_caps,
 };
 
 static bool bios_parser2_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 86ab8f16f621..1b957c60156b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -150,6 +150,9 @@ struct dc_vbios_funcs {
 			struct dc_bios *dcb,
 			struct graphics_object_id object_id,
 			struct bp_disp_connector_caps_info *info);
+	enum bp_result (*get_lttpr_caps)(
+			struct dc_bios *dcb,
+			uint8_t *dce_caps);
 };
 
 struct bios_registers {
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 58364a8eb1f3..82b3cd89b383 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -981,6 +981,40 @@ struct atom_display_controller_info_v4_2
   uint8_t  reserved3[8];
 };
 
+struct atom_display_controller_info_v4_3
+{
+  struct  atom_common_table_header  table_header;
+  uint32_t display_caps;
+  uint32_t bootup_dispclk_10khz;
+  uint16_t dce_refclk_10khz;
+  uint16_t i2c_engine_refclk_10khz;
+  uint16_t dvi_ss_percentage;       // in unit of 0.001%
+  uint16_t dvi_ss_rate_10hz;
+  uint16_t hdmi_ss_percentage;      // in unit of 0.001%
+  uint16_t hdmi_ss_rate_10hz;
+  uint16_t dp_ss_percentage;        // in unit of 0.001%
+  uint16_t dp_ss_rate_10hz;
+  uint8_t  dvi_ss_mode;             // enum of atom_spread_spectrum_mode
+  uint8_t  hdmi_ss_mode;            // enum of atom_spread_spectrum_mode
+  uint8_t  dp_ss_mode;              // enum of atom_spread_spectrum_mode
+  uint8_t  ss_reserved;
+  uint8_t  dfp_hardcode_mode_num;   // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
+  uint8_t  dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
+  uint8_t  vga_hardcode_mode_num;   // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+  uint8_t  vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
+  uint16_t dpphy_refclk_10khz;
+  uint16_t reserved2;
+  uint8_t  dcnip_min_ver;
+  uint8_t  dcnip_max_ver;
+  uint8_t  max_disp_pipe_num;
+  uint8_t  max_vbios_active_disp_pipe_num;
+  uint8_t  max_ppll_num;
+  uint8_t  max_disp_phy_num;
+  uint8_t  max_aux_pairs;
+  uint8_t  remotedisplayconfig;
+  uint8_t  reserved3[8];
+};
+
 struct atom_display_controller_info_v4_4 {
 	struct atom_common_table_header table_header;
 	uint32_t display_caps;
@@ -1043,7 +1077,8 @@ enum dce_info_caps_def
   DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2      =0x04,
   // only for VBIOS
   DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING   =0x08,
-
+  // only for VBIOS
+  DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE	 =0x20,
 };
 
 /* 
-- 
2.25.1

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[PATCH 02/21] drm/amd/display: Add refresh rate trace

[Anson Jacob]

From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

When we have to debug VRR issues, we usually want to know the current
refresh rate; for this reason, it is handy to have a way to check in
real-time the refresh rate value. This commit introduces a kernel trace
that can provide such information.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++++++++++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_trace.h   | 19 +++++++++++++++++++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4c02373a707a..29313d71155e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -459,6 +459,9 @@ static void dm_vupdate_high_irq(void *interrupt_params)
 	struct common_irq_params *irq_params = interrupt_params;
 	struct amdgpu_device *adev = irq_params->adev;
 	struct amdgpu_crtc *acrtc;
+	struct drm_device *drm_dev;
+	struct drm_vblank_crtc *vblank;
+	ktime_t frame_duration_ns, previous_timestamp;
 	unsigned long flags;
 	int vrr_active;
 
@@ -466,6 +469,17 @@ static void dm_vupdate_high_irq(void *interrupt_params)
 
 	if (acrtc) {
 		vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
+		drm_dev = acrtc->base.dev;
+		vblank = &drm_dev->vblank[acrtc->base.index];
+		previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
+		frame_duration_ns = vblank->time - previous_timestamp;
+
+		if (frame_duration_ns > 0) {
+			trace_amdgpu_refresh_rate_track(acrtc->base.index,
+						frame_duration_ns,
+						ktime_divns(NSEC_PER_SEC, frame_duration_ns));
+			atomic64_set(&irq_params->previous_timestamp, vblank->time);
+		}
 
 		DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d\n",
 			      acrtc->crtc_id,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 1b8988dc0daf..c5f5f62cf591 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -66,6 +66,7 @@ struct dc_plane_state;
 struct common_irq_params {
 	struct amdgpu_device *adev;
 	enum dc_irq_source irq_src;
+	atomic64_t previous_timestamp;
 };
 
 /**
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index ac8bcd171b57..46a33f64cf8e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -618,6 +618,25 @@ TRACE_EVENT(amdgpu_dmub_trace_high_irq,
 		  __entry->param0, __entry->param1)
 );
 
+TRACE_EVENT(amdgpu_refresh_rate_track,
+	TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz),
+	TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz),
+	TP_STRUCT__entry(
+		__field(int, crtc_index)
+		__field(ktime_t, refresh_rate_ns)
+		__field(uint32_t, refresh_rate_hz)
+		),
+	TP_fast_assign(
+		__entry->crtc_index = crtc_index;
+		__entry->refresh_rate_ns = refresh_rate_ns;
+		__entry->refresh_rate_hz = refresh_rate_hz;
+	),
+	TP_printk("crtc_index=%d refresh_rate=%dHz (%lld)",
+		  __entry->crtc_index,
+		  __entry->refresh_rate_hz,
+		  __entry->refresh_rate_ns)
+);
+
 #endif /* _AMDGPU_DM_TRACE_H_ */
 
 #undef TRACE_INCLUDE_PATH
-- 
2.25.1

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[PATCH 03/21] drm/amd/display: Fix static checker warnings on tracebuff_fb

[Anson Jacob]

From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>

[Why]
Static analysis on linux-next has found a potential null pointer
dereference;

[How]
Refactor the function, add ASSERT and remove the unnecessary check.

Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 142 +++++++++---------
 1 file changed, 68 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 8ba0a9e2da54..743d3b7f6f24 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -415,6 +415,12 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	if (!dmub->sw_init)
 		return DMUB_STATUS_INVALID;
 
+	if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
+		!tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
+		ASSERT(0);
+		return DMUB_STATUS_INVALID;
+	}
+
 	dmub->fb_base = params->fb_base;
 	dmub->fb_offset = params->fb_offset;
 	dmub->psp_version = params->psp_version;
@@ -422,97 +428,85 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 	if (dmub->hw_funcs.reset)
 		dmub->hw_funcs.reset(dmub);
 
-	if (inst_fb && data_fb) {
-		cw0.offset.quad_part = inst_fb->gpu_addr;
-		cw0.region.base = DMUB_CW0_BASE;
-		cw0.region.top = cw0.region.base + inst_fb->size - 1;
-
-		cw1.offset.quad_part = stack_fb->gpu_addr;
-		cw1.region.base = DMUB_CW1_BASE;
-		cw1.region.top = cw1.region.base + stack_fb->size - 1;
-
-		if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
-		    /**
-		     * Read back all the instruction memory so we don't hang the
-		     * DMCUB when backdoor loading if the write from x86 hasn't been
-		     * flushed yet. This only occurs in backdoor loading.
-		     */
-		    dmub_flush_buffer_mem(inst_fb);
-		    dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
-		}
-
-	}
-
-	if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb &&
-	    fw_state_fb && scratch_mem_fb) {
-		cw2.offset.quad_part = data_fb->gpu_addr;
-		cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
-		cw2.region.top = cw2.region.base + data_fb->size;
+	cw0.offset.quad_part = inst_fb->gpu_addr;
+	cw0.region.base = DMUB_CW0_BASE;
+	cw0.region.top = cw0.region.base + inst_fb->size - 1;
 
-		cw3.offset.quad_part = bios_fb->gpu_addr;
-		cw3.region.base = DMUB_CW3_BASE;
-		cw3.region.top = cw3.region.base + bios_fb->size;
-
-		cw4.offset.quad_part = mail_fb->gpu_addr;
-		cw4.region.base = DMUB_CW4_BASE;
-		cw4.region.top = cw4.region.base + mail_fb->size;
+	cw1.offset.quad_part = stack_fb->gpu_addr;
+	cw1.region.base = DMUB_CW1_BASE;
+	cw1.region.top = cw1.region.base + stack_fb->size - 1;
 
+	if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
 		/**
-		 * Doubled the mailbox region to accomodate inbox and outbox.
-		 * Note: Currently, currently total mailbox size is 16KB. It is split
-		 * equally into 8KB between inbox and outbox. If this config is
-		 * changed, then uncached base address configuration of outbox1
-		 * has to be updated in funcs->setup_out_mailbox.
+		 * Read back all the instruction memory so we don't hang the
+		 * DMCUB when backdoor loading if the write from x86 hasn't been
+		 * flushed yet. This only occurs in backdoor loading.
 		 */
-		inbox1.base = cw4.region.base;
-		inbox1.top = cw4.region.base + DMUB_RB_SIZE;
-		outbox1.base = inbox1.top;
-		outbox1.top = cw4.region.top;
+		dmub_flush_buffer_mem(inst_fb);
+		dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
+	}
 
-		cw5.offset.quad_part = tracebuff_fb->gpu_addr;
-		cw5.region.base = DMUB_CW5_BASE;
-		cw5.region.top = cw5.region.base + tracebuff_fb->size;
+	cw2.offset.quad_part = data_fb->gpu_addr;
+	cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
+	cw2.region.top = cw2.region.base + data_fb->size;
 
-		outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
-		outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
+	cw3.offset.quad_part = bios_fb->gpu_addr;
+	cw3.region.base = DMUB_CW3_BASE;
+	cw3.region.top = cw3.region.base + bios_fb->size;
 
+	cw4.offset.quad_part = mail_fb->gpu_addr;
+	cw4.region.base = DMUB_CW4_BASE;
+	cw4.region.top = cw4.region.base + mail_fb->size;
 
-		cw6.offset.quad_part = fw_state_fb->gpu_addr;
-		cw6.region.base = DMUB_CW6_BASE;
-		cw6.region.top = cw6.region.base + fw_state_fb->size;
+	/**
+	 * Doubled the mailbox region to accomodate inbox and outbox.
+	 * Note: Currently, currently total mailbox size is 16KB. It is split
+	 * equally into 8KB between inbox and outbox. If this config is
+	 * changed, then uncached base address configuration of outbox1
+	 * has to be updated in funcs->setup_out_mailbox.
+	 */
+	inbox1.base = cw4.region.base;
+	inbox1.top = cw4.region.base + DMUB_RB_SIZE;
+	outbox1.base = inbox1.top;
+	outbox1.top = cw4.region.top;
 
-		dmub->fw_state = fw_state_fb->cpu_addr;
+	cw5.offset.quad_part = tracebuff_fb->gpu_addr;
+	cw5.region.base = DMUB_CW5_BASE;
+	cw5.region.top = cw5.region.base + tracebuff_fb->size;
 
-		dmub->scratch_mem_fb = *scratch_mem_fb;
+	outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
+	outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
 
-		if (dmub->hw_funcs.setup_windows)
-			dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4,
-						     &cw5, &cw6);
+	cw6.offset.quad_part = fw_state_fb->gpu_addr;
+	cw6.region.base = DMUB_CW6_BASE;
+	cw6.region.top = cw6.region.base + fw_state_fb->size;
 
-		if (dmub->hw_funcs.setup_outbox0)
-			dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
+	dmub->fw_state = fw_state_fb->cpu_addr;
 
-		if (dmub->hw_funcs.setup_mailbox)
-			dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
-		if (dmub->hw_funcs.setup_out_mailbox)
-			dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
-	}
+	dmub->scratch_mem_fb = *scratch_mem_fb;
 
-	if (mail_fb) {
-		dmub_memset(&rb_params, 0, sizeof(rb_params));
-		rb_params.ctx = dmub;
-		rb_params.base_address = mail_fb->cpu_addr;
-		rb_params.capacity = DMUB_RB_SIZE;
+	if (dmub->hw_funcs.setup_windows)
+		dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
 
-		dmub_rb_init(&dmub->inbox1_rb, &rb_params);
+	if (dmub->hw_funcs.setup_outbox0)
+		dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
 
-		// Initialize outbox1 ring buffer
-		rb_params.ctx = dmub;
-		rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
-		rb_params.capacity = DMUB_RB_SIZE;
-		dmub_rb_init(&dmub->outbox1_rb, &rb_params);
+	if (dmub->hw_funcs.setup_mailbox)
+		dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
+	if (dmub->hw_funcs.setup_out_mailbox)
+		dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
 
-	}
+	dmub_memset(&rb_params, 0, sizeof(rb_params));
+	rb_params.ctx = dmub;
+	rb_params.base_address = mail_fb->cpu_addr;
+	rb_params.capacity = DMUB_RB_SIZE;
+	dmub_rb_init(&dmub->inbox1_rb, &rb_params);
+
+	// Initialize outbox1 ring buffer
+	rb_params.ctx = dmub;
+	rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
+	rb_params.capacity = DMUB_RB_SIZE;
+	dmub_rb_init(&dmub->outbox1_rb, &rb_params);
 
 	dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
 	outbox0_rb_params.ctx = dmub;
-- 
2.25.1

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[PATCH 04/21] drm/amd/display: Guard ASSR with internal display flag

[Anson Jacob]

From: Stylon Wang <stylon.wang@amd.com>

[Why]
ASSR enabling only considers capability declared in DPCD.
We also need to check whether the connector is internal.

[How]
ASSR enabling need to check both DPCD capability and internal display
flag.

Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 58 +++++++++++++------
 1 file changed, 41 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 484d96f78ade..a92fc1875474 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1635,6 +1635,42 @@ enum link_training_result dc_link_dp_perform_link_training(
 	return status;
 }
 
+static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
+{
+	struct dc_link *link = stream->link;
+	enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
+#ifdef CONFIG_DRM_AMD_DC_HDCP
+	struct cp_psp *cp_psp = &stream->ctx->cp_psp;
+#endif
+
+	/* ASSR must be supported on the panel */
+	if (panel_mode == DP_PANEL_MODE_DEFAULT)
+		return panel_mode;
+
+	/* eDP or internal DP only */
+	if (link->connector_signal != SIGNAL_TYPE_EDP &&
+		!(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
+		 link->is_internal_display))
+		return DP_PANEL_MODE_DEFAULT;
+
+#ifdef CONFIG_DRM_AMD_DC_HDCP
+	if (cp_psp && cp_psp->funcs.enable_assr) {
+		if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
+			/* since eDP implies ASSR on, change panel
+			 * mode to disable ASSR
+			 */
+			panel_mode = DP_PANEL_MODE_DEFAULT;
+		}
+	} else
+		panel_mode = DP_PANEL_MODE_DEFAULT;
+
+#else
+	/* turn off ASSR if the implementation is not compiled in */
+	panel_mode = DP_PANEL_MODE_DEFAULT;
+#endif
+	return panel_mode;
+}
+
 bool perform_link_training_with_retries(
 	const struct dc_link_settings *link_setting,
 	bool skip_video_pattern,
@@ -1646,7 +1682,7 @@ bool perform_link_training_with_retries(
 	uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
 	struct dc_stream_state *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->link;
-	enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
+	enum dp_panel_mode panel_mode;
 
 	/* We need to do this before the link training to ensure the idle pattern in SST
 	 * mode will be sent right after the link training
@@ -1671,23 +1707,11 @@ bool perform_link_training_with_retries(
 			msleep(delay_dp_power_up_in_ms);
 		}
 
-#ifdef CONFIG_DRM_AMD_DC_HDCP
-		if (panel_mode == DP_PANEL_MODE_EDP) {
-			struct cp_psp *cp_psp = &stream->ctx->cp_psp;
-
-			if (cp_psp && cp_psp->funcs.enable_assr) {
-				if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
-					/* since eDP implies ASSR on, change panel
-					 * mode to disable ASSR
-					 */
-					panel_mode = DP_PANEL_MODE_DEFAULT;
-				}
-			} else
-				panel_mode = DP_PANEL_MODE_DEFAULT;
-		}
-#endif
-
+		panel_mode = try_enable_assr(stream);
 		dp_set_panel_mode(link, panel_mode);
+		DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
+			 link->link_index,
+			 panel_mode != DP_PANEL_MODE_DEFAULT);
 
 		if (link->aux_access_disabled) {
 			dc_link_dp_perform_link_training_skip_aux(link, link_setting);
-- 
2.25.1

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[PATCH 05/21] drm/amd/display: enable DP DSC Compliance automation

[Anson Jacob]

From: Qingqing Zhuo <qingqing.zhuo@amd.com>

[Why]
Color depth data is not parsed during test requests.

[How]
Update display color depth according to color depth
request from the test equipment.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index a92fc1875474..962e88dd8dda 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2808,10 +2808,27 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
 	enum dp_test_pattern test_pattern;
 	enum dp_test_pattern_color_space test_pattern_color_space =
 			DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
+	enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
+	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
+	struct pipe_ctx *pipe_ctx = NULL;
+	int i;
 
 	memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
 	memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
 
+	for (i = 0; i < MAX_PIPES; i++) {
+		if (pipes[i].stream == NULL)
+			continue;
+
+		if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
+			pipe_ctx = &pipes[i];
+			break;
+		}
+	}
+
+	if (pipe_ctx == NULL)
+		return;
+
 	/* get link test pattern and pattern parameters */
 	core_link_read_dpcd(
 			link,
@@ -2849,6 +2866,29 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
 				DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
 				DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
 
+	switch (dpcd_test_params.bits.BPC) {
+	case 0: // 6 bits
+		requestColorDepth = COLOR_DEPTH_666;
+		break;
+	case 1: // 8 bits
+		requestColorDepth = COLOR_DEPTH_888;
+		break;
+	case 2: // 10 bits
+		requestColorDepth = COLOR_DEPTH_101010;
+		break;
+	case 3: // 12 bits
+		requestColorDepth = COLOR_DEPTH_121212;
+		break;
+	default:
+		break;
+	}
+
+	if (requestColorDepth != COLOR_DEPTH_UNDEFINED
+			&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
+		pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
+		dp_update_dsc_config(pipe_ctx);
+	}
+
 	dc_link_dp_set_test_pattern(
 			link,
 			test_pattern,
-- 
2.25.1

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[PATCH 06/21] drm/amd/display: define mod_hdcp_display_disable_option struct

[Anson Jacob]

From: Wenjing Liu <wenjing.liu@amd.com>

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c |  6 +++---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c        |  4 ++--
 drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h     | 10 ++++++++--
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 0cdbfcd475ec..60f91853bd82 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -191,7 +191,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
 				psp_set_srm(hdcp_work->hdcp.config.psp.handle, hdcp_work->srm, hdcp_work->srm_size,
 					    &hdcp_work->srm_version);
 
-			display->adjust.disable = 0;
+			display->adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE;
 			if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) {
 				hdcp_w->link.adjust.hdcp1.disable = 0;
 				hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
@@ -203,7 +203,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
 			schedule_delayed_work(&hdcp_w->property_validate_dwork,
 					      msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
 		} else {
-			display->adjust.disable = 1;
+			display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
 			hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 			cancel_delayed_work(&hdcp_w->property_validate_dwork);
 		}
@@ -456,7 +456,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 	link->dp.assr_enabled = config->assr_enabled;
 	link->dp.mst_enabled = config->mst_enabled;
-	display->adjust.disable = 1;
+	display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
 	link->adjust.auth_delay = 3;
 	link->adjust.hdcp1.disable = 0;
 
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index 20e554e771d1..e7b841d960e7 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -53,7 +53,7 @@ static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)
 	 */
 	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
 		if (hdcp->displays[i].state != MOD_HDCP_DISPLAY_INACTIVE &&
-				!hdcp->displays[i].adjust.disable) {
+				hdcp->displays[i].adjust.disable != MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION) {
 			is_auth_needed = 1;
 			break;
 		}
@@ -74,7 +74,7 @@ static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)
 	 */
 	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
 		if (hdcp->displays[i].state != MOD_HDCP_DISPLAY_INACTIVE &&
-				!hdcp->displays[i].adjust.disable) {
+				hdcp->displays[i].adjust.disable != MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION) {
 			is_auth_needed = 1;
 			break;
 		}
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index d223ed3be5d3..5fbc4c1376e4 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -120,6 +120,12 @@ enum mod_hdcp_display_state {
 	MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED
 };
 
+enum mod_hdcp_display_disable_option {
+	MOD_HDCP_DISPLAY_NOT_DISABLE = 0,
+	MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION,
+	MOD_HDCP_DISPLAY_DISABLE_ENCRYPTION,
+};
+
 struct mod_hdcp_ddc {
 	void *handle;
 	struct {
@@ -149,8 +155,8 @@ struct mod_hdcp_psp {
 };
 
 struct mod_hdcp_display_adjustment {
-	uint8_t disable			: 1;
-	uint8_t reserved		: 7;
+	uint8_t disable			: 2;
+	uint8_t reserved		: 6;
 };
 
 struct mod_hdcp_link_adjustment_hdcp1 {
-- 
2.25.1

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[PATCH 07/21] drm/amd/display: add mod hdcp interface for supporting encryption state query

[Anson Jacob]

From: Wenjing Liu <wenjing.liu@amd.com>

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |  6 +++
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   |  4 +-
 .../display/modules/hdcp/hdcp1_execution.c    | 37 +++++++++++--------
 .../display/modules/hdcp/hdcp1_transition.c   |  6 +--
 .../display/modules/hdcp/hdcp2_execution.c    | 10 +++--
 .../display/modules/hdcp/hdcp2_transition.c   | 10 ++---
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   | 10 +++++
 7 files changed, 54 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index e7b841d960e7..68a6481d7f8f 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -314,6 +314,9 @@ enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp *hdcp,
 		goto out;
 	}
 
+	/* save current encryption states to restore after next authentication */
+	mod_hdcp_save_current_encryption_states(hdcp);
+
 	/* reset existing authentication status */
 	status = reset_authentication(hdcp, output);
 	if (status != MOD_HDCP_STATUS_SUCCESS)
@@ -360,6 +363,9 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct mod_hdcp *hdcp,
 		goto out;
 	}
 
+	/* save current encryption states to restore after next authentication */
+	mod_hdcp_save_current_encryption_states(hdcp);
+
 	/* stop current authentication */
 	status = reset_authentication(hdcp, output);
 	if (status != MOD_HDCP_STATUS_SUCCESS)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index 5c22cf7e6118..3ce91db560d1 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -331,6 +331,8 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(
 		struct mod_hdcp *hdcp, struct mod_hdcp_display *display);
 enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
 		struct mod_hdcp *hdcp, uint8_t index);
+bool mod_hdcp_is_link_encryption_enabled(struct mod_hdcp *hdcp);
+void mod_hdcp_save_current_encryption_states(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp1_destroy_session(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp1_validate_rx(struct mod_hdcp *hdcp);
@@ -339,8 +341,6 @@ enum mod_hdcp_status mod_hdcp_hdcp1_validate_ksvlist_vp(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp1_enable_dp_stream_encryption(
 	struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp);
-enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *hdcp,
-							       enum mod_hdcp_encryption_status *encryption_status);
 enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp2_prepare_ake_init(struct mod_hdcp *hdcp);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
index 73ca49f05bd3..eeac14300a2a 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
@@ -256,10 +256,12 @@ static enum mod_hdcp_status authenticated(struct mod_hdcp *hdcp,
 		goto out;
 	}
 
-	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp1_link_maintenance,
+	mod_hdcp_execute_and_set(mod_hdcp_hdcp1_link_maintenance,
 			&input->link_maintenance, &status,
-			hdcp, "link_maintenance"))
-		goto out;
+			hdcp, "link_maintenance");
+
+	if (status != MOD_HDCP_STATUS_SUCCESS)
+		mod_hdcp_save_current_encryption_states(hdcp);
 out:
 	return status;
 }
@@ -425,19 +427,24 @@ static enum mod_hdcp_status authenticated_dp(struct mod_hdcp *hdcp,
 		event_ctx->unexpected_event = 1;
 		goto out;
 	}
-
-	if (!mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,
-			&input->bstatus_read, &status,
-			hdcp, "bstatus_read"))
-		goto out;
-	if (!mod_hdcp_execute_and_set(check_link_integrity_dp,
-			&input->link_integrity_check, &status,
-			hdcp, "link_integrity_check"))
-		goto out;
-	if (!mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,
-			&input->reauth_request_check, &status,
-			hdcp, "reauth_request_check"))
+	if (!mod_hdcp_is_link_encryption_enabled(hdcp))
 		goto out;
+
+	if (status == MOD_HDCP_STATUS_SUCCESS)
+		mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,
+				&input->bstatus_read, &status,
+				hdcp, "bstatus_read");
+	if (status == MOD_HDCP_STATUS_SUCCESS)
+		mod_hdcp_execute_and_set(check_link_integrity_dp,
+				&input->link_integrity_check, &status,
+				hdcp, "link_integrity_check");
+	if (status == MOD_HDCP_STATUS_SUCCESS)
+		mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,
+				&input->reauth_request_check, &status,
+				hdcp, "reauth_request_check");
+
+	if (status != MOD_HDCP_STATUS_SUCCESS)
+		mod_hdcp_save_current_encryption_states(hdcp);
 out:
 	return status;
 }
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
index 24ab95b093f7..3dda8c1d83fc 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
@@ -93,7 +93,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct mod_hdcp *hdcp,
 		}
 		break;
 	case H1_A45_AUTHENTICATED:
-		if (input->link_maintenance != PASS) {
+		if (input->link_maintenance == FAIL) {
 			/* 1A-07: consider invalid ri' a failure */
 			/* 1A-07a: consider read ri' not returned a failure */
 			fail_and_restart_in_ms(0, &status, output);
@@ -243,8 +243,8 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
 		}
 		break;
 	case D1_A4_AUTHENTICATED:
-		if (input->link_integrity_check != PASS ||
-				input->reauth_request_check != PASS) {
+		if (input->link_integrity_check == FAIL ||
+				input->reauth_request_check == FAIL) {
 			/* 1A-07: restart hdcp on a link integrity failure */
 			fail_and_restart_in_ms(0, &status, output);
 			break;
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
index a0895a7efda2..f164f6a5d4dc 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
@@ -564,11 +564,13 @@ static enum mod_hdcp_status authenticated(struct mod_hdcp *hdcp,
 		event_ctx->unexpected_event = 1;
 		goto out;
 	}
-
-	if (!process_rxstatus(hdcp, event_ctx, input, &status))
-		goto out;
-	if (event_ctx->rx_id_list_ready)
+	if (!mod_hdcp_is_link_encryption_enabled(hdcp))
 		goto out;
+
+	process_rxstatus(hdcp, event_ctx, input, &status);
+
+	if (status != MOD_HDCP_STATUS_SUCCESS)
+		mod_hdcp_save_current_encryption_states(hdcp);
 out:
 	return status;
 }
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
index e738c7ae66ec..b0306ed6d6b4 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
@@ -245,8 +245,8 @@ enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp,
 		HDCP_FULL_DDC_TRACE(hdcp);
 		break;
 	case H2_A5_AUTHENTICATED:
-		if (input->rxstatus_read != PASS ||
-				input->reauth_request_check != PASS) {
+		if (input->rxstatus_read == FAIL ||
+				input->reauth_request_check == FAIL) {
 			fail_and_restart_in_ms(0, &status, output);
 			break;
 		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
@@ -562,11 +562,11 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
 		HDCP_FULL_DDC_TRACE(hdcp);
 		break;
 	case D2_A5_AUTHENTICATED:
-		if (input->rxstatus_read != PASS ||
-				input->reauth_request_check != PASS) {
+		if (input->rxstatus_read == FAIL ||
+				input->reauth_request_check == FAIL) {
 			fail_and_restart_in_ms(0, &status, output);
 			break;
-		} else if (input->link_integrity_check_dp != PASS) {
+		} else if (input->link_integrity_check_dp == FAIL) {
 			if (hdcp->connection.hdcp2_retry_count >= 1)
 				adjust->hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
 			fail_and_restart_in_ms(0, &status, output);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 904ce9b88088..9d7ca316dc3f 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -914,3 +914,13 @@ enum mod_hdcp_status mod_hdcp_hdcp2_validate_stream_ready(struct mod_hdcp *hdcp)
 	return status;
 }
 
+bool mod_hdcp_is_link_encryption_enabled(struct mod_hdcp *hdcp)
+{
+	/* unsupported */
+	return true;
+}
+
+void mod_hdcp_save_current_encryption_states(struct mod_hdcp *hdcp)
+{
+	/* unsupported */
+}
-- 
2.25.1

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[PATCH 08/21] drm/amd/display: Fix typo for variable name

[Anson Jacob]

From: Vladimir Stempen <vladimir.stempen@amd.com>

[why]
Word "remainder" was misspelled as "reminder" in
reduceSizeAndFraction method variable.

[how]
Fix the spelling.

Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com>
Reviewed-by: Alexander Deucher <alexander.deucher@amd.com>
Reviewed-by: Bindu R <Bindu.R@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e0aa88a7766b..e1f33f908b5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1893,7 +1893,7 @@ uint64_t reduceSizeAndFraction(
 	num = *numerator;
 	denom = *denominator;
 	for (i = 0; i < count; i++) {
-		uint32_t num_reminder, denom_reminder;
+		uint32_t num_remainder, denom_remainder;
 		uint64_t num_result, denom_result;
 		if (checkUint32Bounary &&
 			num <= max_int32 && denom <= max_int32) {
@@ -1901,13 +1901,13 @@ uint64_t reduceSizeAndFraction(
 			break;
 		}
 		do {
-			num_result = div_u64_rem(num, prime_numbers[i], &num_reminder);
-			denom_result = div_u64_rem(denom, prime_numbers[i], &denom_reminder);
-			if (num_reminder == 0 && denom_reminder == 0) {
+			num_result = div_u64_rem(num, prime_numbers[i], &num_remainder);
+			denom_result = div_u64_rem(denom, prime_numbers[i], &denom_remainder);
+			if (num_remainder == 0 && denom_remainder == 0) {
 				num = num_result;
 				denom = denom_result;
 			}
-		} while (num_reminder == 0 && denom_reminder == 0);
+		} while (num_remainder == 0 && denom_remainder == 0);
 	}
 	*numerator = num;
 	*denominator = denom;
-- 
2.25.1

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[PATCH 09/21] drm/amd/display: Rename fs_params to hdr_tm_params

[Anson Jacob]

From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>

[Why&How]
Renaming structure to better indicate its meaning.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 +++---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.h | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 5c67e12b2e55..ef742d95ef05 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -942,7 +942,7 @@ static void hermite_spline_eetf(struct fixed31_32 input_x,
 static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
 		uint32_t hw_points_num,
 		const struct hw_x_point *coordinate_x,
-		const struct freesync_hdr_tf_params *fs_params,
+		const struct hdr_tm_params *fs_params,
 		struct calculate_buffer *cal_buffer)
 {
 	uint32_t i;
@@ -2027,7 +2027,7 @@ bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
 static bool calculate_curve(enum dc_transfer_func_predefined trans,
 				struct dc_transfer_func_distributed_points *points,
 				struct pwl_float_data_ex *rgb_regamma,
-				const struct freesync_hdr_tf_params *fs_params,
+				const struct hdr_tm_params *fs_params,
 				uint32_t sdr_ref_white_level,
 				struct calculate_buffer *cal_buffer)
 {
@@ -2106,7 +2106,7 @@ static bool calculate_curve(enum dc_transfer_func_predefined trans,
 
 bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 		const struct dc_gamma *ramp, bool mapUserRamp, bool canRomBeUsed,
-		const struct freesync_hdr_tf_params *fs_params,
+		const struct hdr_tm_params *fs_params,
 		struct calculate_buffer *cal_buffer)
 {
 	struct dc_transfer_func_distributed_points *tf_pts = &output_tf->tf_pts;
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
index 7563457e2ff4..2893abf48208 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
@@ -76,7 +76,7 @@ struct regamma_lut {
 	};
 };
 
-struct freesync_hdr_tf_params {
+struct hdr_tm_params {
 	unsigned int sdr_white_level;
 	unsigned int min_content; // luminance in 1/10000 nits
 	unsigned int max_content; // luminance in nits
@@ -108,7 +108,7 @@ void precompute_de_pq(void);
 
 bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 		const struct dc_gamma *ramp, bool mapUserRamp, bool canRomBeUsed,
-		const struct freesync_hdr_tf_params *fs_params,
+		const struct hdr_tm_params *fs_params,
 		struct calculate_buffer *cal_buffer);
 
 bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
-- 
2.25.1

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[PATCH 10/21] drm/amd/display: Interface for LTTPR interop

[Anson Jacob]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
The logic to toggle LTTPR transparent/non-transparent requires 2 flags
provided by BIOS

[HOW]
Repurpose the interface to get dce caps so both LTTPR querying functions
can use them.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../drm/amd/display/dc/bios/bios_parser2.c    | 75 ++++++++++++++++---
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |  3 +
 drivers/gpu/drm/amd/include/atomfirmware.h    |  1 +
 3 files changed, 67 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 2ee0c6fc069a..d79f4fe06c47 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -916,7 +916,7 @@ static enum bp_result bios_parser_get_soc_bb_info(
 	return result;
 }
 
-static enum bp_result get_lttpr_caps_v4_1(
+static enum bp_result get_disp_caps_v4_1(
 	struct bios_parser *bp,
 	uint8_t *dce_caps)
 {
@@ -935,12 +935,12 @@ static enum bp_result get_lttpr_caps_v4_1(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+	*dce_caps = disp_cntl_tbl->display_caps;
 
 	return result;
 }
 
-static enum bp_result get_lttpr_caps_v4_2(
+static enum bp_result get_disp_caps_v4_2(
 	struct bios_parser *bp,
 	uint8_t *dce_caps)
 {
@@ -959,12 +959,12 @@ static enum bp_result get_lttpr_caps_v4_2(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+	*dce_caps = disp_cntl_tbl->display_caps;
 
 	return result;
 }
 
-static enum bp_result get_lttpr_caps_v4_3(
+static enum bp_result get_disp_caps_v4_3(
 	struct bios_parser *bp,
 	uint8_t *dce_caps)
 {
@@ -983,12 +983,12 @@ static enum bp_result get_lttpr_caps_v4_3(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+	*dce_caps = disp_cntl_tbl->display_caps;
 
 	return result;
 }
 
-static enum bp_result get_lttpr_caps_v4_4(
+static enum bp_result get_disp_caps_v4_4(
 	struct bios_parser *bp,
 	uint8_t *dce_caps)
 {
@@ -1007,7 +1007,52 @@ static enum bp_result get_lttpr_caps_v4_4(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = !!(disp_cntl_tbl->display_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
+	*dce_caps = disp_cntl_tbl->display_caps;
+
+	return result;
+}
+
+static enum bp_result bios_parser_get_lttpr_interop(
+	struct dc_bios *dcb,
+	uint8_t *dce_caps)
+{
+	struct bios_parser *bp = BP_FROM_DCB(dcb);
+	enum bp_result result = BP_RESULT_UNSUPPORTED;
+	struct atom_common_table_header *header;
+	struct atom_data_revision tbl_revision;
+
+	if (!DATA_TABLES(dce_info))
+		return BP_RESULT_UNSUPPORTED;
+
+	header = GET_IMAGE(struct atom_common_table_header,
+						DATA_TABLES(dce_info));
+	get_atom_data_table_revision(header, &tbl_revision);
+	switch (tbl_revision.major) {
+	case 4:
+		switch (tbl_revision.minor) {
+		case 1:
+			result = get_disp_caps_v4_1(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
+			break;
+		case 2:
+			result = get_disp_caps_v4_2(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
+			break;
+		case 3:
+			result = get_disp_caps_v4_3(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
+			break;
+		case 4:
+			result = get_disp_caps_v4_4(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
 
 	return result;
 }
@@ -1031,16 +1076,20 @@ static enum bp_result bios_parser_get_lttpr_caps(
 	case 4:
 		switch (tbl_revision.minor) {
 		case 1:
-			result = get_lttpr_caps_v4_1(bp, dce_caps);
+			result = get_disp_caps_v4_1(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
 			break;
 		case 2:
-			result = get_lttpr_caps_v4_2(bp, dce_caps);
+			result = get_disp_caps_v4_2(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
 			break;
 		case 3:
-			result = get_lttpr_caps_v4_3(bp, dce_caps);
+			result = get_disp_caps_v4_3(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
 			break;
 		case 4:
-			result = get_lttpr_caps_v4_4(bp, dce_caps);
+			result = get_disp_caps_v4_4(bp, dce_caps);
+			*dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
 			break;
 		default:
 			break;
@@ -2670,6 +2719,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
 	.get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
 
 	.get_lttpr_caps = bios_parser_get_lttpr_caps,
+
+	.get_lttpr_interop = bios_parser_get_lttpr_interop,
 };
 
 static bool bios_parser2_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 1b957c60156b..67abda44eb1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -153,6 +153,9 @@ struct dc_vbios_funcs {
 	enum bp_result (*get_lttpr_caps)(
 			struct dc_bios *dcb,
 			uint8_t *dce_caps);
+	enum bp_result (*get_lttpr_interop)(
+			struct dc_bios *dcb,
+			uint8_t *dce_caps);
 };
 
 struct bios_registers {
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 82b3cd89b383..c77ed38c20fb 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1079,6 +1079,7 @@ enum dce_info_caps_def
   DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING   =0x08,
   // only for VBIOS
   DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE	 =0x20,
+  DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
 };
 
 /* 
-- 
2.25.1

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[PATCH 11/21] drm/amd/display: Enumerate LTTPR modes

[Anson Jacob]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
There are three possible modes for LTTPR:
- Non-LTTPR mode, where AUX timeout is 400 us and no per-hop link
training is done
- LTTPR Transparent mode, where AUX timeout is 3200 us and no per-hop
link training is done
- LTTPR Non-Transparent mode, where AUX timeout is 3200 us and per-hop
link training is done

[HOW]
Use an enum instead of a bool to track LTTPR state; modify comparisons
accordingly.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 33 +++++++++++++------
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  9 ++++-
 3 files changed, 32 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 962e88dd8dda..209286357867 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -284,7 +284,7 @@ static uint8_t dc_dp_initialize_scrambling_data_symbols(
 
 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 {
-	return (link->lttpr_non_transparent_mode && offset != 0);
+	return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 }
 
 static void dpcd_set_lt_pattern_and_lane_settings(
@@ -1072,7 +1072,7 @@ static enum link_training_result perform_clock_recovery_sequence(
 		/* 3. wait receiver to lock-on*/
 		wait_time_microsec = lt_settings->cr_pattern_time;
 
-		if (link->lttpr_non_transparent_mode)
+		if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
 			wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
 
 		wait_for_training_aux_rd_interval(
@@ -1326,7 +1326,17 @@ static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
 	return 0; // invalid value
 }
 
-static void configure_lttpr_mode(struct dc_link *link)
+static void configure_lttpr_mode_transparent(struct dc_link *link)
+{
+	uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
+
+	core_link_write_dpcd(link,
+			DP_PHY_REPEATER_MODE,
+			(uint8_t *)&repeater_mode,
+			sizeof(repeater_mode));
+}
+
+static void configure_lttpr_mode_non_transparent(struct dc_link *link)
 {
 	/* aux timeout is already set to extended */
 	/* RESET/SET lttpr mode to enable non transparent mode */
@@ -1346,7 +1356,7 @@ static void configure_lttpr_mode(struct dc_link *link)
 		link->dpcd_caps.lttpr_caps.mode = repeater_mode;
 	}
 
-	if (link->lttpr_non_transparent_mode) {
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
 
 		DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
 
@@ -1562,8 +1572,10 @@ enum link_training_result dc_link_dp_perform_link_training(
 			&lt_settings);
 
 	/* Configure lttpr mode */
-	if (link->lttpr_non_transparent_mode)
-		configure_lttpr_mode(link);
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
+		configure_lttpr_mode_non_transparent(link);
+	else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
+		configure_lttpr_mode_transparent(link);
 
 	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
 		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
@@ -1578,7 +1590,7 @@ enum link_training_result dc_link_dp_perform_link_training(
 
 	dp_set_fec_ready(link, fec_enable);
 
-	if (link->lttpr_non_transparent_mode) {
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
 
 		/* 2. perform link training (set link training done
 		 *  to false is done as well)
@@ -1899,7 +1911,7 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
 	 * account for lttpr repeaters cap
 	 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
 	 */
-	if (link->lttpr_non_transparent_mode) {
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
 		if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
 			max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
 
@@ -2057,7 +2069,7 @@ bool dp_verify_link_cap(
 	max_link_cap = get_max_link_cap(link);
 
 	/* Grant extended timeout request */
-	if (link->lttpr_non_transparent_mode && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
+	if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
 		uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
 
 		core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
@@ -3529,7 +3541,8 @@ static bool retrieve_link_cap(struct dc_link *link)
 	}
 
 	/* decide lttpr non transparent mode */
-	link->lttpr_non_transparent_mode = is_lttpr_present;
+	/*This is a temporary placeholder for LTTPR logic. More comprehensive logic will be added in a future change*/
+	link->lttpr_mode = is_lttpr_present ? LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_NON_LTTPR;
 
 	if (!is_lttpr_present)
 		dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 124ce215fca5..22fe19ee842d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -302,7 +302,7 @@ void dp_set_hw_lane_settings(
 {
 	struct link_encoder *encoder = link->link_enc;
 
-	if (link->lttpr_non_transparent_mode && !is_immediate_downstream(link, offset))
+	if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && !is_immediate_downstream(link, offset))
 		return;
 
 	/* call Encoder to set lane settings */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index c50ef5a909a6..7b927e634279 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -35,6 +35,13 @@ enum dc_link_fec_state {
 	dc_link_fec_ready,
 	dc_link_fec_enabled
 };
+
+enum lttpr_mode {
+	LTTPR_MODE_NON_LTTPR,
+	LTTPR_MODE_TRANSPARENT,
+	LTTPR_MODE_NON_TRANSPARENT,
+};
+
 struct dc_link_status {
 	bool link_active;
 	struct dpcd_caps *dpcd_caps;
@@ -100,7 +107,7 @@ struct dc_link {
 	bool link_state_valid;
 	bool aux_access_disabled;
 	bool sync_lt_in_progress;
-	bool lttpr_non_transparent_mode;
+	enum lttpr_mode lttpr_mode;
 	bool is_internal_display;
 
 	/* TODO: Rename. Flag an endpoint as having a programmable mapping to a
-- 
2.25.1

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[PATCH 12/21] drm/amd/display: LTTPR config logic

[Anson Jacob]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
Some systems can enable LTTPR through bits in BIOS, while other systems
can be configured at boot to enable LTTPR. Some configs enable
Non-Transparent mode, while others enable Transparent mode.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 51 +++++++++++++++----
 1 file changed, 41 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 209286357867..cebf68200f43 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3447,6 +3447,9 @@ static bool retrieve_link_cap(struct dc_link *link)
 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
 	bool is_lttpr_present = false;
 	const uint32_t post_oui_delay = 30; // 30ms
+	bool vbios_lttpr_enable = false;
+	bool vbios_lttpr_interop = false;
+	struct dc_bios *bios = link->dc->ctx->dc_bios;
 
 	memset(dpcd_data, '\0', sizeof(dpcd_data));
 	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
@@ -3494,13 +3497,45 @@ static bool retrieve_link_cap(struct dc_link *link)
 		return false;
 	}
 
-	if (link->dc->caps.extended_aux_timeout_support &&
-			link->dc->config.allow_lttpr_non_transparent_mode) {
+	/* Query BIOS to determine if LTTPR functionality is forced on by system */
+	if (bios->funcs->get_lttpr_caps) {
+		enum bp_result bp_query_result;
+		uint8_t is_vbios_lttpr_enable = 0;
+
+		bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
+		vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
+	}
+
+	if (bios->funcs->get_lttpr_interop) {
+		enum bp_result bp_query_result;
+		uint8_t is_vbios_interop_enabled = 0;
+
+		bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
+		vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
+	}
+
+	/*
+	 * Logic to determine LTTPR mode
+	 */
+	link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+	if (vbios_lttpr_enable && vbios_lttpr_interop)
+		link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
+	else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
+		if (link->dc->config.allow_lttpr_non_transparent_mode)
+			link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
+		else
+			link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
+	} else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
+		if (!link->dc->config.allow_lttpr_non_transparent_mode
+			|| !link->dc->caps.extended_aux_timeout_support)
+			link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
+		else
+			link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
+	}
+
+	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
 		/* By reading LTTPR capability, RX assumes that we will enable
-		 * LTTPR non transparent if LTTPR is present.
-		 * Therefore, only query LTTPR capability when both LTTPR
-		 * extended aux timeout and
-		 * non transparent mode is supported by hardware
+		 * LTTPR extended aux timeout if LTTPR is present.
 		 */
 		status = core_link_read_dpcd(
 				link,
@@ -3540,10 +3575,6 @@ static bool retrieve_link_cap(struct dc_link *link)
 			CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
 	}
 
-	/* decide lttpr non transparent mode */
-	/*This is a temporary placeholder for LTTPR logic. More comprehensive logic will be added in a future change*/
-	link->lttpr_mode = is_lttpr_present ? LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_NON_LTTPR;
-
 	if (!is_lttpr_present)
 		dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
 
-- 
2.25.1

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[PATCH 13/21] drm/amd/display: Fix MST topology debugfs

[Anson Jacob]

From: Eryk Brol <eryk.brol@amd.com>

[why]
The drm dump_topology function was previously called on all
DP connectors. This resulted in empty topology dumps for those
connectors which weren't root MST nodes.

[how]
Make sure we only dump topology from the root MST node.

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index f6f10a8c3e43..5a9809e33af8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2901,6 +2901,10 @@ static int mst_topo_show(struct seq_file *m, void *unused)
 
 		aconnector = to_amdgpu_dm_connector(connector);
 
+		/* Ensure we're only dumping the topology of a root mst node */
+		if (!aconnector->mst_mgr.mst_state)
+			continue;
+
 		seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
 		drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
 	}
-- 
2.25.1

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[PATCH 14/21] drm/amd/display: Add dynamic link encoder selection.

[Anson Jacob]

From: Jimmy Kizito <Jimmy.Kizito@amd.com>

[Why]
Some display endpoints may be programmably mapped to compatible link
encoders. The assignment of link encoders to links has to be dynamic to
accommodate the increased flexibility in comparison to conventional
display endpoints.

[How]
- Add link encoder assignment tracking variables.
- Execute link encoder assignment algorithm before enabling link and
release link encoders from links once they are disabled.

Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/Makefile       |   5 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |   4 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  16 +-
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 204 ++++++++++++++++++
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   7 +
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  10 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |   4 +
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  15 ++
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  27 +++
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  13 ++
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |  68 ++++++
 11 files changed, 366 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index bbde6e6a4e43..f33847299bca 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -54,8 +54,9 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI
 
 include $(AMD_DC)
 
-DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
-dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
+dc_link_enc_cfg.o
 
 ifdef CONFIG_DRM_AMD_DC_DCN
 DISPLAY_CORE += dc_vm_helper.o
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d55c1dd6464c..12cb95c5a1f9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -52,6 +52,7 @@
 
 #include "link_hwss.h"
 #include "link_encoder.h"
+#include "link_enc_cfg.h"
 
 #include "dc_link_ddc.h"
 #include "dm_helpers.h"
@@ -870,6 +871,9 @@ static bool dc_construct(struct dc *dc,
 	if (!create_links(dc, init_params->num_virtual_links))
 		goto fail;
 
+	/* Initialise DIG link encoder resource tracking variables. */
+	link_enc_cfg_init(dc, dc->current_state);
+
 	return true;
 
 fail:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2cfb53387c55..719fc6b502b6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -92,11 +92,14 @@ static void dc_link_destruct(struct dc_link *link)
 		link->panel_cntl->funcs->destroy(&link->panel_cntl);
 
 	if (link->link_enc) {
-		/* Update link encoder tracking variables. These are used for the dynamic
-		 * assignment of link encoders to streams.
+		/* Update link encoder resource tracking variables. These are used for
+		 * the dynamic assignment of link encoders to streams. Virtual links
+		 * are not assigned encoder resources on creation.
 		 */
-		link->dc->res_pool->link_encoders[link->link_enc->preferred_engine] = NULL;
-		link->dc->res_pool->dig_link_enc_count--;
+		if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
+			link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
+			link->dc->res_pool->dig_link_enc_count--;
+		}
 		link->link_enc->funcs->destroy(&link->link_enc);
 	}
 
@@ -1409,6 +1412,8 @@ static bool dc_link_construct(struct dc_link *link,
 	link->link_id =
 		bios->funcs->get_connector_id(bios, init_params->connector_index);
 
+	link->ep_type = DISPLAY_ENDPOINT_PHY;
+
 	DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
 
 	if (bios->funcs->get_disp_connector_caps_info) {
@@ -1547,7 +1552,8 @@ static bool dc_link_construct(struct dc_link *link,
 	/* Update link encoder tracking variables. These are used for the dynamic
 	 * assignment of link encoders to streams.
 	 */
-	link->dc->res_pool->link_encoders[link->link_enc->preferred_engine] = link->link_enc;
+	link->eng_id = link->link_enc->preferred_engine;
+	link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
 	link->dc->res_pool->dig_link_enc_count++;
 
 	link->link_enc_hw_inst = link->link_enc->transmitter;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
new file mode 100644
index 000000000000..c2bf9e5d9675
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "link_enc_cfg.h"
+#include "resource.h"
+#include "dc_link_dp.h"
+
+/* Check whether stream is supported by DIG link encoders. */
+static bool is_dig_link_enc_stream(struct dc_stream_state *stream)
+{
+	bool is_dig_stream = false;
+	struct link_encoder *link_enc = NULL;
+	int i;
+
+	/* Loop over created link encoder objects. */
+	for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
+		link_enc = stream->ctx->dc->res_pool->link_encoders[i];
+
+		if (link_enc &&
+				((uint32_t)stream->signal & link_enc->output_signals)) {
+			if (dc_is_dp_signal(stream->signal)) {
+				/* DIGs do not support DP2.0 streams with 128b/132b encoding. */
+				struct dc_link_settings link_settings = {0};
+
+				decide_link_settings(stream, &link_settings);
+				if ((link_settings.link_rate >= LINK_RATE_LOW) &&
+						link_settings.link_rate <= LINK_RATE_HIGH3) {
+					is_dig_stream = true;
+					break;
+				}
+			} else {
+				is_dig_stream = true;
+				break;
+			}
+		}
+	}
+
+	return is_dig_stream;
+}
+
+/* Update DIG link encoder resource tracking variables in dc_state. */
+static void update_link_enc_assignment(
+		struct dc_state *state,
+		struct dc_stream_state *stream,
+		enum engine_id eng_id,
+		bool add_enc)
+{
+	int eng_idx;
+	int stream_idx;
+	int i;
+
+	if (eng_id != ENGINE_ID_UNKNOWN) {
+		eng_idx = eng_id - ENGINE_ID_DIGA;
+		stream_idx = -1;
+
+		/* Index of stream in dc_state used to update correct entry in
+		 * link_enc_assignments table.
+		 */
+		for (i = 0; i < state->stream_count; i++) {
+			if (stream == state->streams[i]) {
+				stream_idx = i;
+				break;
+			}
+		}
+
+		/* Update link encoder assignments table, link encoder availability
+		 * pool and link encoder assigned to stream in state.
+		 * Add/remove encoder resource to/from stream.
+		 */
+		if (stream_idx != -1) {
+			if (add_enc) {
+				state->res_ctx.link_enc_assignments[stream_idx] = (struct link_enc_assignment){
+					.valid = true,
+					.ep_id = (struct display_endpoint_id) {
+						.link_id = stream->link->link_id,
+						.ep_type = stream->link->ep_type},
+					.eng_id = eng_id};
+				state->res_ctx.link_enc_avail[eng_idx] = ENGINE_ID_UNKNOWN;
+				stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx];
+			} else {
+				state->res_ctx.link_enc_assignments[stream_idx].valid = false;
+				state->res_ctx.link_enc_avail[eng_idx] = eng_id;
+				stream->link_enc = NULL;
+			}
+		} else {
+			dm_output_to_console("%s: Stream not found in dc_state.\n", __func__);
+		}
+	}
+}
+
+/* Return first available DIG link encoder. */
+static enum engine_id find_first_avail_link_enc(
+		struct dc_context *ctx,
+		struct dc_state *state)
+{
+	enum engine_id eng_id = ENGINE_ID_UNKNOWN;
+	int i;
+
+	for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
+		eng_id = state->res_ctx.link_enc_avail[i];
+		if (eng_id != ENGINE_ID_UNKNOWN)
+			break;
+	}
+
+	return eng_id;
+}
+
+void link_enc_cfg_init(
+		struct dc *dc,
+		struct dc_state *state)
+{
+	int i;
+
+	for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) {
+		if (dc->res_pool->link_encoders[i])
+			state->res_ctx.link_enc_avail[i] = (enum engine_id) i;
+		else
+			state->res_ctx.link_enc_avail[i] = ENGINE_ID_UNKNOWN;
+	}
+}
+
+void link_enc_cfg_link_encs_assign(
+		struct dc *dc,
+		struct dc_state *state,
+		struct dc_stream_state *streams[],
+		uint8_t stream_count)
+{
+	enum engine_id eng_id = ENGINE_ID_UNKNOWN;
+	int i;
+
+	/* Release DIG link encoder resources before running assignment algorithm. */
+	for (i = 0; i < stream_count; i++)
+		dc->res_pool->funcs->link_enc_unassign(state, streams[i]);
+
+	/* (a) Assign DIG link encoders to physical (unmappable) endpoints first. */
+	for (i = 0; i < stream_count; i++) {
+		struct dc_stream_state *stream = streams[i];
+
+		/* Skip stream if not supported by DIG link encoder. */
+		if (!is_dig_link_enc_stream(stream))
+			continue;
+
+		/* Physical endpoints have a fixed mapping to DIG link encoders. */
+		if (!stream->link->is_dig_mapping_flexible) {
+			eng_id = stream->link->eng_id;
+			update_link_enc_assignment(state, stream, eng_id, true);
+		}
+	}
+
+	/* (b) Then assign encoders to mappable endpoints. */
+	eng_id = ENGINE_ID_UNKNOWN;
+
+	for (i = 0; i < stream_count; i++) {
+		struct dc_stream_state *stream = streams[i];
+
+		/* Skip stream if not supported by DIG link encoder. */
+		if (!is_dig_link_enc_stream(stream))
+			continue;
+
+		/* Mappable endpoints have a flexible mapping to DIG link encoders. */
+		if (stream->link->is_dig_mapping_flexible) {
+			eng_id = find_first_avail_link_enc(stream->ctx, state);
+			update_link_enc_assignment(state, stream, eng_id, true);
+		}
+	}
+}
+
+void link_enc_cfg_link_enc_unassign(
+		struct dc_state *state,
+		struct dc_stream_state *stream)
+{
+	enum engine_id eng_id = ENGINE_ID_UNKNOWN;
+
+	/* Only DIG link encoders. */
+	if (!is_dig_link_enc_stream(stream))
+		return;
+
+	if (stream->link_enc)
+		eng_id = stream->link_enc->preferred_engine;
+
+	update_link_enc_assignment(state, stream, eng_id, false);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 3c91d16c2710..ac7a75887f95 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1930,6 +1930,9 @@ enum dc_status dc_remove_stream_from_ctx(
 				dc->res_pool,
 			del_pipe->stream_res.stream_enc,
 			false);
+	/* Release link encoder from stream in new dc_state. */
+	if (dc->res_pool->funcs->link_enc_unassign)
+		dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
 
 	if (del_pipe->stream_res.audio)
 		update_audio_usage(
@@ -2842,6 +2845,10 @@ bool pipe_need_reprogram(
 	if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
 		return true;
 
+	/* DIG link encoder resource assignment for stream changed. */
+	if (pipe_ctx_old->stream->link_enc != pipe_ctx->stream->link_enc)
+		return true;
+
 	return false;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 7b927e634279..b0013e674864 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -132,6 +132,11 @@ struct dc_link {
 	uint8_t hpd_src;
 
 	uint8_t link_enc_hw_inst;
+	/* DIG link encoder ID. Used as index in link encoder resource pool.
+	 * For links with fixed mapping to DIG, this is not changed after dc_link
+	 * object creation.
+	 */
+	enum engine_id eng_id;
 
 	bool test_pattern_enabled;
 	union compliance_test_state compliance_test_state;
@@ -151,6 +156,11 @@ struct dc_link {
 	struct panel_cntl *panel_cntl;
 	struct link_encoder *link_enc;
 	struct graphics_object_id link_id;
+	/* Endpoint type distinguishes display endpoints which do not have entries
+	 * in the BIOS connector table from those that do. Helps when tracking link
+	 * encoder to display endpoint assignments.
+	 */
+	enum display_endpoint_type ep_type;
 	union ddi_channel_mapping ddi_channel_mapping;
 	struct connector_device_tag_info device_tag;
 	struct dpcd_caps dpcd_caps;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index e747370fc43b..2bc057e0b447 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -136,6 +136,10 @@ struct dc_stream_state {
 	struct dc_sink *sink;
 
 	struct dc_link *link;
+	/* For dynamic link encoder assignment, update the link encoder assigned to
+	 * a stream via the volatile dc_state rather than the static dc_link.
+	 */
+	struct link_encoder *link_enc;
 	struct dc_panel_patch sink_patches;
 	union display_content_support content_support;
 	struct dc_crtc_timing timing;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 80757a0ea7c6..b5e875ee9027 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -934,4 +934,19 @@ enum dc_psr_version {
 	DC_PSR_VERSION_UNSUPPORTED		= 0xFFFFFFFF,
 };
 
+/* Possible values of display_endpoint_id.endpoint */
+enum display_endpoint_type {
+	DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
+	DISPLAY_ENDPOINT_UNKNOWN = -1
+};
+
+/* Extends graphics_object_id with an additional member 'ep_type' for
+ * distinguishing between physical endpoints (with entries in BIOS connector table) and
+ * logical endpoints.
+ */
+struct display_endpoint_id {
+	struct graphics_object_id link_id;
+	enum display_endpoint_type ep_type;
+};
+
 #endif /* DC_TYPES_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index eb1a19bf0d81..81b92f20d5b6 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -118,6 +118,27 @@ struct resource_funcs {
 		display_e2e_pipe_params_st *pipes,
 		bool fast_validate);
 
+	/*
+	 * Algorithm for assigning available link encoders to links.
+	 *
+	 * Update link_enc_assignments table and link_enc_avail list accordingly in
+	 * struct resource_context.
+	 */
+	void (*link_encs_assign)(
+			struct dc *dc,
+			struct dc_state *state,
+			struct dc_stream_state *streams[],
+			uint8_t stream_count);
+	/*
+	 * Unassign a link encoder from a stream.
+	 *
+	 * Update link_enc_assignments table and link_enc_avail list accordingly in
+	 * struct resource_context.
+	 */
+	void (*link_enc_unassign)(
+			struct dc_state *state,
+			struct dc_stream_state *stream);
+
 	enum dc_status (*validate_global)(
 		struct dc *dc,
 		struct dc_state *context);
@@ -358,6 +379,12 @@ struct resource_context {
 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
 	uint8_t dp_clock_source_ref_count;
 	bool is_dsc_acquired[MAX_PIPES];
+	/* A table/array of encoder-to-link assignments. One entry per stream.
+	 * Indexed by stream index in dc_state.
+	 */
+	struct link_enc_assignment link_enc_assignments[MAX_PIPES];
+	/* List of available link encoders. Uses engine ID as encoder identifier. */
+	enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool is_mpc_3dlut_acquired[MAX_PIPES];
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 7f5acd8fb918..80bc99500645 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -187,4 +187,17 @@ struct link_encoder_funcs {
 		struct link_encoder *enc);
 };
 
+/*
+ * Used to track assignments of links (display endpoints) to link encoders.
+ *
+ * Entry in link_enc_assignments table in struct resource_context.
+ * Entries only marked valid once encoder assigned to a link and invalidated once unassigned.
+ * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint.
+ */
+struct link_enc_assignment {
+	bool valid;
+	struct display_endpoint_id ep_id;
+	enum engine_id eng_id;
+};
+
 #endif /* LINK_ENCODER_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
new file mode 100644
index 000000000000..ad641632eadd
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DC_INC_LINK_ENC_CFG_H_
+#define DC_INC_LINK_ENC_CFG_H_
+
+/* This module implements functionality for dynamically assigning DIG link
+ * encoder resources to display endpoints (links).
+ */
+
+#include "core_types.h"
+
+/*
+ * Initialise link encoder resource tracking.
+ */
+void link_enc_cfg_init(
+		struct dc *dc,
+		struct dc_state *state);
+
+/*
+ * Algorithm for assigning available DIG link encoders to streams.
+ *
+ * Update link_enc_assignments table and link_enc_avail list accordingly in
+ * struct resource_context.
+ *
+ * Loop over all streams twice:
+ * a) First assign encoders to unmappable endpoints.
+ * b) Then assign encoders to mappable endpoints.
+ */
+void link_enc_cfg_link_encs_assign(
+		struct dc *dc,
+		struct dc_state *state,
+		struct dc_stream_state *streams[],
+		uint8_t stream_count);
+
+/*
+ * Unassign a link encoder from a stream.
+ *
+ * Update link_enc_assignments table and link_enc_avail list accordingly in
+ * struct resource_context.
+ */
+void link_enc_cfg_link_enc_unassign(
+		struct dc_state *state,
+		struct dc_stream_state *stream);
+
+#endif /* DC_INC_LINK_ENC_CFG_H_ */
-- 
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 15/21] drm/amd/display: Update display endpoint control path.

[Anson Jacob]

From: Jimmy Kizito <Jimmy.Kizito@amd.com>

[Why]
Some display endpoints may be dynamically mapped to the link encoders
which drive them.

[How]
Update the code paths for display enabling/disabling to accommodate
the dynamic association between links and link encoders.

Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 15 ++-
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 99 +++++++++++++++++++
 .../drm/amd/display/dc/core/dc_link_hwss.c    | 22 ++++-
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 18 ++++
 4 files changed, 146 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cebf68200f43..0b8082a15e24 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1728,11 +1728,16 @@ bool perform_link_training_with_retries(
 		if (link->aux_access_disabled) {
 			dc_link_dp_perform_link_training_skip_aux(link, link_setting);
 			return true;
-		} else if (dc_link_dp_perform_link_training(
-				link,
-				link_setting,
-				skip_video_pattern) == LINK_TRAINING_SUCCESS)
-			return true;
+		} else {
+			enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
+
+				status = dc_link_dp_perform_link_training(
+										link,
+										link_setting,
+										skip_video_pattern);
+			if (status == LINK_TRAINING_SUCCESS)
+				return true;
+		}
 
 		/* latest link training still fail, skip delay and keep PHY on
 		 */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index c2bf9e5d9675..1361b87d86d7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -127,6 +127,32 @@ static enum engine_id find_first_avail_link_enc(
 	return eng_id;
 }
 
+/* Return stream using DIG link encoder resource. NULL if unused. */
+static struct dc_stream_state *get_stream_using_link_enc(
+		struct dc_state *state,
+		enum engine_id eng_id)
+{
+	struct dc_stream_state *stream = NULL;
+	int stream_idx = -1;
+	int i;
+
+	for (i = 0; i < state->stream_count; i++) {
+		struct link_enc_assignment assignment = state->res_ctx.link_enc_assignments[i];
+
+		if (assignment.valid && (assignment.eng_id == eng_id)) {
+			stream_idx = i;
+			break;
+		}
+	}
+
+	if (stream_idx != -1)
+		stream = state->streams[stream_idx];
+	else
+		dm_output_to_console("%s: No stream using DIG(%d).\n", __func__, eng_id);
+
+	return stream;
+}
+
 void link_enc_cfg_init(
 		struct dc *dc,
 		struct dc_state *state)
@@ -202,3 +228,76 @@ void link_enc_cfg_link_enc_unassign(
 
 	update_link_enc_assignment(state, stream, eng_id, false);
 }
+
+bool link_enc_cfg_is_transmitter_mappable(
+		struct dc_state *state,
+		struct link_encoder *link_enc)
+{
+	bool is_mappable = false;
+	enum engine_id eng_id = link_enc->preferred_engine;
+	struct dc_stream_state *stream = get_stream_using_link_enc(state, eng_id);
+
+	if (stream)
+		is_mappable = stream->link->is_dig_mapping_flexible;
+
+	return is_mappable;
+}
+
+struct dc_link *link_enc_cfg_get_link_using_link_enc(
+		struct dc_state *state,
+		enum engine_id eng_id)
+{
+	struct dc_link *link = NULL;
+	int stream_idx = -1;
+	int i;
+
+	for (i = 0; i < state->stream_count; i++) {
+		struct link_enc_assignment assignment = state->res_ctx.link_enc_assignments[i];
+
+		if (assignment.valid && (assignment.eng_id == eng_id)) {
+			stream_idx = i;
+			break;
+		}
+	}
+
+	if (stream_idx != -1)
+		link = state->streams[stream_idx]->link;
+	else
+		dm_output_to_console("%s: No link using DIG(%d).\n", __func__, eng_id);
+
+	return link;
+}
+
+struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(
+		struct dc_state *state,
+		struct dc_link *link)
+{
+	struct link_encoder *link_enc = NULL;
+	struct display_endpoint_id ep_id;
+	int stream_idx = -1;
+	int i;
+
+	ep_id = (struct display_endpoint_id) {
+		.link_id = link->link_id,
+		.ep_type = link->ep_type};
+
+	for (i = 0; i < state->stream_count; i++) {
+		struct link_enc_assignment assignment = state->res_ctx.link_enc_assignments[i];
+
+		if (assignment.valid &&
+				assignment.ep_id.link_id.id == ep_id.link_id.id &&
+				assignment.ep_id.link_id.enum_id == ep_id.link_id.enum_id &&
+				assignment.ep_id.link_id.type == ep_id.link_id.type &&
+				assignment.ep_id.ep_type == ep_id.ep_type) {
+			stream_idx = i;
+			break;
+		}
+	}
+
+	if (stream_idx != -1)
+		link_enc = state->streams[stream_idx]->link_enc;
+	else
+		dm_output_to_console("%s: No link encoder used by link(%d).\n", __func__, link->link_index);
+
+	return link_enc;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 22fe19ee842d..48ad1a8d4a74 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -14,6 +14,7 @@
 #include "dpcd_defs.h"
 #include "dsc.h"
 #include "resource.h"
+#include "link_enc_cfg.h"
 #include "clk_mgr.h"
 
 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
@@ -95,7 +96,7 @@ void dp_enable_link_phy(
 	enum clock_source_id clock_source,
 	const struct dc_link_settings *link_settings)
 {
-	struct link_encoder *link_enc = link->link_enc;
+	struct link_encoder *link_enc;
 	struct dc  *dc = link->ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 
@@ -105,6 +106,13 @@ void dp_enable_link_phy(
 			link->dc->res_pool->dp_clock_source;
 	unsigned int i;
 
+	/* Link should always be assigned encoder when en-/disabling. */
+	if (link->is_dig_mapping_flexible && dc->res_pool->funcs->link_encs_assign)
+		link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+	else
+		link_enc = link->link_enc;
+	ASSERT(link_enc);
+
 	if (link->connector_signal == SIGNAL_TYPE_EDP) {
 		link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
@@ -227,6 +235,14 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 {
 	struct dc  *dc = link->ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
+	struct link_encoder *link_enc;
+
+	/* Link should always be assigned encoder when en-/disabling. */
+	if (link->is_dig_mapping_flexible && dc->res_pool->funcs->link_encs_assign)
+		link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+	else
+		link_enc = link->link_enc;
+	ASSERT(link_enc);
 
 	if (!link->wa_flags.dp_keep_receiver_powered)
 		dp_receiver_power_ctrl(link, false);
@@ -234,13 +250,13 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
 	if (signal == SIGNAL_TYPE_EDP) {
 		if (link->dc->hwss.edp_backlight_control)
 			link->dc->hwss.edp_backlight_control(link, false);
-		link->link_enc->funcs->disable_output(link->link_enc, signal);
+		link_enc->funcs->disable_output(link_enc, signal);
 		link->dc->hwss.edp_power_control(link, false);
 	} else {
 		if (dmcu != NULL && dmcu->funcs->lock_phy)
 			dmcu->funcs->lock_phy(dmcu);
 
-		link->link_enc->funcs->disable_output(link->link_enc, signal);
+		link_enc->funcs->disable_output(link_enc, signal);
 
 		if (dmcu != NULL && dmcu->funcs->unlock_phy)
 			dmcu->funcs->unlock_phy(dmcu);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
index ad641632eadd..7d36e55f3097 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -65,4 +65,22 @@ void link_enc_cfg_link_enc_unassign(
 		struct dc_state *state,
 		struct dc_stream_state *stream);
 
+/*
+ * Check whether the transmitter driven by a link encoder is a mappable
+ * endpoint.
+ */
+bool link_enc_cfg_is_transmitter_mappable(
+		struct dc_state *state,
+		struct link_encoder *link_enc);
+
+/* Return link using DIG link encoder resource. NULL if unused. */
+struct dc_link *link_enc_cfg_get_link_using_link_enc(
+		struct dc_state *state,
+		enum engine_id eng_id);
+
+/* Return DIG link encoder used by link. NULL if unused. */
+struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(
+		struct dc_state *state,
+		struct dc_link *link);
+
 #endif /* DC_INC_LINK_ENC_CFG_H_ */
-- 
2.25.1

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[PATCH 16/21] drm/amd/display: New path for enabling DPG

[Anson Jacob]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
We want to make enabling test pattern a part of the
stream update code path. This change is the first step
towards that goal.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 11 +++++++++++
 drivers/gpu/drm/amd/display/dc/dc_stream.h | 12 ++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 12cb95c5a1f9..7a0f5057f0ff 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2394,6 +2394,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	if (update->dither_option)
 		stream->dither_option = *update->dither_option;
 
+	if (update->pending_test_pattern)
+		stream->test_pattern = *update->pending_test_pattern;
 	/* update current stream with writeback info */
 	if (update->wb_update) {
 		int i;
@@ -2489,6 +2491,15 @@ static void commit_planes_do_stream_update(struct dc *dc,
 				}
 			}
 
+			if (stream_update->pending_test_pattern) {
+				dc_link_dp_set_test_pattern(stream->link,
+					stream->test_pattern.type,
+					stream->test_pattern.color_space,
+					stream->test_pattern.p_link_settings,
+					stream->test_pattern.p_custom_pattern,
+					stream->test_pattern.cust_pattern_size);
+			}
+
 			/* Full fe update*/
 			if (update_type == UPDATE_TYPE_FAST)
 				continue;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 2bc057e0b447..b0297f07f9de 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -130,6 +130,14 @@ union stream_update_flags {
 	uint32_t raw;
 };
 
+struct test_pattern {
+	enum dp_test_pattern type;
+	enum dp_test_pattern_color_space color_space;
+	struct link_training_settings const *p_link_settings;
+	unsigned char const *p_custom_pattern;
+	unsigned int cust_pattern_size;
+};
+
 struct dc_stream_state {
 	// sink is deprecated, new code should not reference
 	// this pointer
@@ -231,6 +239,8 @@ struct dc_stream_state {
 
 	uint32_t stream_id;
 	bool is_dsc_enabled;
+
+	struct test_pattern test_pattern;
 	union stream_update_flags update_flags;
 
 	bool has_non_synchronizable_pclk;
@@ -268,6 +278,8 @@ struct dc_stream_update {
 	struct dc_dsc_config *dsc_config;
 	struct dc_transfer_func *func_shaper;
 	struct dc_3dlut *lut3d_func;
+
+	struct test_pattern *pending_test_pattern;
 };
 
 bool dc_is_stream_unchanged(
-- 
2.25.1

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[PATCH 17/21] drm/amd/display: Set max TTU on DPG enable

[Anson Jacob]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
There is a bug in HW that causes P-State to hang when DPG is enabled in
certain conditions.

[HOW]
The solution is to force MIN_TTU_VBLANK register to maximum value
whenever DPG has been enabled.
Make stream do a full update on test pattern change, so that the TTUs
get updated.
When DPG is enabled, update the ttu_regs.min_ttu_vblank field of each
pipe in the stream's topology to the maximum value (0xffffff).

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c     | 30 +++++++++++++++-----
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h |  1 +
 2 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7a0f5057f0ff..a241b42a2fbb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -49,6 +49,7 @@
 #include "timing_generator.h"
 #include "abm.h"
 #include "virtual/virtual_link_encoder.h"
+#include "hubp.h"
 
 #include "link_hwss.h"
 #include "link_encoder.h"
@@ -2095,6 +2096,10 @@ static enum surface_update_type check_update_surfaces_for_stream(
 	if (stream_status == NULL || stream_status->plane_count != surface_count)
 		overall_type = UPDATE_TYPE_FULL;
 
+	if (stream_update && stream_update->pending_test_pattern) {
+		overall_type = UPDATE_TYPE_FULL;
+	}
+
 	/* some stream updates require passive update */
 	if (stream_update) {
 		union stream_update_flags *su_flags = &stream_update->stream->update_flags;
@@ -2491,6 +2496,14 @@ static void commit_planes_do_stream_update(struct dc *dc,
 				}
 			}
 
+
+			/* Full fe update*/
+			if (update_type == UPDATE_TYPE_FAST)
+				continue;
+
+			if (stream_update->dsc_config)
+				dp_update_dsc_config(pipe_ctx);
+
 			if (stream_update->pending_test_pattern) {
 				dc_link_dp_set_test_pattern(stream->link,
 					stream->test_pattern.type,
@@ -2500,13 +2513,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
 					stream->test_pattern.cust_pattern_size);
 			}
 
-			/* Full fe update*/
-			if (update_type == UPDATE_TYPE_FAST)
-				continue;
-
-			if (stream_update->dsc_config)
-				dp_update_dsc_config(pipe_ctx);
-
 			if (stream_update->dpms_off) {
 				if (*stream_update->dpms_off) {
 					core_link_disable_stream(pipe_ctx);
@@ -2593,6 +2599,16 @@ static void commit_planes_for_stream(struct dc *dc,
 		}
 	}
 
+	if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
+		struct pipe_ctx *mpcc_pipe;
+		struct pipe_ctx *odm_pipe;
+
+		for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
+			for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+				odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
+	}
+
+
 	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
 		if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
 			if (should_use_dmub_lock(stream->link)) {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 346dcd87dc10..80e1a32bc63d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -29,6 +29,7 @@
 #include "mem_input.h"
 
 #define OPP_ID_INVALID 0xf
+#define MAX_TTU 0xffffff
 
 
 enum cursor_pitch {
-- 
2.25.1

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[PATCH 18/21] drm/amd/display: add log for automated test

[Anson Jacob]

From: Qingqing Zhuo <qingqing.zhuo@amd.com>

[Why&How]
Add log for easier debug purposes.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0b8082a15e24..7d2e433c2275 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2902,6 +2902,10 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
 
 	if (requestColorDepth != COLOR_DEPTH_UNDEFINED
 			&& pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
+		DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
+				__func__,
+				pipe_ctx->stream->timing.display_color_depth,
+				requestColorDepth);
 		pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
 		dp_update_dsc_config(pipe_ctx);
 	}
-- 
2.25.1

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[PATCH 19/21] drm/amd/display: [FW Promotion] Release 0.0.58

[Anson Jacob]

From: Anthony Koo <Anthony.Koo@amd.com>

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 2d23462f4980..c5776a55e2a5 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x899019e5c
+#define DMUB_FW_VERSION_GIT_HASH 0x8bb402f5a
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 57
+#define DMUB_FW_VERSION_REVISION 58
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
-- 
2.25.1

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[PATCH 20/21] drm/amd/display: Disable MALL when SMU not present

[Anson Jacob]

From: Chris Park <Chris.Park@amd.com>

[Why]
Bring-up purpose code to disable DMUB calling into
SMU and timeout for MALL when SMU is not present.

[How]
Disable MALL when SMU is not present.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c   | 7 +++++++
 drivers/gpu/drm/amd/display/dc/core/dc.c                   | 4 ++++
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h            | 3 +++
 3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 81ea5d3a1947..577e7f97045e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -432,6 +432,12 @@ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
 			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
 }
 
+static bool dcn3_is_smu_prsent(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	return clk_mgr->smu_present;
+}
+
 static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
 					struct dc_clocks *b)
 {
@@ -494,6 +500,7 @@ static struct clk_mgr_funcs dcn3_funcs = {
 		.are_clock_states_equal = dcn3_are_clock_states_equal,
 		.enable_pme_wa = dcn3_enable_pme_wa,
 		.notify_link_rate_change = dcn30_notify_link_rate_change,
+		.is_smu_present = dcn3_is_smu_prsent
 };
 
 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a241b42a2fbb..d9ab134a178f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3256,6 +3256,10 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
 	if (dc->debug.disable_idle_power_optimizations)
 		return;
 
+	if (dc->clk_mgr->funcs->is_smu_present)
+		if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
+			return;
+
 	if (allow == dc->idle_optimizations_allowed)
 		return;
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 4e94f2dec572..5dc8d02b40c3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -262,6 +262,9 @@ struct clk_mgr_funcs {
 
 	/* Get current memclk states from PMFW, update relevant structures */
 	void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
+
+	/* Get SMU present */
+	bool (*is_smu_present)(struct clk_mgr *clk_mgr);
 };
 
 struct clk_mgr {
-- 
2.25.1

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[PATCH 21/21] drm/amd/display: 3.2.129

[Anson Jacob]

From: Aric Cyr <aric.cyr@amd.com>

This version brings along following features/fixes:
- LTTPR improvements
- Disable MALL when SMU not present
- Fix bug in HW that causes P-State to hang when DPG is enabled in
  certain conditions
- Update code path for enabling DPG
- Update display endpoint control path
- Add dynamic link encoder selection
- Fix debugfs MST topology to dump from the root MST node
- Enable DP DSC Compliance automation for Linux
- ASSR is enabled only when DPCD is supported and the display
  connected is internal
- Added kernel trace event to print real-time refresh rate value
  to debug VRR issues

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 55f3c76823d8..8b725347e2ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
 /* forward declaration */
 struct aux_payload;
 
-#define DC_VER "3.2.128"
+#define DC_VER "3.2.129"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

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RE: [PATCH 00/21] DC Patches March 26, 2021

[Wheeler, Daniel]

[AMD Public Use]

Hi all,

This week this patchset was tested on a HP Envy 360, with Ryzen 5 4500U, on the following display types (via usb-c to dp/dvi/hdmi/vga):
4k 60z, 1440p 144hz, 1680*1050 60hz, internal eDP 1080p 60hz

Tested on a Sapphire Pulse RX5700XT on the following display types (via DP):
4k60 60hz, 1440p 144hz, 1680x1050 60hz.

Also tested on a Reference AMD RX6800 on the following display types (via DP):
4k60 60hz, 1440p 144hz. 

Tested using a MST hub at 2x 4k 30hz on all systems.

Tested by Dan Wheeler <daniel.wheeler@amd.com>

Thank you,

Dan Wheeler
Technologist  |  AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook |  Twitter |  amd.com  


-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Anson Jacob
Sent: March 26, 2021 6:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Jacob, Anson <Anson.Jacob@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; R, Bindu <Bindu.R@amd.com>
Subject: [PATCH 00/21] DC Patches March 26, 2021

This patchset brings along following features/fixes:
    - LTTPR improvements
    - Disable MALL when SMU not present
    - Fix bug in HW that causes P-State to hang when DPG is enabled in
      certain conditions
    - Update code path for enabling DPG
    - Update display endpoint control path
    - Add dynamic link encoder selection
    - Fix debugfs MST topology to dump from the root MST node
    - Enable DP DSC Compliance automation for Linux
    - ASSR is enabled only when DPCD is supported and the display
      connected is internal
    - Added kernel trace event to print real-time refresh rate value
      to debug VRR issues

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.58

Aric Cyr (1):
  drm/amd/display: 3.2.129

Chris Park (1):
  drm/amd/display: Disable MALL when SMU not present

Eryk Brol (1):
  drm/amd/display: Fix MST topology debugfs

Jimmy Kizito (2):
  drm/amd/display: Add dynamic link encoder selection.
  drm/amd/display: Update display endpoint control path.

Krunoslav Kovac (1):
  drm/amd/display: Rename fs_params to hdr_tm_params

Leo (Hanghong) Ma (1):
  drm/amd/display: Fix static checker warnings on tracebuff_fb

Qingqing Zhuo (2):
  drm/amd/display: enable DP DSC Compliance automation
  drm/amd/display: add log for automated test

Rodrigo Siqueira (1):
  drm/amd/display: Add refresh rate trace

Stylon Wang (1):
  drm/amd/display: Guard ASSR with internal display flag

Vladimir Stempen (1):
  drm/amd/display: Fix typo for variable name

Wenjing Liu (2):
  drm/amd/display: define mod_hdcp_display_disable_option struct
  drm/amd/display: add mod hdcp interface for supporting encryption
    state query

Wesley Chalmers (6):
  drm/amd/display: BIOS LTTPR Caps Interface
  drm/amd/display: Interface for LTTPR interop
  drm/amd/display: Enumerate LTTPR modes
  drm/amd/display: LTTPR config logic
  drm/amd/display: New path for enabling DPG
  drm/amd/display: Set max TTU on DPG enable

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  14 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |   4 +
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    |   6 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_trace.h   |  19 ++
 drivers/gpu/drm/amd/display/dc/Makefile       |   5 +-
 .../drm/amd/display/dc/bios/bios_parser2.c    | 190 +++++++++++
 .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  |   7 +
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  35 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  16 +-  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 197 +++++++++---  .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 303 ++++++++++++++++++
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  24 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   7 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   2 +-
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |   6 +
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  19 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  16 +
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  15 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  10 +-
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  27 ++
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  13 +  .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |  86 +++++
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 142 ++++----
 .../amd/display/modules/color/color_gamma.c   |   6 +-
 .../amd/display/modules/color/color_gamma.h   |   4 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |  10 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   |   4 +-
 .../display/modules/hdcp/hdcp1_execution.c    |  37 ++-
 .../display/modules/hdcp/hdcp1_transition.c   |   6 +-
 .../display/modules/hdcp/hdcp2_execution.c    |  10 +-
 .../display/modules/hdcp/hdcp2_transition.c   |  10 +-
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   |  10 +
 .../drm/amd/display/modules/inc/mod_hdcp.h    |  10 +-
 drivers/gpu/drm/amd/include/atomfirmware.h    |  38 ++-
 38 files changed, 1141 insertions(+), 176 deletions(-)  create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h

--
2.25.1

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