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From: Jingyi Wang <wangjingyi11@huawei.com>
To: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: <maz@kernel.org>, <tglx@linutronix.de>,
	<wanghaibin.wang@huawei.com>, <wangjingyi11@huawei.com>,
	<yuzenghui@huawei.com>, <zhukeqian1@huawei.com>
Subject: [RFC PATCH 1/3] irqchip/gic-v3: Make use of ICC_SGI1R IRM bit
Date: Mon, 29 Mar 2021 16:52:08 +0800	[thread overview]
Message-ID: <20210329085210.11524-2-wangjingyi11@huawei.com> (raw)
In-Reply-To: <20210329085210.11524-1-wangjingyi11@huawei.com>

IRM, bit[40] in ICC_SGI1R, determines how the generated SGIs
are distributed to PEs. If the bit is set, interrupts are routed
to all PEs in the system excluding "self". We use cpumask to
determine if this bit should be set and make use of that.

This will reduce vm trap when broadcast IPIs are sent.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
 drivers/irqchip/irq-gic-v3.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index eb0ee356a629..8ecc1b274ea8 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1127,6 +1127,7 @@ static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 {
 	int cpu;
+	cpumask_t tmp;
 
 	if (WARN_ON(d->hwirq >= 16))
 		return;
@@ -1137,6 +1138,17 @@ static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 	 */
 	wmb();
 
+	if (!cpumask_and(&tmp, mask, cpumask_of(smp_processor_id()))) {
+		/* Set Interrupt Routing Mode bit */
+		u64 val;
+		val = (d->hwirq) << ICC_SGI1R_SGI_ID_SHIFT;
+		val |= BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
+		gic_write_sgi1r(val);
+
+		isb();
+		return;
+	}
+
 	for_each_cpu(cpu, mask) {
 		u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
 		u16 tlist;
-- 
2.19.1


WARNING: multiple messages have this Message-ID (diff)
From: Jingyi Wang <wangjingyi11@huawei.com>
To: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Cc: <maz@kernel.org>, <tglx@linutronix.de>,
	<wanghaibin.wang@huawei.com>, <wangjingyi11@huawei.com>,
	<yuzenghui@huawei.com>, <zhukeqian1@huawei.com>
Subject: [RFC PATCH 1/3] irqchip/gic-v3: Make use of ICC_SGI1R IRM bit
Date: Mon, 29 Mar 2021 16:52:08 +0800	[thread overview]
Message-ID: <20210329085210.11524-2-wangjingyi11@huawei.com> (raw)
In-Reply-To: <20210329085210.11524-1-wangjingyi11@huawei.com>

IRM, bit[40] in ICC_SGI1R, determines how the generated SGIs
are distributed to PEs. If the bit is set, interrupts are routed
to all PEs in the system excluding "self". We use cpumask to
determine if this bit should be set and make use of that.

This will reduce vm trap when broadcast IPIs are sent.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
 drivers/irqchip/irq-gic-v3.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index eb0ee356a629..8ecc1b274ea8 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1127,6 +1127,7 @@ static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 {
 	int cpu;
+	cpumask_t tmp;
 
 	if (WARN_ON(d->hwirq >= 16))
 		return;
@@ -1137,6 +1138,17 @@ static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
 	 */
 	wmb();
 
+	if (!cpumask_and(&tmp, mask, cpumask_of(smp_processor_id()))) {
+		/* Set Interrupt Routing Mode bit */
+		u64 val;
+		val = (d->hwirq) << ICC_SGI1R_SGI_ID_SHIFT;
+		val |= BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
+		gic_write_sgi1r(val);
+
+		isb();
+		return;
+	}
+
 	for_each_cpu(cpu, mask) {
 		u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
 		u16 tlist;
-- 
2.19.1


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  reply	other threads:[~2021-03-29  9:06 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-29  8:52 [RFC PATCH 0/3] arm: Some IPI injection optimization Jingyi Wang
2021-03-29  8:52 ` Jingyi Wang
2021-03-29  8:52 ` Jingyi Wang [this message]
2021-03-29  8:52   ` [RFC PATCH 1/3] irqchip/gic-v3: Make use of ICC_SGI1R IRM bit Jingyi Wang
2021-03-29  9:55   ` Marc Zyngier
2021-03-29  9:55     ` Marc Zyngier
2021-03-29 10:38     ` Jingyi Wang
2021-03-29 10:38       ` Jingyi Wang
2021-03-29 11:28       ` Marc Zyngier
2021-03-29 11:28         ` Marc Zyngier
2021-03-29  8:52 ` [RFC PATCH 2/3] irqchip/gic-v3: Implement gic_ipi_send_single() Jingyi Wang
2021-03-29  8:52   ` Jingyi Wang
2021-03-29  8:52 ` [RFC PATCH 3/3] arm/arm64: Use gic_ipi_send_single() to inject single IPI Jingyi Wang
2021-03-29  8:52   ` Jingyi Wang
2021-03-29 10:07   ` Marc Zyngier
2021-03-29 10:07     ` Marc Zyngier
2021-03-29 11:03     ` Jingyi Wang
2021-03-29 11:03       ` Jingyi Wang
2021-03-29 15:09   ` kernel test robot

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