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From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
	robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
	leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv4 5/6] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
Date: Tue,  6 Apr 2021 17:04:48 +0800	[thread overview]
Message-ID: <20210406090449.36352-6-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20210406090449.36352-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - Rebased against the latest code base

 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 46826752a691..704e9e249729 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -875,6 +875,7 @@
 			interrupts = <0 118 0x4>, /* controller interrupt */
 				     <0 117 0x4>; /* PME interrupt */
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -902,6 +903,7 @@
 			interrupts = <0 128 0x4>,
 				     <0 127 0x4>;
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -929,6 +931,7 @@
 			interrupts = <0 162 0x4>,
 				     <0 161 0x4>;
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 2>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
	robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
	leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv4 5/6] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes
Date: Tue,  6 Apr 2021 17:04:48 +0800	[thread overview]
Message-ID: <20210406090449.36352-6-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20210406090449.36352-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
 - Rebased against the latest code base

 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 46826752a691..704e9e249729 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -875,6 +875,7 @@
 			interrupts = <0 118 0x4>, /* controller interrupt */
 				     <0 117 0x4>; /* PME interrupt */
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -902,6 +903,7 @@
 			interrupts = <0 128 0x4>,
 				     <0 127 0x4>;
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -929,6 +931,7 @@
 			interrupts = <0 162 0x4>,
 				     <0 161 0x4>;
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 2>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.17.1


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  parent reply	other threads:[~2021-04-06  8:59 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-06  9:04 [PATCHv4 0/6] PCI: layerscape: Add power management support Zhiqiang Hou
2021-04-06  9:04 ` Zhiqiang Hou
2021-04-06  9:04 ` [PATCHv4 1/6] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou
2021-04-06  9:04   ` Zhiqiang Hou
2021-04-06  9:04 ` [PATCHv4 2/6] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Zhiqiang Hou
2021-04-06  9:04   ` Zhiqiang Hou
2021-04-06  9:04 ` [PATCHv4 3/6] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou
2021-04-06  9:04   ` Zhiqiang Hou
2021-04-06  9:04 ` [PATCHv4 4/6] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Zhiqiang Hou
2021-04-06  9:04   ` Zhiqiang Hou
2021-04-06  9:04 ` Zhiqiang Hou [this message]
2021-04-06  9:04   ` [PATCHv4 5/6] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Zhiqiang Hou
2021-04-06  9:04 ` [PATCHv4 6/6] PCI: layerscape: Add power management support Zhiqiang Hou
2021-04-06  9:04   ` Zhiqiang Hou
2021-04-06 19:57   ` kernel test robot

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