From: Greentime Hu <greentime.hu@sifive.com> To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v5 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver Date: Tue, 6 Apr 2021 17:26:30 +0800 [thread overview] Message-ID: <20210406092634.50465-3-greentime.hu@sifive.com> (raw) In-Reply-To: <20210406092634.50465-1-greentime.hu@sifive.com> We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c | 13 +++++++++++++ drivers/clk/sifive/sifive-prci.h | 4 ++++ drivers/reset/Kconfig | 1 + 4 files changed, 20 insertions(+) diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 1c14eb20c066..9132c3c4aa86 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -10,6 +10,8 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + select RESET_CONTROLLER + select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 8fdba5da2902..0704fddba6b9 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -583,6 +583,19 @@ static int sifive_prci_probe(struct platform_device *pdev) if (IS_ERR(pd->va)) return PTR_ERR(pd->va); + pd->reset.rcdev.owner = THIS_MODULE; + pd->reset.rcdev.nr_resets = PRCI_RST_NR; + pd->reset.rcdev.ops = &reset_simple_ops; + pd->reset.rcdev.of_node = pdev->dev.of_node; + pd->reset.active_low = true; + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; + spin_lock_init(&pd->reset.lock); + + r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); + if (r) { + dev_err(dev, "could not register reset controller: %d\n", r); + return r; + } r = __prci_register_clocks(dev, pd, desc); if (r) { dev_err(dev, "could not register clocks: %d\n", r); diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 022c67cf053c..91658a88af4e 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -11,6 +11,7 @@ #include <linux/clk/analogbits-wrpll-cln28hpc.h> #include <linux/clk-provider.h> +#include <linux/reset/reset-simple.h> #include <linux/platform_device.h> /* @@ -121,6 +122,8 @@ #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) +#define PRCI_RST_NR 7 + /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 @@ -221,6 +224,7 @@ */ struct __prci_data { void __iomem *va; + struct reset_simple_data reset; struct clk_hw_onecell_data hw_clks; }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..d0f5d0afc240 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com> To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v5 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver Date: Tue, 6 Apr 2021 17:26:30 +0800 [thread overview] Message-ID: <20210406092634.50465-3-greentime.hu@sifive.com> (raw) In-Reply-To: <20210406092634.50465-1-greentime.hu@sifive.com> We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c | 13 +++++++++++++ drivers/clk/sifive/sifive-prci.h | 4 ++++ drivers/reset/Kconfig | 1 + 4 files changed, 20 insertions(+) diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 1c14eb20c066..9132c3c4aa86 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -10,6 +10,8 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + select RESET_CONTROLLER + select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 8fdba5da2902..0704fddba6b9 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -583,6 +583,19 @@ static int sifive_prci_probe(struct platform_device *pdev) if (IS_ERR(pd->va)) return PTR_ERR(pd->va); + pd->reset.rcdev.owner = THIS_MODULE; + pd->reset.rcdev.nr_resets = PRCI_RST_NR; + pd->reset.rcdev.ops = &reset_simple_ops; + pd->reset.rcdev.of_node = pdev->dev.of_node; + pd->reset.active_low = true; + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; + spin_lock_init(&pd->reset.lock); + + r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); + if (r) { + dev_err(dev, "could not register reset controller: %d\n", r); + return r; + } r = __prci_register_clocks(dev, pd, desc); if (r) { dev_err(dev, "could not register clocks: %d\n", r); diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 022c67cf053c..91658a88af4e 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -11,6 +11,7 @@ #include <linux/clk/analogbits-wrpll-cln28hpc.h> #include <linux/clk-provider.h> +#include <linux/reset/reset-simple.h> #include <linux/platform_device.h> /* @@ -121,6 +122,8 @@ #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) +#define PRCI_RST_NR 7 + /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 @@ -221,6 +224,7 @@ */ struct __prci_data { void __iomem *va; + struct reset_simple_data reset; struct clk_hw_onecell_data hw_clks; }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..d0f5d0afc240 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-04-06 9:26 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-06 9:26 [PATCH v5 0/6] Add SiFive FU740 PCIe host controller driver support Greentime Hu 2021-04-06 9:26 ` Greentime Hu 2021-04-06 9:26 ` [PATCH v5 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver Greentime Hu 2021-04-06 9:26 ` Greentime Hu 2021-04-06 9:26 ` Greentime Hu [this message] 2021-04-06 9:26 ` [PATCH v5 2/6] clk: sifive: Use reset-simple " Greentime Hu 2021-04-06 9:26 ` [PATCH v5 3/6] MAINTAINERS: Add maintainers for SiFive FU740 " Greentime Hu 2021-04-06 9:26 ` Greentime Hu 2021-04-06 9:26 ` [PATCH v5 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller Greentime Hu 2021-04-06 9:26 ` Greentime Hu 2021-04-08 15:58 ` Rob Herring 2021-04-08 15:58 ` Rob Herring 2021-04-06 9:26 ` [PATCH v5 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver Greentime Hu 2021-04-06 9:26 ` Greentime Hu 2021-04-08 15:27 ` Rob Herring 2021-04-08 15:27 ` Rob Herring 2021-04-28 19:47 ` Bjorn Helgaas 2021-04-28 19:47 ` Bjorn Helgaas 2021-04-29 14:59 ` Lorenzo Pieralisi 2021-04-29 14:59 ` Lorenzo Pieralisi 2021-04-29 15:15 ` Bjorn Helgaas 2021-04-29 15:15 ` Bjorn Helgaas 2021-04-29 16:40 ` Lorenzo Pieralisi 2021-04-29 16:40 ` Lorenzo Pieralisi 2021-04-29 20:18 ` Bjorn Helgaas 2021-04-29 20:18 ` Bjorn Helgaas 2021-04-06 9:26 ` [PATCH v5 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC Greentime Hu 2021-04-06 9:26 ` Greentime Hu 2021-04-08 16:25 ` [PATCH v5 0/6] Add SiFive FU740 PCIe host controller driver support Lorenzo Pieralisi 2021-04-08 16:25 ` Lorenzo Pieralisi 2021-04-09 2:23 ` Greentime Hu 2021-04-09 2:23 ` Greentime Hu 2021-04-09 8:54 ` Lorenzo Pieralisi 2021-04-09 8:54 ` Lorenzo Pieralisi 2021-04-12 2:37 ` Greentime Hu 2021-04-12 2:37 ` Greentime Hu 2021-04-23 4:43 ` Palmer Dabbelt 2021-04-23 4:43 ` Palmer Dabbelt 2021-04-23 5:10 ` Palmer Dabbelt 2021-04-23 5:10 ` Palmer Dabbelt 2021-04-23 6:00 ` Greentime Hu 2021-04-23 6:00 ` Greentime Hu 2021-04-23 9:39 ` Lorenzo Pieralisi 2021-04-23 9:39 ` Lorenzo Pieralisi 2021-05-03 16:40 ` Bjorn Helgaas 2021-05-03 16:40 ` Bjorn Helgaas 2021-05-04 7:20 ` Greentime Hu 2021-05-04 7:20 ` Greentime Hu 2021-05-04 10:12 ` Lorenzo Pieralisi 2021-05-04 10:12 ` Lorenzo Pieralisi 2021-05-04 10:58 ` Greentime Hu 2021-05-04 10:58 ` Greentime Hu
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