[Buildroot] [PATCH 1/3] package/gcc: bump to version 10.3

* [Buildroot] [PATCH 1/3] package/gcc: bump to version 10.3
@ 2021-04-11  9:47 Romain Naour
  2021-04-11  9:47 ` [Buildroot] [PATCH 2/3] package/mpfr: bump to version 4.1.0 Romain Naour
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Romain Naour @ 2021-04-11  9:47 UTC (permalink / raw)
  To: buildroot

Remove upstream patch
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5aeabae7f0cdd8dd3a01103b68b2e7a66a71c685

Rebase the patch: Revert "re PR target/92095 (internal error with -O1 -mcpu=niagara2 -fPIE)"
Add the link to the bug report.

Tested with toolchain-builder:
https://gitlab.com/kubu93/toolchains-builder/-/pipelines/284176939

Signed-off-by: Romain Naour <romain.naour@gmail.com>
---
 .../0001-arc-Refurbish-adc-sbc-patterns.patch | 242 ------------------
 ...et-92095-internal-error-with-O1-mcp.patch} |  31 ++-
 package/gcc/Config.in.host                    |   2 +-
 package/gcc/gcc.hash                          |   4 +-
 4 files changed, 20 insertions(+), 259 deletions(-)
 delete mode 100644 package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch
 rename package/gcc/{10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch => 10.3.0/0001-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch} (93%)

diff --git a/package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch b/package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch
deleted file mode 100644
index ed7b000ede..0000000000
--- a/package/gcc/10.2.0/0001-arc-Refurbish-adc-sbc-patterns.patch
+++ /dev/null
@@ -1,242 +0,0 @@
-From 09944fba5bfb8e5543ce043c70d08222cf2f97ff Mon Sep 17 00:00:00 2001
-From: Claudiu Zissulescu <claziss@synopsys.com>
-Date: Wed, 11 Nov 2020 12:31:10 +0200
-Subject: [PATCH] arc: Refurbish adc/sbc patterns
-
-The adc/sbc patterns were unecessary spliting, remove that and
-associated functions.
-
-gcc/ChangeLog:
-
-2020-10-11  Claudiu Zissulescu  <claziss@synopsys.com>
-
-	* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
-	it.
-	(arc_sets_cc_p): Likewise.
-	(arc_need_delay): Likewise.
-	* config/arc/arc.c (arc_sets_cc_p): Likewise.
-	(arc_need_delay): Likewise.
-	(arc_scheduling_not_expected): Likewise.
-	* config/arc/arc.md: Convert adc/sbc patterns to simple
-	instruction definitions.
-
-Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
-Signed-off-by: Veronika Kremneva <kremneva@synopsys.com>
----
- gcc/config/arc/arc-protos.h |  3 --
- gcc/config/arc/arc.c        | 53 -------------------------
- gcc/config/arc/arc.md       | 95 ++++++++++++++-------------------------------
- 3 files changed, 29 insertions(+), 122 deletions(-)
-
-diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
-index c72d78e3b9e..de4cf47c818 100644
---- a/gcc/config/arc/arc-protos.h
-+++ b/gcc/config/arc/arc-protos.h
-@@ -90,10 +90,7 @@ extern void split_subsi (rtx *);
- extern void arc_split_move (rtx *);
- extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
- extern rtx arc_regno_use_in (unsigned int, rtx);
--extern bool arc_scheduling_not_expected (void);
--extern bool arc_sets_cc_p (rtx_insn *insn);
- extern int arc_label_align (rtx_insn *label);
--extern bool arc_need_delay (rtx_insn *insn);
- extern bool arc_text_label (rtx_insn *insn);
- 
- extern bool arc_short_comparison_p (rtx, int);
-diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
-index fcb83c4e23e..2daf83dd009 100644
---- a/gcc/config/arc/arc.c
-+++ b/gcc/config/arc/arc.c
-@@ -10341,59 +10341,6 @@ arc_attr_type (rtx_insn *insn)
-   return get_attr_type (insn);
- }
- 
--/* Return true if insn sets the condition codes.  */
--
--bool
--arc_sets_cc_p (rtx_insn *insn)
--{
--  if (NONJUMP_INSN_P (insn))
--    if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
--      insn = seq->insn (seq->len () - 1);
--  return arc_attr_type (insn) == TYPE_COMPARE;
--}
--
--/* Return true if INSN is an instruction with a delay slot we may want
--   to fill.  */
--
--bool
--arc_need_delay (rtx_insn *insn)
--{
--  rtx_insn *next;
--
--  if (!flag_delayed_branch)
--    return false;
--  /* The return at the end of a function needs a delay slot.  */
--  if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
--      && (!(next = next_active_insn (insn))
--	  || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE)
--	      && arc_attr_type (next) == TYPE_RETURN))
--      && (!TARGET_PAD_RETURN
--	  || (prev_active_insn (insn)
--	      && prev_active_insn (prev_active_insn (insn))
--	      && prev_active_insn (prev_active_insn (prev_active_insn (insn))))))
--    return true;
--  if (NONJUMP_INSN_P (insn)
--      ? (GET_CODE (PATTERN (insn)) == USE
--	 || GET_CODE (PATTERN (insn)) == CLOBBER
--	 || GET_CODE (PATTERN (insn)) == SEQUENCE)
--      : JUMP_P (insn)
--      ? (GET_CODE (PATTERN (insn)) == ADDR_VEC
--	 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
--      : !CALL_P (insn))
--    return false;
--  return num_delay_slots (insn) != 0;
--}
--
--/* Return true if the scheduling pass(es) has/have already run,
--   i.e. where possible, we should try to mitigate high latencies
--   by different instruction selection.  */
--
--bool
--arc_scheduling_not_expected (void)
--{
--  return cfun->machine->arc_reorg_started;
--}
--
- /* Code has a minimum p2 alignment of 1, which we must restore after
-    an ADDR_DIFF_VEC.  */
- 
-diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
-index d4d9f59a3ea..6c09c86884f 100644
---- a/gcc/config/arc/arc.md
-+++ b/gcc/config/arc/arc.md
-@@ -2857,43 +2857,25 @@ archs4x, archs4xd"
-    (set_attr "type" "compare")
-    (set_attr "length" "4,4,8")])
- 
--; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end
--; needlessly prioritizing the matching constraint.
--; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional
--; execution is used where possible.
--(define_insn_and_split "adc"
--  [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
--	(plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))
--			  (match_operand:SI 1 "nonmemory_operand"
--							 "%c,0,c,0,cCal"))
--		 (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
-+(define_insn "adc"
-+  [(set (match_operand:SI 0 "register_operand"    "=r,  r,r,r,  r,r")
-+	(plus:SI
-+	 (plus:SI
-+	  (ltu:SI (reg:CC_C CC_REG) (const_int 0))
-+	  (match_operand:SI 1 "nonmemory_operand" "%r,  0,r,0,Cal,r"))
-+	 (match_operand:SI 2 "nonmemory_operand"   "r,C_0,L,I,  r,Cal")))]
-   "register_operand (operands[1], SImode)
-    || register_operand (operands[2], SImode)"
-   "@
--	adc %0,%1,%2
--	add.cs %0,%1,1
--	adc %0,%1,%2
--	adc %0,%1,%2
--	adc %0,%1,%2"
--  ; if we have a bad schedule after sched2, split.
--  "reload_completed
--   && !optimize_size && (!TARGET_ARC600_FAMILY)
--   && arc_scheduling_not_expected ()
--   && arc_sets_cc_p (prev_nonnote_insn (insn))
--   /* If next comes a return or other insn that needs a delay slot,
--      expect the adc to get into the delay slot.  */
--   && next_nonnote_insn (insn)
--   && !arc_need_delay (next_nonnote_insn (insn))
--   /* Restore operands before emitting.  */
--   && (extract_insn_cached (insn), 1)"
--  [(set (match_dup 0) (match_dup 3))
--   (cond_exec
--     (ltu (reg:CC_C CC_REG) (const_int 0))
--     (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))))]
--  "operands[3] = simplify_gen_binary (PLUS, SImode, operands[1], operands[2]);"
-+    adc\\t%0,%1,%2
-+    add.cs\\t%0,%1,1
-+    adc\\t%0,%1,%2
-+    adc\\t%0,%1,%2
-+    adc\\t%0,%1,%2
-+    adc\\t%0,%1,%2"
-   [(set_attr "cond" "use")
-    (set_attr "type" "cc_arith")
--   (set_attr "length" "4,4,4,4,8")])
-+   (set_attr "length" "4,4,4,4,8,8")])
- 
- ; combiner-splitter cmp / scc -> cmp / adc
- (define_split
-@@ -3025,7 +3007,7 @@ archs4x, archs4xd"
-       DONE;
-     }
-   emit_insn (gen_sub_f (l0, l1, l2));
--  emit_insn (gen_sbc (h0, h1, h2, gen_rtx_REG (CCmode, CC_REG)));
-+  emit_insn (gen_sbc (h0, h1, h2));
-   DONE;
-   ")
- 
-@@ -3040,44 +3022,25 @@ archs4x, archs4xd"
-    (set_attr "type" "cc_arith")
-    (set_attr "length" "4")])
- 
--; w/c/c comes first (rather than Rcw/0/C_0) to prevent the middle-end
--; needlessly prioritizing the matching constraint.
--; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional execution
--; is used where possible.
--(define_insn_and_split "sbc"
--  [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
--	(minus:SI (minus:SI (match_operand:SI 1 "nonmemory_operand"
--						"c,0,c,0,cCal")
--			    (ltu:SI (match_operand:CC_C 3 "cc_use_register")
--				    (const_int 0)))
--		  (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
-+(define_insn "sbc"
-+  [(set (match_operand:SI 0 "dest_reg_operand"   "=r,r,r,r,r,r")
-+	(minus:SI
-+	 (minus:SI
-+	  (match_operand:SI 1 "nonmemory_operand" "r,  0,r,0,  r,Cal")
-+	  (ltu:SI (reg:CC_C CC_REG) (const_int 0)))
-+	 (match_operand:SI 2 "nonmemory_operand"  "r,C_0,L,I,Cal,r")))]
-   "register_operand (operands[1], SImode)
-    || register_operand (operands[2], SImode)"
-   "@
--	sbc %0,%1,%2
--	sub.cs %0,%1,1
--	sbc %0,%1,%2
--	sbc %0,%1,%2
--	sbc %0,%1,%2"
--  ; if we have a bad schedule after sched2, split.
--  "reload_completed
--   && !optimize_size && (!TARGET_ARC600_FAMILY)
--   && arc_scheduling_not_expected ()
--   && arc_sets_cc_p (prev_nonnote_insn (insn))
--   /* If next comes a return or other insn that needs a delay slot,
--      expect the adc to get into the delay slot.  */
--   && next_nonnote_insn (insn)
--   && !arc_need_delay (next_nonnote_insn (insn))
--   /* Restore operands before emitting.  */
--   && (extract_insn_cached (insn), 1)"
--  [(set (match_dup 0) (match_dup 4))
--   (cond_exec
--     (ltu (reg:CC_C CC_REG) (const_int 0))
--     (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1))))]
--  "operands[4] = simplify_gen_binary (MINUS, SImode, operands[1], operands[2]);"
-+    sbc\\t%0,%1,%2
-+    sub.cs\\t%0,%1,1
-+    sbc\\t%0,%1,%2
-+    sbc\\t%0,%1,%2
-+    sbc\\t%0,%1,%2
-+    sbc\\t%0,%1,%2"
-   [(set_attr "cond" "use")
-    (set_attr "type" "cc_arith")
--   (set_attr "length" "4,4,4,4,8")])
-+   (set_attr "length" "4,4,4,4,8,8")])
- 
- (define_insn "sub_f"
-   [(set (reg:CC CC_REG)
--- 
-2.16.2
-
diff --git a/package/gcc/10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch b/package/gcc/10.3.0/0001-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
similarity index 93%
rename from package/gcc/10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
rename to package/gcc/10.3.0/0001-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
index 6f11713c6b..af0d2d7d02 100644
--- a/package/gcc/10.2.0/0002-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
+++ b/package/gcc/10.3.0/0001-Revert-re-PR-target-92095-internal-error-with-O1-mcp.patch
@@ -1,4 +1,4 @@
-From 472472ee0aaccb6389747d6281c34c558bcca7d8 Mon Sep 17 00:00:00 2001
+From 0824d6819857f306583592bce96315893f91bd84 Mon Sep 17 00:00:00 2001
 From: Romain Naour <romain.naour@gmail.com>
 Date: Wed, 20 Jan 2021 23:26:29 +0100
 Subject: [PATCH] Revert "re PR target/92095 (internal error with -O1
@@ -16,6 +16,9 @@ the commit that introcuce the regression.
 
 Reverting this patch allowed to produce a working rootfs.
 
+Reported to gcc:
+https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98784
+
 Signed-off-by: Romain Naour <romain.naour@gmail.com>
 Cc: Eric Botcazou <ebotcazou@gcc.gnu.org>
 ---
@@ -30,7 +33,7 @@ Cc: Eric Botcazou <ebotcazou@gcc.gnu.org>
  delete mode 100644 gcc/testsuite/gcc.c-torture/compile/20191108-1.c
 
 diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
-index f525cd7a422..0d9f47af644 100644
+index 5f9999a669c..37452b06415 100644
 --- a/gcc/config/sparc/sparc-protos.h
 +++ b/gcc/config/sparc/sparc-protos.h
 @@ -69,7 +69,6 @@ extern void sparc_split_reg_mem (rtx, rtx, machine_mode);
@@ -42,10 +45,10 @@ index f525cd7a422..0d9f47af644 100644
  extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *);
  extern const char *output_return (rtx_insn *);
 diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
-index aefced85fe1..3ff6f9200f6 100644
+index d0843102148..14d112d8ca8 100644
 --- a/gcc/config/sparc/sparc.c
 +++ b/gcc/config/sparc/sparc.c
-@@ -4192,6 +4192,13 @@ eligible_for_sibcall_delay (rtx_insn *trial)
+@@ -4157,6 +4157,13 @@ eligible_for_sibcall_delay (rtx_insn *trial)
  static bool
  sparc_cannot_force_const_mem (machine_mode mode, rtx x)
  {
@@ -59,7 +62,7 @@ index aefced85fe1..3ff6f9200f6 100644
    switch (GET_CODE (x))
      {
      case CONST_INT:
-@@ -4227,11 +4234,9 @@ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+@@ -4192,11 +4199,9 @@ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
  }
  \f
  /* Global Offset Table support.  */
@@ -73,7 +76,7 @@ index aefced85fe1..3ff6f9200f6 100644
  
  /* Return the SYMBOL_REF for the Global Offset Table.  */
  
-@@ -4244,6 +4249,27 @@ sparc_got (void)
+@@ -4209,6 +4214,27 @@ sparc_got (void)
    return got_symbol_rtx;
  }
  
@@ -101,7 +104,7 @@ index aefced85fe1..3ff6f9200f6 100644
  /* Wrapper around the load_pcrel_sym{si,di} patterns.  */
  
  static rtx
-@@ -4263,78 +4289,30 @@ gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
+@@ -4228,78 +4254,30 @@ gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
    return insn;
  }
  
@@ -186,7 +189,7 @@ index aefced85fe1..3ff6f9200f6 100644
  }
  
  /* Ensure that we are not using patterns that are not OK with PIC.  */
-@@ -5499,7 +5477,7 @@ save_local_or_in_reg_p (unsigned int regno, int leaf_function)
+@@ -5464,7 +5442,7 @@ save_local_or_in_reg_p (unsigned int regno, int leaf_function)
      return true;
  
    /* GOT register (%l7) if needed.  */
@@ -195,7 +198,7 @@ index aefced85fe1..3ff6f9200f6 100644
      return true;
  
    /* If the function accesses prior frames, the frame pointer and the return
-@@ -12542,9 +12520,10 @@ static void
+@@ -12507,9 +12485,10 @@ static void
  sparc_file_end (void)
  {
    /* If we need to emit the special GOT helper function, do so now.  */
@@ -207,7 +210,7 @@ index aefced85fe1..3ff6f9200f6 100644
  #ifdef DWARF2_UNWIND_INFO
        bool do_cfi;
  #endif
-@@ -12581,22 +12560,17 @@ sparc_file_end (void)
+@@ -12546,22 +12525,17 @@ sparc_file_end (void)
  #ifdef DWARF2_UNWIND_INFO
        do_cfi = dwarf2out_do_cfi_asm ();
        if (do_cfi)
@@ -236,7 +239,7 @@ index aefced85fe1..3ff6f9200f6 100644
  #endif
      }
  
-@@ -13091,10 +13065,7 @@ sparc_init_pic_reg (void)
+@@ -13056,10 +13030,7 @@ sparc_init_pic_reg (void)
    edge entry_edge;
    rtx_insn *seq;
  
@@ -249,10 +252,10 @@ index aefced85fe1..3ff6f9200f6 100644
  
    start_sequence ();
 diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
-index 231c0d84778..899804b80ae 100644
+index 6e9ccb4ecfd..8fb0fa11aed 100644
 --- a/gcc/config/sparc/sparc.md
 +++ b/gcc/config/sparc/sparc.md
-@@ -1604,7 +1604,10 @@
+@@ -1601,7 +1601,10 @@
     (clobber (reg:P O7_REG))]
    "REGNO (operands[0]) == INTVAL (operands[3])"
  {
@@ -321,5 +324,5 @@ index f00283f6e7b..67d4ac38095 100644
  #include <stdbool.h>
  #include <stdint.h>
 -- 
-2.25.4
+2.30.2
 
diff --git a/package/gcc/Config.in.host b/package/gcc/Config.in.host
index 2ed159314c..5b056a934a 100644
--- a/package/gcc/Config.in.host
+++ b/package/gcc/Config.in.host
@@ -74,7 +74,7 @@ config BR2_GCC_VERSION
 	string
 	default "8.4.0"     if BR2_GCC_VERSION_8_X
 	default "9.3.0"     if BR2_GCC_VERSION_9_X
-	default "10.2.0"    if BR2_GCC_VERSION_10_X
+	default "10.3.0"    if BR2_GCC_VERSION_10_X
 	default "arc-2020.09-release" if BR2_GCC_VERSION_ARC
 	default "48152afb96c59733d5bc79e3399bb7b3d4b44266" if BR2_GCC_VERSION_CSKY
 
diff --git a/package/gcc/gcc.hash b/package/gcc/gcc.hash
index 2208095a29..566ae09fc2 100644
--- a/package/gcc/gcc.hash
+++ b/package/gcc/gcc.hash
@@ -2,8 +2,8 @@
 sha512  6de904f552a02de33b11ef52312bb664396efd7e1ce3bbe37bfad5ef617f133095b3767b4804bc7fe78df335cb53bc83f1ac055baed40979ce4c2c3e46b70280  gcc-8.4.0.tar.xz
 #  From ftp://gcc.gnu.org/pub/gcc/releases/gcc-9.3.0/sha512.sum
 sha512  4b9e3639eef6e623747a22c37a904b4750c93b6da77cf3958d5047e9b5ebddb7eebe091cc16ca0a227c0ecbd2bf3b984b221130f269a97ee4cc18f9cf6c444de  gcc-9.3.0.tar.xz
-# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-10.2.0/sha512.sum
-sha512  42ae38928bd2e8183af445da34220964eb690b675b1892bbeb7cd5bb62be499011ec9a93397dba5e2fb681afadfc6f2767d03b9035b44ba9be807187ae6dc65e  gcc-10.2.0.tar.xz
+# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-10.3.0/sha512.sum
+sha512  2b2dd7453d48a398c29eaebd1422b70341001b8c90a62aee51e83344e7fdd8a8e45f82a4a9165bd7edc76dada912c932f4b6632c5636760fec4c5d7e402b3f86  gcc-10.3.0.tar.xz
 
 # Locally calculated (fetched from Github)
 sha512  b0853e2b1c5998044392023fa653e399e74118c46e616504ac59e1a2cf27620f94434767ce06b6cf4ca3dfb57f81d6eda92752befaf095ea5e564a9181b4659c  gcc-arc-2020.09-release.tar.gz
-- 
2.30.2

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