[PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI

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* [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI
@ 2021-02-10  2:42 Tom Rini
  2021-02-10  2:42 ` [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK Tom Rini
                   ` (15 more replies)
  0 siblings, 16 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 8f6ca820a24b..214a2bb9e735 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -41,7 +41,6 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
-CONFIG_SCSI_AHCI=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-04-12  0:24   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 03/16] ata: DWC_AHSATA depends on BLK Tom Rini
                   ` (14 subsequent siblings)
  15 siblings, 1 reply; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

Enable the AHCI and BLK features to complete migration of various
drivers.

Cc: Andrew F. Davis <afd@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 configs/am57xx_hs_evm_usb_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index d020bb0e4626..35f90274a2b1 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -20,6 +20,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_ARMV7_LPAE=y
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
+CONFIG_AHCI=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SPL_LOAD_FIT=y
@@ -69,7 +70,6 @@ CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SCSI_AHCI=y
-# CONFIG_BLK is not set
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK
  2021-02-10  2:42 ` [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK Tom Rini
@ 2021-04-12  0:24   ` Tom Rini
  0 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-04-12  0:24 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:43PM -0500, Tom Rini wrote:

> Enable the AHCI and BLK features to complete migration of various
> drivers.
> 
> Cc: Andrew F. Davis <afd@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 03/16] ata: DWC_AHSATA depends on BLK
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
  2021-02-10  2:42 ` [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-04-12  0:25   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 04/16] ppc: configs: Remove a few non-updated build configurations Tom Rini
                   ` (13 subsequent siblings)
  15 siblings, 1 reply; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

The dwc ahsata driver is written such that CONFIG_BLK must be enabled,
add this as a dependency in Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 drivers/ata/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index f2f8275aeca8..3914f996d91c 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -62,6 +62,7 @@ config DWC_AHCI
 config DWC_AHSATA
 	bool "Enable DWC AHSATA driver support"
 	select LIBATA
+	depends on BLK
 	help
 	  Enable this driver to support the DWC AHSATA SATA controller found
 	  in i.MX5 and i.MX6 SoCs.
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 03/16] ata: DWC_AHSATA depends on BLK
  2021-02-10  2:42 ` [PATCH 03/16] ata: DWC_AHSATA depends on BLK Tom Rini
@ 2021-04-12  0:25   ` Tom Rini
  0 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-04-12  0:25 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:44PM -0500, Tom Rini wrote:

> The dwc ahsata driver is written such that CONFIG_BLK must be enabled,
> add this as a dependency in Kconfig.
> 
> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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* [PATCH 04/16] ppc: configs: Remove a few non-updated build configurations
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
  2021-02-10  2:42 ` [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK Tom Rini
  2021-02-10  2:42 ` [PATCH 03/16] ata: DWC_AHSATA depends on BLK Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-10  2:42 ` [PATCH 05/16] arm: Remove highbank board Tom Rini
                   ` (12 subsequent siblings)
  15 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

In the cases of T2080RDB_SECURE_BOOT, T2080RDB_SRIO_PCIE_BOOT,
P2041RDB_SECURE_BOOT, P2041RDB_SRIO_PCIE_BOOT, P3041DS_SRIO_PCIE_BOOT
and P4080DS_SRIO_PCIE_BOOT while some forms of the board have been
migrated more fully to current build standards, these have not.  Remove
them.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 configs/P2041RDB_SECURE_BOOT_defconfig    | 62 ---------------------
 configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 53 ------------------
 configs/P3041DS_SRIO_PCIE_BOOT_defconfig  | 53 ------------------
 configs/P4080DS_SRIO_PCIE_BOOT_defconfig  | 51 ------------------
 configs/T2080RDB_SECURE_BOOT_defconfig    | 66 -----------------------
 configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 56 -------------------
 6 files changed, 341 deletions(-)
 delete mode 100644 configs/P2041RDB_SECURE_BOOT_defconfig
 delete mode 100644 configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
 delete mode 100644 configs/P3041DS_SRIO_PCIE_BOOT_defconfig
 delete mode 100644 configs/P4080DS_SRIO_PCIE_BOOT_defconfig
 delete mode 100644 configs/T2080RDB_SECURE_BOOT_defconfig
 delete mode 100644 configs/T2080RDB_SRIO_PCIE_BOOT_defconfig

diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index c42e583f6cc9..000000000000
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 822a91be2761..000000000000
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 76ac6abce57c..000000000000
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 5bfce4bcbf44..000000000000
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index b82a4cca955c..000000000000
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 54579fa8aae6..000000000000
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_SYS_CORTINA_FW_IN_REMOTE=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 05/16] arm: Remove highbank board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (2 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 04/16] ppc: configs: Remove a few non-updated build configurations Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-19 13:04   ` André Przywara
  2021-02-10  2:42 ` [PATCH 06/16] arm: Remove dms-ba16 board Tom Rini
                   ` (11 subsequent siblings)
  15 siblings, 1 reply; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/Kconfig                |   7 --
 arch/arm/Makefile               |   1 -
 arch/arm/mach-highbank/Kconfig  |  12 --
 arch/arm/mach-highbank/Makefile |   6 -
 arch/arm/mach-highbank/timer.c  |  34 ------
 board/highbank/MAINTAINERS      |   6 -
 board/highbank/Makefile         |   6 -
 board/highbank/ahci.c           | 207 --------------------------------
 board/highbank/highbank.c       | 148 -----------------------
 configs/highbank_defconfig      |  28 -----
 include/configs/highbank.h      |  60 ---------
 11 files changed, 515 deletions(-)
 delete mode 100644 arch/arm/mach-highbank/Kconfig
 delete mode 100644 arch/arm/mach-highbank/Makefile
 delete mode 100644 arch/arm/mach-highbank/timer.c
 delete mode 100644 board/highbank/MAINTAINERS
 delete mode 100644 board/highbank/Makefile
 delete mode 100644 board/highbank/ahci.c
 delete mode 100644 board/highbank/highbank.c
 delete mode 100644 configs/highbank_defconfig
 delete mode 100644 include/configs/highbank.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 95557d6ed6bd..6fa69d39be5b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -750,11 +750,6 @@ config ARCH_S5PC1XX
 	select DM_SERIAL
 	imply CMD_DM
 
-config ARCH_HIGHBANK
-	bool "Calxeda Highbank"
-	select CPU_V7A
-	select PL011_SERIAL
-
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
 	select DM
@@ -1873,8 +1868,6 @@ source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-exynos/Kconfig"
 
-source "arch/arm/mach-highbank/Kconfig"
-
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-ipq40xx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 28b523b37c70..e1d266c3a4d8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -57,7 +57,6 @@ machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
 machine-$(CONFIG_ARCH_BCMSTB)		+= bcmstb
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
 machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
-machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_IPQ40XX)		+= ipq40xx
 machine-$(CONFIG_ARCH_K3)		+= k3
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
deleted file mode 100644
index 0e73c0414293..000000000000
--- a/arch/arm/mach-highbank/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if ARCH_HIGHBANK
-
-config SYS_BOARD
-	default "highbank"
-
-config SYS_SOC
-	default "highbank"
-
-config SYS_CONFIG_NAME
-	default "highbank"
-
-endif
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
deleted file mode 100644
index 029e266bedce..000000000000
--- a/arch/arm/mach-highbank/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y	:= timer.o
diff --git a/arch/arm/mach-highbank/timer.c b/arch/arm/mach-highbank/timer.c
deleted file mode 100644
index 2423a0e37855..000000000000
--- a/arch/arm/mach-highbank/timer.c
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- *
- * Based on arm926ejs/mx27/timer.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch-armv7/systimer.h>
-
-#undef SYSTIMER_BASE
-#define SYSTIMER_BASE		0xFFF34000	/* Timer 0 and 1 base	*/
-
-static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
-
-/*
- * Start the timer
- */
-int timer_init(void)
-{
-	/*
-	 * Setup timer0
-	 */
-	writel(0, &systimer_base->timer0control);
-	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
-	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
-	writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
-		&systimer_base->timer0control);
-
-	return 0;
-
-}
diff --git a/board/highbank/MAINTAINERS b/board/highbank/MAINTAINERS
deleted file mode 100644
index 69ddeddd6003..000000000000
--- a/board/highbank/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HIGHBANK BOARD
-M:	Rob Herring <robh@kernel.org>
-S:	Maintained
-F:	board/highbank/
-F:	include/configs/highbank.h
-F:	configs/highbank_defconfig
diff --git a/board/highbank/Makefile b/board/highbank/Makefile
deleted file mode 100644
index 57f7f2e2a658..000000000000
--- a/board/highbank/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y	:= highbank.o ahci.o
diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c
deleted file mode 100644
index 9c057278ace1..000000000000
--- a/board/highbank/ahci.c
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2012 Calxeda, Inc.
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
-#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
-#define CPHY_BASE			0xfff58000
-#define CPHY_WIDTH			0x1000
-#define CPHY_DTE_XS			5
-#define CPHY_MII			31
-#define SERDES_CR_CTL			0x80a0
-#define SERDES_CR_ADDR			0x80a1
-#define SERDES_CR_DATA			0x80a2
-#define CR_BUSY				0x0001
-#define CR_START			0x0001
-#define CR_WR_RDN			0x0002
-#define CPHY_TX_INPUT_STS		0x2001
-#define CPHY_RX_INPUT_STS		0x2002
-#define CPHY_SATA_TX_OVERRIDE_BIT	0x8000
-#define CPHY_SATA_RX_OVERRIDE_BIT	0x4000
-#define CPHY_TX_INPUT_OVERRIDE		0x2004
-#define CPHY_RX_INPUT_OVERRIDE		0x2005
-#define SPHY_LANE			0x100
-#define SPHY_HALF_RATE			0x0001
-#define CPHY_SATA_DPLL_MODE		0x0700
-#define CPHY_SATA_DPLL_SHIFT		8
-#define CPHY_SATA_TX_ATTEN		0x1c00
-#define CPHY_SATA_TX_ATTEN_SHIFT	10
-
-#define HB_SREG_SATA_ATTEN		0xfff3cf24
-
-#define SATA_PORT_BASE			0xffe08000
-#define SATA_VERSIONR			0xf8
-#define SATA_HB_VERSION			0x3332302a
-
-static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
-{
-	u32 data;
-	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
-	data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
-	return data;
-}
-
-static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
-{
-	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
-	writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
-}
-
-static u32 combo_phy_read(u8 phy, u32 addr)
-{
-	u8 dev = CPHY_DTE_XS;
-	if (phy == 5)
-		dev = CPHY_MII;
-	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
-		udelay(5);
-	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
-	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
-	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
-		udelay(5);
-	return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
-}
-
-static void combo_phy_write(u8 phy, u32 addr, u32 data)
-{
-	u8 dev = CPHY_DTE_XS;
-	if (phy == 5)
-		dev = CPHY_MII;
-	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
-		udelay(5);
-	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
-	__combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
-	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
-}
-
-static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
-{
-	u32 tmp;
-	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
-	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
-	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-
-	tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
-	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-
-	tmp &= ~CPHY_SATA_DPLL_MODE;
-	tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
-	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-}
-
-static void cphy_tx_attenuation_override(u8 phy, u8 lane)
-{
-	u32 val;
-	u32 tmp;
-	u8  shift;
-
-	shift = ((phy == 5) ? 4 : lane) * 4;
-
-	val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
-
-	if (val & 0x8)
-		return;
-
-	tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
-	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
-	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-
-	tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
-	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-
-	tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
-	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-}
-
-static void cphy_disable_port_overrides(u8 port)
-{
-	u32 tmp;
-	u8 lane = 0, phy = 0;
-
-	if (port == 0)
-		phy = 5;
-	else if (port < 5)
-		lane = port - 1;
-	else
-		return;
-	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
-	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
-	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-
-	tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
-	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
-	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
-}
-
-void cphy_disable_overrides(void)
-{
-	int i;
-	u32 port_map;
-
-	port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
-	for (i = 0; i < 5; i++) {
-		if (port_map & (1 << i))
-			cphy_disable_port_overrides(i);
-	}
-}
-
-static void cphy_override_lane(u8 port)
-{
-	u32 tmp, k = 0;
-	u8 lane = 0, phy = 0;
-
-	if (port == 0)
-		phy = 5;
-	else if (port < 5)
-		lane = port - 1;
-	else
-		return;
-
-	do {
-		tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
-					lane * SPHY_LANE);
-	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
-	cphy_spread_spectrum_override(phy, lane, 3);
-	cphy_tx_attenuation_override(phy, lane);
-}
-
-#define WAIT_MS_LINKUP	4
-
-int ahci_link_up(struct ahci_uc_priv *probe_ent, int port)
-{
-	u32 tmp;
-	int j = 0;
-	u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
-	u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
-				SATA_HB_VERSION ? 1 : 0;
-
-	/* Bring up SATA link.
-	 * SATA link bringup time is usually less than 1 ms; only very
-	 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
-	 */
-	while (j < WAIT_MS_LINKUP) {
-		if (is_highbank && (j == 0)) {
-			cphy_disable_port_overrides(port);
-			writel(0x301, port_mmio + PORT_SCR_CTL);
-			udelay(1000);
-			writel(0x300, port_mmio + PORT_SCR_CTL);
-			udelay(1000);
-			cphy_override_lane(port);
-		}
-
-		tmp = readl(port_mmio + PORT_SCR_STAT);
-		if ((tmp & 0xf) == 0x3)
-			return 0;
-		udelay(1000);
-		j++;
-
-		if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
-			j = 0;	/* retry phy reset */
-	}
-	return 1;
-}
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
deleted file mode 100644
index e07295c7b5c0..000000000000
--- a/board/highbank/highbank.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <cpu_func.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <scsi.h>
-
-#include <linux/sizes.h>
-#include <asm/io.h>
-
-#define HB_AHCI_BASE			0xffe08000
-
-#define HB_SCU_A9_PWR_STATUS		0xfff10008
-#define HB_SREG_A9_PWR_REQ		0xfff3cf00
-#define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
-#define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
-#define HB_SREG_A15_PWR_CTRL		0xfff3c200
-
-#define HB_PWR_SUSPEND			0
-#define HB_PWR_SOFT_RESET		1
-#define HB_PWR_HARD_RESET		2
-#define HB_PWR_SHUTDOWN			3
-
-#define PWRDOM_STAT_SATA		0x80000000
-#define PWRDOM_STAT_PCI			0x40000000
-#define PWRDOM_STAT_EMMC		0x20000000
-
-#define HB_SCU_A9_PWR_NORMAL		0
-#define HB_SCU_A9_PWR_DORMANT		2
-#define HB_SCU_A9_PWR_OFF		3
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void cphy_disable_overrides(void);
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	icache_enable();
-
-	return 0;
-}
-
-/* We know all the init functions have been run now */
-int board_eth_init(struct bd_info *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_CALXEDA_XGMAC
-	rc += calxedaxgmac_initialize(0, 0xfff50000);
-	rc += calxedaxgmac_initialize(1, 0xfff51000);
-#endif
-	return rc;
-}
-
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
-	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
-
-	cphy_disable_overrides();
-	if (reg & PWRDOM_STAT_SATA) {
-		ahci_init((void __iomem *)HB_AHCI_BASE);
-		scsi_scan(true);
-	}
-}
-#endif
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-	char envbuffer[16];
-	u32 boot_choice;
-
-	boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
-	sprintf(envbuffer, "bootcmd%d", boot_choice);
-	if (env_get(envbuffer)) {
-		sprintf(envbuffer, "run bootcmd%d", boot_choice);
-		env_set("bootcmd", envbuffer);
-	} else
-		env_set("bootcmd", "");
-
-	return 0;
-}
-#endif
-
-int dram_init(void)
-{
-	gd->ram_size = SZ_512M;
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *fdt, struct bd_info *bd)
-{
-	static const char disabled[] = "disabled";
-	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
-
-	if (!(reg & PWRDOM_STAT_SATA))
-		do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
-			disabled, sizeof(disabled), 1);
-
-	if (!(reg & PWRDOM_STAT_EMMC))
-		do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
-			disabled, sizeof(disabled), 1);
-
-	return 0;
-}
-#endif
-
-static int is_highbank(void)
-{
-	uint32_t midr;
-
-	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
-
-	return (midr & 0xfff0) == 0xc090;
-}
-
-void reset_cpu(ulong addr)
-{
-	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
-	if (is_highbank())
-		writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
-	else
-		writel(0x1, HB_SREG_A15_PWR_CTRL);
-
-	wfi();
-}
-
-/*
- * turn off the override before transferring control to Linux, since Linux
- * may not support spread spectrum.
- */
-void arch_preboot_os(void)
-{
-	cphy_disable_overrides();
-}
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
deleted file mode 100644
index 369b65ceee88..000000000000
--- a/configs/highbank_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_HIGHBANK=y
-CONFIG_SYS_TEXT_BASE=0x00008000
-CONFIG_NR_DRAM_BANKS=0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
-CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
-CONFIG_AUTOBOOT_KEYED_CTRLC=y
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_ENV_IS_IN_NVRAM=y
-CONFIG_ENV_ADDR=0xFFF88000
-CONFIG_SCSI_AHCI=y
-CONFIG_BOOTCOUNT_LIMIT=y
-# CONFIG_MMC is not set
-CONFIG_SCSI=y
-CONFIG_CONS_INDEX=0
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
deleted file mode 100644
index bdbaa475d204..000000000000
--- a/include/configs/highbank.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
-
-#define CONFIG_SYS_TIMER_RATE		(150000000/256)
-#define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-
-#define CONFIG_PL011_CLOCK		150000000
-#define CONFIG_PL01x_PORTS		{ (void *)(0xFFF36000) }
-
-#define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
-
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	5
-#define CONFIG_SYS_SCSI_MAX_LUN		1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-					CONFIG_SYS_SCSI_MAX_LUN)
-
-#define CONFIG_CALXEDA_XGMAC
-
-#define CONFIG_BOOT_RETRY_TIME		-1
-#define CONFIG_RESET_TO_RETRY
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_LOAD_ADDR		0x800000
-#define CONFIG_SYS_64BIT_LBA
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- * The DRAM is already setup, so do not touch the DT node later.
- */
-#define PHYS_SDRAM_1_SIZE		(4089 << 20)
-
-/* Environment data setup
-*/
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
-
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_INIT_SP_ADDR		0x01000000
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-#endif
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 05/16] arm: Remove highbank board
  2021-02-10  2:42 ` [PATCH 05/16] arm: Remove highbank board Tom Rini
@ 2021-02-19 13:04   ` André Przywara
  2021-02-19 13:30     ` Tom Rini
  0 siblings, 1 reply; 38+ messages in thread
From: André Przywara @ 2021-02-19 13:04 UTC (permalink / raw)
  To: u-boot

On 10/02/2021 02:42, Tom Rini wrote:

Hi Tom,

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.

So I made a series a few months ago to bring highbank up to speed, it
converts everything over to DM, also starts using the DT provided by the
board for its own purposes.
I was facing one issue with SATA though, which made me drop the ball
there :-(
This is for the 2014.07 merge window, I guess? So if I manage to send
something before April, would you consider dropping this patch then?
Or do I need to start the series with a revert?

Cheers,
Andre

> 
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
>  arch/arm/Kconfig                |   7 --
>  arch/arm/Makefile               |   1 -
>  arch/arm/mach-highbank/Kconfig  |  12 --
>  arch/arm/mach-highbank/Makefile |   6 -
>  arch/arm/mach-highbank/timer.c  |  34 ------
>  board/highbank/MAINTAINERS      |   6 -
>  board/highbank/Makefile         |   6 -
>  board/highbank/ahci.c           | 207 --------------------------------
>  board/highbank/highbank.c       | 148 -----------------------
>  configs/highbank_defconfig      |  28 -----
>  include/configs/highbank.h      |  60 ---------
>  11 files changed, 515 deletions(-)
>  delete mode 100644 arch/arm/mach-highbank/Kconfig
>  delete mode 100644 arch/arm/mach-highbank/Makefile
>  delete mode 100644 arch/arm/mach-highbank/timer.c
>  delete mode 100644 board/highbank/MAINTAINERS
>  delete mode 100644 board/highbank/Makefile
>  delete mode 100644 board/highbank/ahci.c
>  delete mode 100644 board/highbank/highbank.c
>  delete mode 100644 configs/highbank_defconfig
>  delete mode 100644 include/configs/highbank.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 95557d6ed6bd..6fa69d39be5b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -750,11 +750,6 @@ config ARCH_S5PC1XX
>  	select DM_SERIAL
>  	imply CMD_DM
>  
> -config ARCH_HIGHBANK
> -	bool "Calxeda Highbank"
> -	select CPU_V7A
> -	select PL011_SERIAL
> -
>  config ARCH_INTEGRATOR
>  	bool "ARM Ltd. Integrator family"
>  	select DM
> @@ -1873,8 +1868,6 @@ source "arch/arm/mach-davinci/Kconfig"
>  
>  source "arch/arm/mach-exynos/Kconfig"
>  
> -source "arch/arm/mach-highbank/Kconfig"
> -
>  source "arch/arm/mach-integrator/Kconfig"
>  
>  source "arch/arm/mach-ipq40xx/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 28b523b37c70..e1d266c3a4d8 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -57,7 +57,6 @@ machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
>  machine-$(CONFIG_ARCH_BCMSTB)		+= bcmstb
>  machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
>  machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
> -machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
>  machine-$(CONFIG_ARCH_IPQ40XX)		+= ipq40xx
>  machine-$(CONFIG_ARCH_K3)		+= k3
>  machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
> diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
> deleted file mode 100644
> index 0e73c0414293..000000000000
> --- a/arch/arm/mach-highbank/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if ARCH_HIGHBANK
> -
> -config SYS_BOARD
> -	default "highbank"
> -
> -config SYS_SOC
> -	default "highbank"
> -
> -config SYS_CONFIG_NAME
> -	default "highbank"
> -
> -endif
> diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
> deleted file mode 100644
> index 029e266bedce..000000000000
> --- a/arch/arm/mach-highbank/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2000-2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -
> -obj-y	:= timer.o
> diff --git a/arch/arm/mach-highbank/timer.c b/arch/arm/mach-highbank/timer.c
> deleted file mode 100644
> index 2423a0e37855..000000000000
> --- a/arch/arm/mach-highbank/timer.c
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2010-2011 Calxeda, Inc.
> - *
> - * Based on arm926ejs/mx27/timer.c
> - */
> -
> -#include <common.h>
> -#include <init.h>
> -#include <asm/io.h>
> -#include <asm/arch-armv7/systimer.h>
> -
> -#undef SYSTIMER_BASE
> -#define SYSTIMER_BASE		0xFFF34000	/* Timer 0 and 1 base	*/
> -
> -static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
> -
> -/*
> - * Start the timer
> - */
> -int timer_init(void)
> -{
> -	/*
> -	 * Setup timer0
> -	 */
> -	writel(0, &systimer_base->timer0control);
> -	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
> -	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
> -	writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
> -		&systimer_base->timer0control);
> -
> -	return 0;
> -
> -}
> diff --git a/board/highbank/MAINTAINERS b/board/highbank/MAINTAINERS
> deleted file mode 100644
> index 69ddeddd6003..000000000000
> --- a/board/highbank/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -HIGHBANK BOARD
> -M:	Rob Herring <robh@kernel.org>
> -S:	Maintained
> -F:	board/highbank/
> -F:	include/configs/highbank.h
> -F:	configs/highbank_defconfig
> diff --git a/board/highbank/Makefile b/board/highbank/Makefile
> deleted file mode 100644
> index 57f7f2e2a658..000000000000
> --- a/board/highbank/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2000-2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -
> -obj-y	:= highbank.o ahci.o
> diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c
> deleted file mode 100644
> index 9c057278ace1..000000000000
> --- a/board/highbank/ahci.c
> +++ /dev/null
> @@ -1,207 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2012 Calxeda, Inc.
> - */
> -
> -#include <common.h>
> -#include <ahci.h>
> -#include <asm/io.h>
> -#include <linux/delay.h>
> -
> -#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
> -#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
> -#define CPHY_BASE			0xfff58000
> -#define CPHY_WIDTH			0x1000
> -#define CPHY_DTE_XS			5
> -#define CPHY_MII			31
> -#define SERDES_CR_CTL			0x80a0
> -#define SERDES_CR_ADDR			0x80a1
> -#define SERDES_CR_DATA			0x80a2
> -#define CR_BUSY				0x0001
> -#define CR_START			0x0001
> -#define CR_WR_RDN			0x0002
> -#define CPHY_TX_INPUT_STS		0x2001
> -#define CPHY_RX_INPUT_STS		0x2002
> -#define CPHY_SATA_TX_OVERRIDE_BIT	0x8000
> -#define CPHY_SATA_RX_OVERRIDE_BIT	0x4000
> -#define CPHY_TX_INPUT_OVERRIDE		0x2004
> -#define CPHY_RX_INPUT_OVERRIDE		0x2005
> -#define SPHY_LANE			0x100
> -#define SPHY_HALF_RATE			0x0001
> -#define CPHY_SATA_DPLL_MODE		0x0700
> -#define CPHY_SATA_DPLL_SHIFT		8
> -#define CPHY_SATA_TX_ATTEN		0x1c00
> -#define CPHY_SATA_TX_ATTEN_SHIFT	10
> -
> -#define HB_SREG_SATA_ATTEN		0xfff3cf24
> -
> -#define SATA_PORT_BASE			0xffe08000
> -#define SATA_VERSIONR			0xf8
> -#define SATA_HB_VERSION			0x3332302a
> -
> -static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
> -{
> -	u32 data;
> -	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
> -	data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
> -	return data;
> -}
> -
> -static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
> -{
> -	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
> -	writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
> -}
> -
> -static u32 combo_phy_read(u8 phy, u32 addr)
> -{
> -	u8 dev = CPHY_DTE_XS;
> -	if (phy == 5)
> -		dev = CPHY_MII;
> -	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
> -		udelay(5);
> -	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
> -	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
> -	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
> -		udelay(5);
> -	return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
> -}
> -
> -static void combo_phy_write(u8 phy, u32 addr, u32 data)
> -{
> -	u8 dev = CPHY_DTE_XS;
> -	if (phy == 5)
> -		dev = CPHY_MII;
> -	while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
> -		udelay(5);
> -	__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
> -	__combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
> -	__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
> -}
> -
> -static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
> -{
> -	u32 tmp;
> -	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
> -	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
> -	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -
> -	tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
> -	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -
> -	tmp &= ~CPHY_SATA_DPLL_MODE;
> -	tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
> -	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -}
> -
> -static void cphy_tx_attenuation_override(u8 phy, u8 lane)
> -{
> -	u32 val;
> -	u32 tmp;
> -	u8  shift;
> -
> -	shift = ((phy == 5) ? 4 : lane) * 4;
> -
> -	val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
> -
> -	if (val & 0x8)
> -		return;
> -
> -	tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
> -	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
> -	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -
> -	tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
> -	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -
> -	tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
> -	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -}
> -
> -static void cphy_disable_port_overrides(u8 port)
> -{
> -	u32 tmp;
> -	u8 lane = 0, phy = 0;
> -
> -	if (port == 0)
> -		phy = 5;
> -	else if (port < 5)
> -		lane = port - 1;
> -	else
> -		return;
> -	tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
> -	tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
> -	combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -
> -	tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
> -	tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
> -	combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
> -}
> -
> -void cphy_disable_overrides(void)
> -{
> -	int i;
> -	u32 port_map;
> -
> -	port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
> -	for (i = 0; i < 5; i++) {
> -		if (port_map & (1 << i))
> -			cphy_disable_port_overrides(i);
> -	}
> -}
> -
> -static void cphy_override_lane(u8 port)
> -{
> -	u32 tmp, k = 0;
> -	u8 lane = 0, phy = 0;
> -
> -	if (port == 0)
> -		phy = 5;
> -	else if (port < 5)
> -		lane = port - 1;
> -	else
> -		return;
> -
> -	do {
> -		tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
> -					lane * SPHY_LANE);
> -	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
> -	cphy_spread_spectrum_override(phy, lane, 3);
> -	cphy_tx_attenuation_override(phy, lane);
> -}
> -
> -#define WAIT_MS_LINKUP	4
> -
> -int ahci_link_up(struct ahci_uc_priv *probe_ent, int port)
> -{
> -	u32 tmp;
> -	int j = 0;
> -	u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
> -	u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
> -				SATA_HB_VERSION ? 1 : 0;
> -
> -	/* Bring up SATA link.
> -	 * SATA link bringup time is usually less than 1 ms; only very
> -	 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
> -	 */
> -	while (j < WAIT_MS_LINKUP) {
> -		if (is_highbank && (j == 0)) {
> -			cphy_disable_port_overrides(port);
> -			writel(0x301, port_mmio + PORT_SCR_CTL);
> -			udelay(1000);
> -			writel(0x300, port_mmio + PORT_SCR_CTL);
> -			udelay(1000);
> -			cphy_override_lane(port);
> -		}
> -
> -		tmp = readl(port_mmio + PORT_SCR_STAT);
> -		if ((tmp & 0xf) == 0x3)
> -			return 0;
> -		udelay(1000);
> -		j++;
> -
> -		if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
> -			j = 0;	/* retry phy reset */
> -	}
> -	return 1;
> -}
> diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
> deleted file mode 100644
> index e07295c7b5c0..000000000000
> --- a/board/highbank/highbank.c
> +++ /dev/null
> @@ -1,148 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2010-2011 Calxeda, Inc.
> - */
> -
> -#include <common.h>
> -#include <ahci.h>
> -#include <cpu_func.h>
> -#include <env.h>
> -#include <fdt_support.h>
> -#include <init.h>
> -#include <net.h>
> -#include <netdev.h>
> -#include <scsi.h>
> -
> -#include <linux/sizes.h>
> -#include <asm/io.h>
> -
> -#define HB_AHCI_BASE			0xffe08000
> -
> -#define HB_SCU_A9_PWR_STATUS		0xfff10008
> -#define HB_SREG_A9_PWR_REQ		0xfff3cf00
> -#define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
> -#define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
> -#define HB_SREG_A15_PWR_CTRL		0xfff3c200
> -
> -#define HB_PWR_SUSPEND			0
> -#define HB_PWR_SOFT_RESET		1
> -#define HB_PWR_HARD_RESET		2
> -#define HB_PWR_SHUTDOWN			3
> -
> -#define PWRDOM_STAT_SATA		0x80000000
> -#define PWRDOM_STAT_PCI			0x40000000
> -#define PWRDOM_STAT_EMMC		0x20000000
> -
> -#define HB_SCU_A9_PWR_NORMAL		0
> -#define HB_SCU_A9_PWR_DORMANT		2
> -#define HB_SCU_A9_PWR_OFF		3
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -void cphy_disable_overrides(void);
> -
> -/*
> - * Miscellaneous platform dependent initialisations
> - */
> -int board_init(void)
> -{
> -	icache_enable();
> -
> -	return 0;
> -}
> -
> -/* We know all the init functions have been run now */
> -int board_eth_init(struct bd_info *bis)
> -{
> -	int rc = 0;
> -
> -#ifdef CONFIG_CALXEDA_XGMAC
> -	rc += calxedaxgmac_initialize(0, 0xfff50000);
> -	rc += calxedaxgmac_initialize(1, 0xfff51000);
> -#endif
> -	return rc;
> -}
> -
> -#ifdef CONFIG_SCSI_AHCI_PLAT
> -void scsi_init(void)
> -{
> -	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
> -
> -	cphy_disable_overrides();
> -	if (reg & PWRDOM_STAT_SATA) {
> -		ahci_init((void __iomem *)HB_AHCI_BASE);
> -		scsi_scan(true);
> -	}
> -}
> -#endif
> -
> -#ifdef CONFIG_MISC_INIT_R
> -int misc_init_r(void)
> -{
> -	char envbuffer[16];
> -	u32 boot_choice;
> -
> -	boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
> -	sprintf(envbuffer, "bootcmd%d", boot_choice);
> -	if (env_get(envbuffer)) {
> -		sprintf(envbuffer, "run bootcmd%d", boot_choice);
> -		env_set("bootcmd", envbuffer);
> -	} else
> -		env_set("bootcmd", "");
> -
> -	return 0;
> -}
> -#endif
> -
> -int dram_init(void)
> -{
> -	gd->ram_size = SZ_512M;
> -	return 0;
> -}
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *fdt, struct bd_info *bd)
> -{
> -	static const char disabled[] = "disabled";
> -	u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
> -
> -	if (!(reg & PWRDOM_STAT_SATA))
> -		do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
> -			disabled, sizeof(disabled), 1);
> -
> -	if (!(reg & PWRDOM_STAT_EMMC))
> -		do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
> -			disabled, sizeof(disabled), 1);
> -
> -	return 0;
> -}
> -#endif
> -
> -static int is_highbank(void)
> -{
> -	uint32_t midr;
> -
> -	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
> -
> -	return (midr & 0xfff0) == 0xc090;
> -}
> -
> -void reset_cpu(ulong addr)
> -{
> -	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
> -	if (is_highbank())
> -		writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
> -	else
> -		writel(0x1, HB_SREG_A15_PWR_CTRL);
> -
> -	wfi();
> -}
> -
> -/*
> - * turn off the override before transferring control to Linux, since Linux
> - * may not support spread spectrum.
> - */
> -void arch_preboot_os(void)
> -{
> -	cphy_disable_overrides();
> -}
> diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
> deleted file mode 100644
> index 369b65ceee88..000000000000
> --- a/configs/highbank_defconfig
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_DCACHE_OFF=y
> -CONFIG_SYS_THUMB_BUILD=y
> -CONFIG_ARCH_HIGHBANK=y
> -CONFIG_SYS_TEXT_BASE=0x00008000
> -CONFIG_NR_DRAM_BANKS=0
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
> -CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_FIT=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_AUTOBOOT_KEYED=y
> -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n"
> -CONFIG_AUTOBOOT_KEYED_CTRLC=y
> -# CONFIG_USE_BOOTCOMMAND is not set
> -# CONFIG_DISPLAY_CPUINFO is not set
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_MISC_INIT_R=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_ENV_IS_IN_NVRAM=y
> -CONFIG_ENV_ADDR=0xFFF88000
> -CONFIG_SCSI_AHCI=y
> -CONFIG_BOOTCOUNT_LIMIT=y
> -# CONFIG_MMC is not set
> -CONFIG_SCSI=y
> -CONFIG_CONS_INDEX=0
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/highbank.h b/include/configs/highbank.h
> deleted file mode 100644
> index bdbaa475d204..000000000000
> --- a/include/configs/highbank.h
> +++ /dev/null
> @@ -1,60 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2010-2011 Calxeda, Inc.
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> -
> -#define CONFIG_SYS_TIMER_RATE		(150000000/256)
> -#define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
> -#define CONFIG_SYS_TIMER_COUNTS_DOWN
> -
> -/*
> - * Size of malloc() pool
> - */
> -#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
> -
> -#define CONFIG_PL011_CLOCK		150000000
> -#define CONFIG_PL01x_PORTS		{ (void *)(0xFFF36000) }
> -
> -#define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
> -
> -#define CONFIG_SCSI_AHCI_PLAT
> -#define CONFIG_SYS_SCSI_MAX_SCSI_ID	5
> -#define CONFIG_SYS_SCSI_MAX_LUN		1
> -#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
> -					CONFIG_SYS_SCSI_MAX_LUN)
> -
> -#define CONFIG_CALXEDA_XGMAC
> -
> -#define CONFIG_BOOT_RETRY_TIME		-1
> -#define CONFIG_RESET_TO_RETRY
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
> -#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> -
> -#define CONFIG_SYS_LOAD_ADDR		0x800000
> -#define CONFIG_SYS_64BIT_LBA
> -
> -/*-----------------------------------------------------------------------
> - * Physical Memory Map
> - * The DRAM is already setup, so do not touch the DT node later.
> - */
> -#define PHYS_SDRAM_1_SIZE		(4089 << 20)
> -
> -/* Environment data setup
> -*/
> -#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
> -#define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
> -
> -#define CONFIG_SYS_SDRAM_BASE		0x00000000
> -#define CONFIG_SYS_INIT_SP_ADDR		0x01000000
> -#define CONFIG_SKIP_LOWLEVEL_INIT
> -
> -#endif
> 

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 05/16] arm: Remove highbank board
  2021-02-19 13:04   ` André Przywara
@ 2021-02-19 13:30     ` Tom Rini
  0 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-19 13:30 UTC (permalink / raw)
  To: u-boot

On Fri, Feb 19, 2021 at 01:04:22PM +0000, Andr? Przywara wrote:
> On 10/02/2021 02:42, Tom Rini wrote:
> 
> Hi Tom,
> 
> > This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> > deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> > requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> > this board.
> 
> So I made a series a few months ago to bring highbank up to speed, it
> converts everything over to DM, also starts using the DT provided by the
> board for its own purposes.
> I was facing one issue with SATA though, which made me drop the ball
> there :-(
> This is for the 2014.07 merge window, I guess? So if I manage to send
> something before April, would you consider dropping this patch then?
> Or do I need to start the series with a revert?

Good question.  I'm not likely to get everything dropped that I want to
drop for v2021.04.  Since you have everything but SATA/etc converted
(which I guess is a driver needs conversion?) I'd like to see the base
converted and you picking up the MAINTAINERS entry for it soon so I can
review and take that.  Thanks!

-- 
Tom
-------------- next part --------------
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 06/16] arm: Remove dms-ba16 board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (3 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 05/16] arm: Remove highbank board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-04-12  0:25   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 07/16] arm: Remove ot1200 board Tom Rini
                   ` (10 subsequent siblings)
  15 siblings, 1 reply; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Akshay Bhat <akshaybhat@timesys.com>
Cc: Ken Lin <Ken.Lin@advantech.com.tw>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/mach-imx/mx6/Kconfig            |   7 -
 board/advantech/dms-ba16/Kconfig         |  31 --
 board/advantech/dms-ba16/MAINTAINERS     |   8 -
 board/advantech/dms-ba16/Makefile        |   6 -
 board/advantech/dms-ba16/clocks.cfg      |  25 -
 board/advantech/dms-ba16/ddr-setup.cfg   |  39 --
 board/advantech/dms-ba16/dms-ba16.c      | 629 -----------------------
 board/advantech/dms-ba16/dms-ba16_1g.cfg |  24 -
 board/advantech/dms-ba16/dms-ba16_2g.cfg |  24 -
 board/advantech/dms-ba16/micron-1g.cfg   |  63 ---
 board/advantech/dms-ba16/samsung-2g.cfg  |  63 ---
 configs/dms-ba16-1g_defconfig            |  66 ---
 configs/dms-ba16_defconfig               |  65 ---
 include/configs/advantech_dms-ba16.h     | 222 --------
 14 files changed, 1272 deletions(-)
 delete mode 100644 board/advantech/dms-ba16/Kconfig
 delete mode 100644 board/advantech/dms-ba16/MAINTAINERS
 delete mode 100644 board/advantech/dms-ba16/Makefile
 delete mode 100644 board/advantech/dms-ba16/clocks.cfg
 delete mode 100644 board/advantech/dms-ba16/ddr-setup.cfg
 delete mode 100644 board/advantech/dms-ba16/dms-ba16.c
 delete mode 100644 board/advantech/dms-ba16/dms-ba16_1g.cfg
 delete mode 100644 board/advantech/dms-ba16/dms-ba16_2g.cfg
 delete mode 100644 board/advantech/dms-ba16/micron-1g.cfg
 delete mode 100644 board/advantech/dms-ba16/samsung-2g.cfg
 delete mode 100644 configs/dms-ba16-1g_defconfig
 delete mode 100644 configs/dms-ba16_defconfig
 delete mode 100644 include/configs/advantech_dms-ba16.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index dacfe623903c..ebc5e6c01d97 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -111,12 +111,6 @@ choice
 	prompt "MX6 board select"
 	optional
 
-config TARGET_ADVANTECH_DMS_BA16
-	bool "Advantech dms-ba16"
-	depends on MX6Q
-	select BOARD_LATE_INIT
-	imply CMD_SATA
-
 config TARGET_APALIS_IMX6
 	bool "Toradex Apalis iMX6 board"
 	depends on MX6Q
@@ -700,7 +694,6 @@ config SYS_SOC
 
 source "board/ge/bx50v3/Kconfig"
 source "board/ge/b1x5v2/Kconfig"
-source "board/advantech/dms-ba16/Kconfig"
 source "board/aristainetos/Kconfig"
 source "board/armadeus/opos6uldev/Kconfig"
 source "board/bachmann/ot1200/Kconfig"
diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig
deleted file mode 100644
index 040eb866b53d..000000000000
--- a/board/advantech/dms-ba16/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-if TARGET_ADVANTECH_DMS_BA16
-
-choice
-	prompt "DDR Size"
-	default SYS_DDR_2G
-
-config SYS_DDR_1G
-	bool "1GiB"
-
-config SYS_DDR_2G
-	bool "2GiB"
-
-endchoice
-
-config IMX_CONFIG
-	default "board/advantech/dms-ba16/dms-ba16_2g.cfg" if SYS_DDR_2G
-	default "board/advantech/dms-ba16/dms-ba16_1g.cfg" if SYS_DDR_1G
-
-config SYS_BOARD
-	default "dms-ba16"
-
-config SYS_VENDOR
-	default "advantech"
-
-config SYS_SOC
-	default "mx6"
-
-config SYS_CONFIG_NAME
-	default "advantech_dms-ba16"
-
-endif
diff --git a/board/advantech/dms-ba16/MAINTAINERS b/board/advantech/dms-ba16/MAINTAINERS
deleted file mode 100644
index e8ea3dd7b3cf..000000000000
--- a/board/advantech/dms-ba16/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-ADVANTECH_DMS-BA16 BOARD
-M:	Akshay Bhat <akshaybhat@timesys.com>
-M:	Ken Lin <Ken.Lin@advantech.com.tw>
-S:	Maintained
-F:	board/advantech/dms-ba16/
-F:	include/configs/advantech_dms-ba16.h
-F:	configs/dms-ba16_defconfig
-F:	configs/dms-ba16-1g_defconfig
diff --git a/board/advantech/dms-ba16/Makefile b/board/advantech/dms-ba16/Makefile
deleted file mode 100644
index b87fc29f065e..000000000000
--- a/board/advantech/dms-ba16/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2016 Timesys Corporation
-# Copyright 2016 Advantech Corporation
-
-obj-y  := dms-ba16.o
diff --git a/board/advantech/dms-ba16/clocks.cfg b/board/advantech/dms-ba16/clocks.cfg
deleted file mode 100644
index abc769c4e5fd..000000000000
--- a/board/advantech/dms-ba16/clocks.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  1    --> CKO1 enabled
- * cko1_div 111  --> divide by 8
- * cko1_sel 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/advantech/dms-ba16/ddr-setup.cfg b/board/advantech/dms-ba16/ddr-setup.cfg
deleted file mode 100644
index 4c43e648f796..000000000000
--- a/board/advantech/dms-ba16/ddr-setup.cfg
+++ /dev/null
@@ -1,39 +0,0 @@
-/* DDR IO */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
-DATA 4, MX6_IOM_GRP_DDRPKE,   0x00000000
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
-DATA 4, MX6_IOM_DRAM_CAS,     0x00000030
-DATA 4, MX6_IOM_DRAM_RAS,     0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS,    0x00000030
-DATA 4, MX6_IOM_DRAM_RESET,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDBA2,   0x00000000
-DATA 4, MX6_IOM_DRAM_SDODT0,  0x00000030
-DATA 4, MX6_IOM_DRAM_SDODT1,  0x00000030
-DATA 4, MX6_IOM_GRP_CTLDS,    0x00000030
-DATA 4, MX6_IOM_DDRMODE_CTL,  0x00020000
-DATA 4, MX6_IOM_DRAM_SDQS0,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6,   0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7,   0x00000030
-DATA 4, MX6_IOM_GRP_DDRMODE,  0x00020000
-DATA 4, MX6_IOM_GRP_B0DS,     0x00000030
-DATA 4, MX6_IOM_GRP_B1DS,     0x00000030
-DATA 4, MX6_IOM_GRP_B2DS,     0x00000030
-DATA 4, MX6_IOM_GRP_B3DS,     0x00000030
-DATA 4, MX6_IOM_GRP_B4DS,     0x00000030
-DATA 4, MX6_IOM_GRP_B5DS,     0x00000030
-DATA 4, MX6_IOM_GRP_B6DS,     0x00000030
-DATA 4, MX6_IOM_GRP_B7DS,     0x00000030
-DATA 4, MX6_IOM_DRAM_DQM0,    0x00000030
-DATA 4, MX6_IOM_DRAM_DQM1,    0x00000030
-DATA 4, MX6_IOM_DRAM_DQM2,    0x00000030
-DATA 4, MX6_IOM_DRAM_DQM3,    0x00000030
-DATA 4, MX6_IOM_DRAM_DQM4,    0x00000030
-DATA 4, MX6_IOM_DRAM_DQM5,    0x00000030
-DATA 4, MX6_IOM_DRAM_DQM6,    0x00000030
-DATA 4, MX6_IOM_DRAM_DQM7,    0x00000030
diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
deleted file mode 100644
index 20820fdf0762..000000000000
--- a/board/advantech/dms-ba16/dms-ba16.c
+++ /dev/null
@@ -1,629 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Timesys Corporation
- * Copyright 2016 Advantech Corporation
- * Copyright 2012 Freescale Semiconductor, Inc.
- */
-
-#include <init.h>
-#include <net.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <input.h>
-#include <pwm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
-	PAD_CTL_HYS)
-
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
-	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
-	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const uart3_pads[] = {
-	MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	/* AR8033 PHY Reset */
-	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
-	/* Reset AR8033 PHY */
-	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-	mdelay(10);
-	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
-	mdelay(1);
-}
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-static struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-static struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
-		.gp = IMX_GPIO_NR(1, 6)
-	}
-};
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
-}
-
-static void setup_spi(void)
-{
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-#endif
-
-static iomux_v3_cfg_t const pcie_pads[] = {
-	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_pcie(void)
-{
-	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
-}
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
-	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC2_BASE_ADDR},
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
-#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 11)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = 1; /* eMMC is always present */
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = !gpio_get_value(USDHC4_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
-	int ret;
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			gpio_direction_input(USDHC2_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			gpio_direction_input(USDHC4_CD_GPIO);
-			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers\n"
-			       "(%d) then supported by the board (%d)\n",
-			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	/* set device address 0x7 */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	/* offset 0x8016: CLK_25M Clock Select */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	/* enable register write, no post increment, address 0x7 */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-	/* set to 125 MHz from local PLL source */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
-	/* set debug port address: SerDes Test and System Mode Control */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-	/* enable rgmii tx clock delay */
-	/* set the reserved bits to avoid board specific voltage peak issue*/
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
-
-	return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	mx6_rgmii_rework(phydev);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-static iomux_v3_cfg_t const backlight_pads[] = {
-	/* Power for LVDS Display */
-	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
-	/* Backlight enable for LVDS display */
-	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
-	/* backlight PWM brightness control */
-	MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
-	imx_enable_hdmi_phy();
-}
-
-int board_cfb_skip(void)
-{
-	gpio_direction_output(LVDS_POWER_GP, 1);
-
-	return 0;
-}
-
-static int detect_baseboard(struct display_info_t const *dev)
-{
-	return 0 == dev->addr;
-}
-
-struct display_info_t const displays[] = {{
-	.bus	= -1,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_baseboard,
-	.enable	= NULL,
-	.mode	= {
-		.name           = "SHARP-LQ156M1LG21",
-		.refresh        = 60,
-		.xres           = 1920,
-		.yres           = 1080,
-		.pixclock       = 7851,
-		.left_margin    = 100,
-		.right_margin   = 40,
-		.upper_margin   = 30,
-		.lower_margin   = 3,
-		.hsync_len      = 10,
-		.vsync_len      = 2,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED
-} }, {
-	.bus	= -1,
-	.addr	= 3,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
-	.enable	= do_enable_hdmi,
-	.mode	= {
-		.name           = "HDMI",
-		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-
-	imx_setup_hdmi();
-
-	/* Set LDB_DI0 as clock source for IPU_DI0 */
-	clrsetbits_le32(&mxc_ccm->chsccdr,
-			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
-			(CHSCCDR_CLK_SEL_LDB_DI0 <<
-			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
-
-	/* Turn on IPU LDB DI0 clocks */
-	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-
-	enable_ipu_clock();
-
-	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
-	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
-	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
-	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
-	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
-	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
-	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
-	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
-	       &iomux->gpr[2]);
-
-	clrsetbits_le32(&iomux->gpr[3],
-			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
-			IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
-			IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
-		       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
-
-	/* backlights off until needed */
-	imx_iomux_v3_setup_multiple_pads(backlight_pads,
-					 ARRAY_SIZE(backlight_pads));
-
-	gpio_direction_input(LVDS_POWER_GP);
-	gpio_direction_input(LVDS_BACKLIGHT_GP);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
-	return 1;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	setup_iomux_enet();
-	setup_pcie();
-
-	return cpu_eth_init(bis);
-}
-
-static iomux_v3_cfg_t const misc_pads[] = {
-	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
-	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
-	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
-	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
-	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
-	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
-};
-#define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
-#define WIFI_EN	IMX_GPIO_NR(6, 14)
-
-int setup_ba16_sata(void)
-{
-	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	int ret;
-
-	ret = enable_sata_clock();
-	if (ret)
-		return ret;
-
-	clrsetbits_le32(&iomuxc_regs->gpr[13],
-			IOMUXC_GPR13_SATA_MASK,
-			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
-			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
-			|IOMUXC_GPR13_SATA_SPEED_3G
-			|(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
-			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
-			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
-			|IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
-			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	imx_iomux_v3_setup_multiple_pads(misc_pads,
-					 ARRAY_SIZE(misc_pads));
-
-	setup_iomux_uart();
-
-#if defined(CONFIG_VIDEO_IPUV3)
-	/* Set LDB clock to PLL2 PFD0 */
-	select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
-#endif
-	return 0;
-}
-
-int board_init(void)
-{
-	gpio_direction_output(SUS_S3_OUT, 1);
-	gpio_direction_output(WIFI_EN, 1);
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
-#endif
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_MXC_SPI
-	setup_spi();
-#endif
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-	/* 4 bit bus width */
-	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
-	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
-	{NULL,	 0},
-};
-#endif
-
-void pmic_init(void)
-{
-
-#define DA9063_ADDR 0x58
-#define BCORE2_CONF 0x9D
-#define BCORE1_CONF 0x9E
-#define BPRO_CONF 0x9F
-#define BIO_CONF 0xA0
-#define BMEM_CONF 0xA1
-#define BPERI_CONF 0xA2
-#define MODE_BIT_H 7
-#define MODE_BIT_L 6
-
-        uchar val;
-        i2c_set_bus_num(2);
-
-        i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
-        val |= (1 << MODE_BIT_H);
-        val &= ~(1 << MODE_BIT_L);
-        i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
-
-        i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
-        val |= (1 << MODE_BIT_H);
-        val &= ~(1 << MODE_BIT_L);
-        i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
-
-        i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
-        val |= (1 << MODE_BIT_H);
-        val &= ~(1 << MODE_BIT_L);
-        i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
-
-        i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
-        val |= (1 << MODE_BIT_H);
-        val &= ~(1 << MODE_BIT_L);
-        i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
-
-        i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
-        val |= (1 << MODE_BIT_H);
-        val &= ~(1 << MODE_BIT_L);
-        i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
-
-        i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
-        val |= (1 << MODE_BIT_H);
-        val &= ~(1 << MODE_BIT_L);
-        i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
-
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
-	add_board_boot_modes(board_boot_modes);
-#endif
-
-#if defined(CONFIG_VIDEO_IPUV3)
-	/*
-	 * We need@least 200ms between power on and backlight on
-	 * as per specifications from CHI MEI
-	 */
-	mdelay(250);
-
-	/* enable backlight PWM 1 */
-	pwm_init(0, 0, 0);
-
-	/* duty cycle 5000000ns, period: 5000000ns */
-	pwm_config(0, 5000000, 5000000);
-
-	/* Backlight Power */
-	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
-
-	pwm_enable(0);
-#endif
-
-#ifdef CONFIG_SATA
-	setup_ba16_sata();
-#endif
-
-        /* board specific pmic init */
-        pmic_init();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
-	return 0;
-}
diff --git a/board/advantech/dms-ba16/dms-ba16_1g.cfg b/board/advantech/dms-ba16/dms-ba16_1g.cfg
deleted file mode 100644
index 1c737baaf28b..000000000000
--- a/board/advantech/dms-ba16/dms-ba16_1g.cfg
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * Copyright 2015 Timesys Corporation.
- * Copyright 2015 General Electric Company
- *
- * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-IMAGE_VERSION 2
-BOOT_FROM sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#include "micron-1g.cfg"
-#include "clocks.cfg"
diff --git a/board/advantech/dms-ba16/dms-ba16_2g.cfg b/board/advantech/dms-ba16/dms-ba16_2g.cfg
deleted file mode 100644
index 371a84eb7e2b..000000000000
--- a/board/advantech/dms-ba16/dms-ba16_2g.cfg
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * Copyright 2015 Timesys Corporation.
- * Copyright 2015 General Electric Company
- *
- * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-IMAGE_VERSION 2
-BOOT_FROM sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#include "samsung-2g.cfg"
-#include "clocks.cfg"
diff --git a/board/advantech/dms-ba16/micron-1g.cfg b/board/advantech/dms-ba16/micron-1g.cfg
deleted file mode 100644
index 8cfefe28e21c..000000000000
--- a/board/advantech/dms-ba16/micron-1g.cfg
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Calibrations */
-/* ZQ */
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
-/* write leveling */
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
-/* Read DQS Gating calibration */
-DATA 4, MX6_MMDC_P0_MPDGCTRL0,   0x43480350
-DATA 4, MX6_MMDC_P0_MPDGCTRL1,   0x033C0340
-DATA 4, MX6_MMDC_P1_MPDGCTRL0,   0x43480350
-DATA 4, MX6_MMDC_P1_MPDGCTRL1,   0x03340314
-/* Read calibration */
-DATA 4, MX6_MMDC_P0_MPRDDLCTL,   0x382E2C32
-DATA 4, MX6_MMDC_P1_MPRDDLCTL,   0x38363044
-/* Write calibration */
-DATA 4 MX6_MMDC_P0_MPWRDLCTL,    0x3A38403A
-DATA 4 MX6_MMDC_P1_MPWRDLCTL,    0x4432483E
-/* read data bit delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/* Complete calibration by forced measurment */
-DATA 4, MX6_MMDC_P0_MPMUR0,	0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0,	0x00000800
-
-/* MMDC init */
-DATA 4, MX6_MMDC_P0_MDPDC,      0x00020036
-DATA 4, MX6_MMDC_P0_MDOTC,      0x09444040
-DATA 4, MX6_MMDC_P0_MDCFG0,     0x555A79A5
-DATA 4, MX6_MMDC_P0_MDCFG1,     0xDB538E64
-DATA 4, MX6_MMDC_P0_MDCFG2,     0x01ff00db
-DATA 4, MX6_MMDC_P0_MDMISC,     0x00001740
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00008000
-DATA 4, MX6_MMDC_P0_MDRWD,      0x000026d2
-DATA 4, MX6_MMDC_P0_MDOR,       0x005a1023
-DATA 4, MX6_MMDC_P0_MDASP,      0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL,      0x831a0000
-
-/* Initialize memory */
-DATA 4, MX6_MMDC_P0_MDSCR,      0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR,      0x0408803a
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR,      0x0000803b
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00048039
-DATA 4, MX6_MMDC_P0_MDSCR,      0x09408030
-DATA 4, MX6_MMDC_P0_MDSCR,      0x09408038
-DATA 4, MX6_MMDC_P0_MDSCR,      0x04008040
-DATA 4, MX6_MMDC_P0_MDSCR,      0x04008048
-DATA 4, MX6_MMDC_P0_MDREF,      0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL,  0x00033337
-DATA 4, MX6_MMDC_P1_MPODTCTRL,  0x00033337
-DATA 4, MX6_MMDC_P0_MDPDC,      0x00025576
-DATA 4, MX6_MMDC_P0_MAPSR,      0x00011006
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00000000
diff --git a/board/advantech/dms-ba16/samsung-2g.cfg b/board/advantech/dms-ba16/samsung-2g.cfg
deleted file mode 100644
index 4166cc9c57fb..000000000000
--- a/board/advantech/dms-ba16/samsung-2g.cfg
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Calibrations */
-/* ZQ */
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL,  0xa1390003
-/* write leveling */
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
-/* Read DQS Gating calibration */
-DATA 4, MX6_MMDC_P0_MPDGCTRL0,   0x45380544
-DATA 4, MX6_MMDC_P0_MPDGCTRL1,   0x05280530
-DATA 4, MX6_MMDC_P1_MPDGCTRL0,   0x4530053C
-DATA 4, MX6_MMDC_P1_MPDGCTRL1,   0x0530050C
-/* Read calibration */
-DATA 4, MX6_MMDC_P0_MPRDDLCTL,   0x36303032
-DATA 4, MX6_MMDC_P1_MPRDDLCTL,   0x38363042
-/* Write calibration */
-DATA 4, MX6_MMDC_P0_MPWRDLCTL,   0x3A3A423E
-DATA 4, MX6_MMDC_P1_MPWRDLCTL,   0x4A38483E
-/* read data bit delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/* Complete calibration by forced measurment */
-DATA 4, MX6_MMDC_P0_MPMUR0,     0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0,     0x00000800
-
-/* MMDC init */
-DATA 4, MX6_MMDC_P0_MDPDC,      0x00020036
-DATA 4, MX6_MMDC_P0_MDOTC,      0x09444040
-DATA 4, MX6_MMDC_P0_MDCFG0,     0x8A8F79A4
-DATA 4, MX6_MMDC_P0_MDCFG1,     0xDB538E64
-DATA 4, MX6_MMDC_P0_MDCFG2,     0x01ff00db
-DATA 4, MX6_MMDC_P0_MDMISC,     0x00001740
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00008000
-DATA 4, MX6_MMDC_P0_MDRWD,      0x000026d2
-DATA 4, MX6_MMDC_P0_MDOR,       0x008F1023
-DATA 4, MX6_MMDC_P0_MDASP,      0x00000047
-DATA 4, MX6_MMDC_P0_MDCTL,      0x841a0000
-
-/* Initialize memory */
-DATA 4, MX6_MMDC_P0_MDSCR,      0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR,      0x0408803a
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR,      0x0000803b
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00408031
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00408039
-DATA 4, MX6_MMDC_P0_MDSCR,      0x09408030
-DATA 4, MX6_MMDC_P0_MDSCR,      0x09408038
-DATA 4, MX6_MMDC_P0_MDSCR,      0x04008040
-DATA 4, MX6_MMDC_P0_MDSCR,      0x04008048
-DATA 4, MX6_MMDC_P0_MDREF,      0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL,  0x00011117
-DATA 4, MX6_MMDC_P1_MPODTCTRL,  0x00011117
-DATA 4, MX6_MMDC_P0_MDPDC,      0x00025576
-DATA 4, MX6_MMDC_P0_MAPSR,      0x00011006
-DATA 4, MX6_MMDC_P0_MDSCR,      0x00000000
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
deleted file mode 100644
index f7b6bc6dedb3..000000000000
--- a/configs/dms-ba16-1g_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MX6Q=y
-CONFIG_TARGET_ADVANTECH_DMS_BA16=y
-CONFIG_SYS_DDR_1G=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_BOOTDELAY=1
-CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DWC_AHSATA=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_USDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_MII=y
-CONFIG_PWM_IMX=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Advantech"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_SPLASH_SCREEN=y
-CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
deleted file mode 100644
index c70808745478..000000000000
--- a/configs/dms-ba16_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MX6Q=y
-CONFIG_TARGET_ADVANTECH_DMS_BA16=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_BOOTDELAY=1
-CONFIG_DEFAULT_FDT_FILE="imx6q-dms-ba16.dtb"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DWC_AHSATA=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_USDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_MII=y
-CONFIG_PWM_IMX=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Advantech"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_SPLASH_SCREEN=y
-CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
deleted file mode 100644
index 1ecb7c9df895..000000000000
--- a/include/configs/advantech_dms-ba16.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Timesys Corporation
- * Copyright (C) 2016 Advantech Corporation
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- */
-
-#ifndef __ADVANTECH_DMSBA16_CONFIG_H
-#define __ADVANTECH_DMSBA16_CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-#include <asm/mach-imx/gpio.h>
-
-#define CONFIG_BOARD_NAME	"Advantech DMS-BA16"
-
-#define CONFIG_MXC_UART_BASE	UART4_BASE
-#define CONSOLE_DEV	"ttymxc3"
-#define CONFIG_EXTRA_BOOTARGS	"panic=10"
-
-#define CONFIG_BOOT_DIR	""
-#define CONFIG_LOADCMD "fatload"
-#define CONFIG_RFSPART "2"
-
-#include "mx6_common.h"
-#include <linux/sizes.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
-
-/* SATA Configs */
-#define CONFIG_SYS_SATA_MAX_DEVICE	1
-#define CONFIG_DWC_AHSATA_PORT_ID	0
-#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
-
-/* USB Configs */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS	0
-
-#define CONFIG_USBD_HS
-
-/* Networking Configs */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RGMII
-#define CONFIG_ETHPRIME		"FEC"
-#define CONFIG_FEC_MXC_PHYADDR		4
-
-/* Serial Flash */
-
-#define CONFIG_LOADADDR	0x12000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"script=boot.scr\0" \
-	"image=" CONFIG_BOOT_DIR "/uImage\0" \
-	"uboot=u-boot.imx\0" \
-	"fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"fdt_addr=0x18000000\0" \
-	"boot_fdt=yes\0" \
-	"ip_dyn=yes\0" \
-	"console=" CONSOLE_DEV "\0" \
-	"fdt_high=0xffffffff\0"	  \
-	"initrd_high=0xffffffff\0" \
-	"sddev=0\0" \
-	"emmcdev=1\0" \
-	"partnum=1\0" \
-	"loadcmd=" CONFIG_LOADCMD "\0" \
-	"rfspart=" CONFIG_RFSPART "\0" \
-	"update_sd_firmware=" \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"if mmc dev ${mmcdev}; then "	\
-			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
-				"setexpr fw_sz ${filesize} / 0x200; " \
-				"setexpr fw_sz ${fw_sz} + 1; "	\
-				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
-			"fi; "	\
-		"fi\0" \
-	"update_sf_uboot=" \
-		"if tftp $loadaddr $uboot; then " \
-			"sf probe; " \
-			"sf erase 0 0xC0000; " \
-			"sf write $loadaddr 0x400 $filesize; " \
-			"echo 'U-Boot upgraded. Please reset'; " \
-		"fi\0" \
-	"setargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \
-	"loadbootscript=" \
-		"${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
-	"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
-		" source\0" \
-	"loadimage=" \
-		"${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
-	"loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
-	"tryboot=" \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loadimage; then " \
-				"run doboot; " \
-			"fi; " \
-		"fi;\0" \
-	"doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
-		"run setargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootm; " \
-		"fi;\0" \
-	"netargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
-		"run netargs; " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootm; " \
-		"fi;\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"usb start; " \
-	"setenv dev usb; " \
-	"setenv devnum 0; " \
-	"setenv rootdev sda${rfspart}; " \
-	"run tryboot; " \
-	\
-	"setenv dev mmc; " \
-	"setenv rootdev mmcblk0p${rfspart}; " \
-	\
-	"setenv devnum ${sddev}; " \
-	"if mmc dev ${devnum}; then " \
-		"run tryboot; " \
-	"fi; " \
-	\
-	"setenv devnum ${emmcdev}; " \
-	"setenv rootdev mmcblk${emmcdev}p${rfspart}; " \
-	"if mmc dev ${devnum}; then " \
-		"run tryboot; " \
-	"fi; " \
-	\
-	"bmode usb; " \
-
-#define CONFIG_ARP_TIMEOUT     200UL
-
-/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* FLASH and environment organization */
-
-#define CONFIG_SYS_FSL_USDHC_NUM        3
-
-/* Framebuffer */
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-#define CONFIG_IMX6_PWM_PER_CLK         66000000
-
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO      IMX_GPIO_NR(7, 12)
-#define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 5)
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_SPEED            100000
-#define CONFIG_SYS_I2C_MXC_I2C1
-#define CONFIG_SYS_I2C_MXC_I2C2
-#define CONFIG_SYS_I2C_MXC_I2C3
-
-#endif	/* __ADVANTECH_DMSBA16_CONFIG_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 06/16] arm: Remove dms-ba16 board
  2021-02-10  2:42 ` [PATCH 06/16] arm: Remove dms-ba16 board Tom Rini
@ 2021-04-12  0:25   ` Tom Rini
  0 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-04-12  0:25 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:47PM -0500, Tom Rini wrote:

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.
> 
> Cc: Akshay Bhat <akshaybhat@timesys.com>
> Cc: Ken Lin <Ken.Lin@advantech.com.tw>
> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 07/16] arm: Remove ot1200 board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (4 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 06/16] arm: Remove dms-ba16 board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-17  9:58   ` Christian Gmeiner
  2021-04-12  0:25   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 08/16] arm: Remove mx53loco board Tom Rini
                   ` (9 subsequent siblings)
  15 siblings, 2 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  In order to
convert to using the DWC SATA driver under DM further migrations are
required.

Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/mach-imx/mx6/Kconfig              |   6 -
 board/bachmann/ot1200/Kconfig              |  12 -
 board/bachmann/ot1200/MAINTAINERS          |   6 -
 board/bachmann/ot1200/Makefile             |  11 -
 board/bachmann/ot1200/README               |  20 --
 board/bachmann/ot1200/mx6q_4x_mt41j128.cfg | 154 ---------
 board/bachmann/ot1200/ot1200.c             | 359 ---------------------
 board/bachmann/ot1200/ot1200_spl.c         | 152 ---------
 configs/ot1200_defconfig                   |  59 ----
 configs/ot1200_spl_defconfig               |  70 ----
 include/configs/ot1200.h                   |  95 ------
 11 files changed, 944 deletions(-)
 delete mode 100644 board/bachmann/ot1200/Kconfig
 delete mode 100644 board/bachmann/ot1200/MAINTAINERS
 delete mode 100644 board/bachmann/ot1200/Makefile
 delete mode 100644 board/bachmann/ot1200/README
 delete mode 100644 board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
 delete mode 100644 board/bachmann/ot1200/ot1200.c
 delete mode 100644 board/bachmann/ot1200/ot1200_spl.c
 delete mode 100644 configs/ot1200_defconfig
 delete mode 100644 configs/ot1200_spl_defconfig
 delete mode 100644 include/configs/ot1200.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ebc5e6c01d97..0660035a9fd2 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -470,11 +470,6 @@ config TARGET_OPOS6ULDEV
 	depends on MX6UL
 	select MX6UL_OPOS6UL
 
-config TARGET_OT1200
-	bool "Bachmann OT1200"
-	select SUPPORT_SPL
-	imply CMD_SATA
-
 config TARGET_PICO_IMX6
 	bool "PICO-IMX6"
 	depends on MX6QDL
@@ -696,7 +691,6 @@ source "board/ge/bx50v3/Kconfig"
 source "board/ge/b1x5v2/Kconfig"
 source "board/aristainetos/Kconfig"
 source "board/armadeus/opos6uldev/Kconfig"
-source "board/bachmann/ot1200/Kconfig"
 source "board/barco/platinum/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
deleted file mode 100644
index 4ccb60a97fed..000000000000
--- a/board/bachmann/ot1200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OT1200
-
-config SYS_BOARD
-	default "ot1200"
-
-config SYS_VENDOR
-	default "bachmann"
-
-config SYS_CONFIG_NAME
-	default "ot1200"
-
-endif
diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS
deleted file mode 100644
index ad75c24ee469..000000000000
--- a/board/bachmann/ot1200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BACHMANN ELECTRONIC OT1200 BOARD
-M:	Christian Gmeiner <christian.gmeiner@gmail.com>
-S:	Maintained
-F:	board/bachmann/ot1200
-F:	include/configs/ot1200.h
-F:	configs/ot1200*_defconfig
diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
deleted file mode 100644
index 73000e3d3ce6..000000000000
--- a/board/bachmann/ot1200/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
-# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
-# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
-
-ifdef CONFIG_SPL_BUILD
-obj-y  := ot1200.o ot1200_spl.o
-else
-obj-y  := ot1200.o
-endif
diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README
deleted file mode 100644
index c03d44e458a4..000000000000
--- a/board/bachmann/ot1200/README
+++ /dev/null
@@ -1,20 +0,0 @@
-U-Boot for the Bachmann electronic GmbH OT1200 devices
-
-There are two different versions of the base board, which differ
-in the way ethernet is done. The variant detection is done during
-runtime based on the address of the found phy.
-
-- "mr" variant
-FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
-port is always up and auto-negotiation is not possible.
-
-- normal variant
-FEC is connected to a normal phy and auto-negotiation is possible.
-
-
-The variant name is part of the dtb file name loaded by u-boot. This
-make is possible to boot the linux kernel and make use variant specific
-devicetree (fixed-phy link).
-
-In order to support different display resoltuions/sizes the OT1200 devices
-are making use of EDID data stored in an i2c EEPROM.
diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
deleted file mode 100644
index f4f605fc8d0f..000000000000
--- a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
+++ /dev/null
@@ -1,154 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7974
-DATA 4 0x021b0010 0xDB538F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005A1023
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x19308030
-DATA 4 0x021b001c 0x19308038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
-
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4 0x020c4060 0x000000fb
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
deleted file mode 100644
index d3af634e3aba..000000000000
--- a/board/bachmann/ot1200/ot1200.c
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014, Bachmann electronic GmbH
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <env.h>
-#include <malloc.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <pca953x.h>
-#include <asm/gpio.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define OUTPUT_40OHM	(PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
-#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL	(PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |	\
-	PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL	(PAD_CTL_HYS | OUTPUT_40OHM |		\
-	PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |	\
-	PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-static iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_DISP0_DAT3__ECSPI3_SS0  | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT4__ECSPI3_SS1  | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
-static void setup_iomux_spi(void)
-{
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
-}
-
-static iomux_v3_cfg_t const feature_pads[] = {
-	/* SD card detect */
-	MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
-
-	/* eMMC soldered? */
-	MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
-};
-
-static void setup_iomux_features(void)
-{
-	imx_iomux_v3_setup_multiple_pads(feature_pads,
-		ARRAY_SIZE(feature_pads));
-}
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C2 - EEPROM */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
-		.gp = IMX_GPIO_NR(3, 16)
-	}
-};
-
-/* I2C3 - IO expander  */
-static struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
-		.gp = IMX_GPIO_NR(3, 17)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-
-static void setup_iomux_i2c(void)
-{
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-}
-
-static void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00C03F3F, &ccm->CCGR0);
-	writel(0x0030FC33, &ccm->CCGR1);
-	writel(0x0FFFC000, &ccm->CCGR2);
-	writel(0x3FF00000, &ccm->CCGR3);
-	writel(0x00FFF300, &ccm->CCGR4);
-	writel(0x0F0000C3, &ccm->CCGR5);
-	writel(0x000003FF, &ccm->CCGR6);
-}
-
-int board_early_init_f(void)
-{
-	ccgr_init();
-	gpr_init();
-
-	setup_iomux_uart();
-	setup_iomux_spi();
-	setup_iomux_i2c();
-	setup_iomux_features();
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret;
-
-	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-		gpio_direction_input(IMX_GPIO_NR(4, 5));
-		ret = gpio_get_value(IMX_GPIO_NR(4, 5));
-	} else {
-		gpio_direction_input(IMX_GPIO_NR(1, 5));
-		ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
-	}
-
-	return ret;
-}
-
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-int board_mmc_init(struct bd_info *bis)
-{
-	int ret;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
-	usdhc_cfg[0].max_bus_width = 8;
-	usdhc_cfg[1].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) then supported by the board (%d)\n",
-				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static void leds_on(void)
-{
-	/* turn on all possible leds connected via GPIO expander */
-	i2c_set_bus_num(2);
-	pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
-	pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
-}
-
-static void backlight_lcd_off(void)
-{
-	unsigned gpio = IMX_GPIO_NR(2, 0);
-	gpio_direction_output(gpio, 0);
-
-	gpio = IMX_GPIO_NR(2, 3);
-	gpio_direction_output(gpio, 0);
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	uint32_t base = IMX_FEC_BASE;
-	struct mii_dev *bus = NULL;
-	struct phy_device *phydev = NULL;
-	int ret;
-
-	setup_iomux_enet();
-
-	bus = fec_get_miibus(base, -1);
-	if (!bus)
-		return -EINVAL;
-
-	/* scan phy 0 and 5 */
-	phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
-	if (!phydev) {
-		ret = -EINVAL;
-		goto free_bus;
-	}
-
-	/* depending on the phy address we can detect our board version */
-	if (phydev->addr == 0)
-		env_set("boardver", "");
-	else
-		env_set("boardver", "mr");
-
-	printf("using phy at %d\n", phydev->addr);
-	ret = fec_probe(bis, -1, base, bus, phydev);
-	if (ret)
-		goto free_phydev;
-
-	return 0;
-
-free_phydev:
-	free(phydev);
-free_bus:
-	free(bus);
-	return ret;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	backlight_lcd_off();
-
-	leds_on();
-
-#ifdef CONFIG_SATA
-	setup_sata();
-#endif
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: "CONFIG_SYS_BOARD"\n");
-	return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-	/* 4 bit bus width */
-	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
-	{NULL,		0},
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
-	add_board_boot_modes(board_boot_modes);
-#endif
-	return 0;
-}
diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c
deleted file mode 100644
index 7fbd6f2c5d3e..000000000000
--- a/board/bachmann/ot1200/ot1200_spl.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015, Bachmann electronic GmbH
- */
-
-#include <common.h>
-#include <init.h>
-#include <spl.h>
-#include <asm/arch/mx6-ddr.h>
-
-/* Configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
-	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
-	.dram_sdclk_0   = 0x00000028,
-	.dram_sdclk_1   = 0x00000028,
-	.dram_cas       = 0x00000028,
-	.dram_ras       = 0x00000028,
-	.dram_reset     = 0x00000028,
-	/* SDCKE[0:1]: 100k pull-up */
-	.dram_sdcke0    = 0x00003000,
-	.dram_sdcke1    = 0x00003000,
-	/* SDBA2: pull-up disabled */
-	.dram_sdba2	    = 0x00000000,
-	/* SDODT[0:1]: 100k pull-up, 48 ohm */
-	.dram_sdodt0    = 0x00000028,
-	.dram_sdodt1    = 0x00000028,
-	/* SDQS[0:7]: Differential input, 48 ohm */
-	.dram_sdqs0     = 0x00000028,
-	.dram_sdqs1     = 0x00000028,
-	.dram_sdqs2     = 0x00000028,
-	.dram_sdqs3     = 0x00000028,
-	.dram_sdqs4     = 0x00000028,
-	.dram_sdqs5     = 0x00000028,
-	.dram_sdqs6     = 0x00000028,
-	.dram_sdqs7     = 0x00000028,
-	/* DQM[0:7]: Differential input, 48 ohm */
-	.dram_dqm0      = 0x00000028,
-	.dram_dqm1      = 0x00000028,
-	.dram_dqm2      = 0x00000028,
-	.dram_dqm3      = 0x00000028,
-	.dram_dqm4      = 0x00000028,
-	.dram_dqm5      = 0x00000028,
-	.dram_dqm6      = 0x00000028,
-	.dram_dqm7      = 0x00000028,
-};
-
-/* Configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
-	/* DDR3 */
-	.grp_ddr_type    = 0x000c0000,
-	.grp_ddrmode_ctl = 0x00020000,
-	/* Disable DDR pullups */
-	.grp_ddrpke      = 0x00000000,
-	/* ADDR[00:16], SDBA[0:1]: 48 ohm */
-	.grp_addds       = 0x00000028,
-	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
-	.grp_ctlds       = 0x00000028,
-	/* DATA[00:63]: Differential input, 48 ohm */
-	.grp_ddrmode     = 0x00020000,
-	.grp_b0ds        = 0x00000028,
-	.grp_b1ds        = 0x00000028,
-	.grp_b2ds        = 0x00000028,
-	.grp_b3ds        = 0x00000028,
-	.grp_b4ds        = 0x00000028,
-	.grp_b5ds        = 0x00000028,
-	.grp_b6ds        = 0x00000028,
-	.grp_b7ds        = 0x00000028,
-};
-
-static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
-	/* Width of data bus: 0=16, 1=32, 2=64 */
-	.dsize      = 2,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density = 32, /* 32Gb per CS */
-	/* Single chip select */
-	.ncs        = 1,
-	.cs1_mirror = 0,	/* war 0 */
-	.rtt_wr     = 1,	/* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
-	.rtt_nom    = 1,	/* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
-	.walat      = 1,	/* Write additional latency */
-	.ralat      = 5,	/* Read additional latency */
-	.mif3_mode  = 3,	/* Command prediction working mode */
-	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
-	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-	.refsel = 1,		/* Refresh cycles at 32KHz */
-	.refr = 7,		/* 8 refresh commands per refresh cycle */
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg micron_2gib_1600 = {
-	.mem_speed = 1600,
-	.density   = 2,
-	.width     = 16,
-	.banks     = 8,
-	.rowaddr   = 14,
-	.coladdr   = 10,
-	.pagesz    = 2,
-	.trcd      = 1375,
-	.trcmin    = 4875,
-	.trasmin   = 3500,
-	.SRT       = 1,
-};
-
-static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
-	/* write leveling calibration determine */
-	.p0_mpwldectrl0 = 0x00260025,
-	.p0_mpwldectrl1 = 0x00270021,
-	.p1_mpwldectrl0 = 0x00180034,
-	.p1_mpwldectrl1 = 0x00180024,
-	/* Read DQS Gating calibration */
-	.p0_mpdgctrl0   = 0x04380344,
-	.p0_mpdgctrl1   = 0x0330032C,
-	.p1_mpdgctrl0   = 0x0338033C,
-	.p1_mpdgctrl1   = 0x032C0300,
-	/* Read Calibration: DQS delay relative to DQ read access */
-	.p0_mprddlctl   = 0x3C2E3238,
-	.p1_mprddlctl   = 0x3A2E303C,
-	/* Write Calibration: DQ/DM delay relative to DQS write access */
-	.p0_mpwrdlctl   = 0x36384036,
-	.p1_mpwrdlctl   = 0x442E4438,
-};
-
-static void ot1200_spl_dram_init(void)
-{
-	mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
-	mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
-		     &micron_2gib_1600);
-}
-
-/*
- * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
- * - we have a stack and a place to store GD, both in SRAM
- * - no variable global data is available
- */
-void board_init_f(ulong dummy)
-{
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	/* iomux and setup of i2c */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* configure MMDC for SDRAM width/size and per-model calibration */
-	ot1200_spl_dram_init();
-}
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
deleted file mode 100644
index 4f8a524c1dc0..000000000000
--- a/configs/ot1200_defconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MX6Q=y
-CONFIG_TARGET_OT1200=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DWC_AHSATA=y
-CONFIG_CMD_PCA953X=y
-CONFIG_FSL_USDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SMSC=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
deleted file mode 100644
index ec3bf9030694..000000000000
--- a/configs/ot1200_spl_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
-CONFIG_MX6Q=y
-CONFIG_TARGET_OT1200=y
-CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DWC_AHSATA=y
-CONFIG_CMD_PCA953X=y
-CONFIG_FSL_USDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=2
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SMSC=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
deleted file mode 100644
index ea61f92bdbbc..000000000000
--- a/include/configs/ot1200.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2014 Bachmann electronic GmbH
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
-
-/* UART Configs */
-#define CONFIG_MXC_UART_BASE           UART1_BASE
-
-/* SF Configs */
-
-/* IO expander */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
-#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED            100000
-
-/* OCOTP Configs */
-#define CONFIG_IMX_OTP
-#define IMX_OTP_BASE                    OCOTP_BASE_ADDR
-#define IMX_OTP_ADDR_MAX                0x7F
-#define IMX_OTP_DATA_ERROR_VAL          0xBADABADA
-#define IMX_OTPWRITE_ENABLED
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_SYS_FSL_USDHC_NUM       2
-
-/* USB Configs */
-#define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE	1
-#define CONFIG_DWC_AHSATA_PORT_ID	0
-#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* SPL */
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE                    ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE             MII100
-#define CONFIG_ETHPRIME                 "FEC"
-#define CONFIG_FEC_MXC_PHYADDR          0x5
-
-#ifndef CONFIG_SPL
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_BUS             1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#endif
-
-/* Physical Memory Map */
-#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment organization */
-/* M25P16 has an erase size of 64 KiB */
-
-#define CONFIG_BOOTP_SERVERIP
-#define CONFIG_BOOTP_BOOTFILE
-
-#endif         /* __CONFIG_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 07/16] arm: Remove ot1200 board
  2021-02-10  2:42 ` [PATCH 07/16] arm: Remove ot1200 board Tom Rini
@ 2021-02-17  9:58   ` Christian Gmeiner
  2021-03-01 14:47     ` Christian Gmeiner
  2021-04-12  0:25   ` Tom Rini
  1 sibling, 1 reply; 38+ messages in thread
From: Christian Gmeiner @ 2021-02-17  9:58 UTC (permalink / raw)
  To: u-boot

Hi Tom

Am Mi., 10. Feb. 2021 um 03:43 Uhr schrieb Tom Rini <trini@konsulko.com>:
>
> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  In order to
> convert to using the DWC SATA driver under DM further migrations are
> required.
>

I will drive tomorrow to the office to get my hands on the device
again. On Monday I will
ack this patch or will post some patches to keep the board.

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 07/16] arm: Remove ot1200 board
  2021-02-17  9:58   ` Christian Gmeiner
@ 2021-03-01 14:47     ` Christian Gmeiner
  0 siblings, 0 replies; 38+ messages in thread
From: Christian Gmeiner @ 2021-03-01 14:47 UTC (permalink / raw)
  To: u-boot

Am Mi., 17. Feb. 2021 um 10:58 Uhr schrieb Christian Gmeiner
<christian.gmeiner@gmail.com>:
>
> Hi Tom
>
> Am Mi., 10. Feb. 2021 um 03:43 Uhr schrieb Tom Rini <trini@konsulko.com>:
> >
> > This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> > deadline for this conversion was the v2019.07 release.  In order to
> > convert to using the DWC SATA driver under DM further migrations are
> > required.
> >
>
> I will drive tomorrow to the office to get my hands on the device
> again. On Monday I will
> ack this patch or will post some patches to keep the board.
>

At the moment there is no time planned for anyone to work on this.

Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 07/16] arm: Remove ot1200 board
  2021-02-10  2:42 ` [PATCH 07/16] arm: Remove ot1200 board Tom Rini
  2021-02-17  9:58   ` Christian Gmeiner
@ 2021-04-12  0:25   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-04-12  0:25 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:48PM -0500, Tom Rini wrote:

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  In order to
> convert to using the DWC SATA driver under DM further migrations are
> required.
> 
> Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 08/16] arm: Remove mx53loco board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (5 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 07/16] arm: Remove ot1200 board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-13 14:14   ` Fabio Estevam
  2021-02-10  2:42 ` [PATCH 09/16] ppc: Remove MPC8349ITX board Tom Rini
                   ` (8 subsequent siblings)
  15 siblings, 1 reply; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Jason Liu <jason.hui.liu@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/mach-imx/mx5/Kconfig                 |   6 -
 arch/arm/mach-imx/mx5/Makefile                |   1 -
 board/freescale/mx53loco/Kconfig              |  15 -
 board/freescale/mx53loco/MAINTAINERS          |   6 -
 board/freescale/mx53loco/Makefile             |   7 -
 board/freescale/mx53loco/mx53loco.c           | 367 ------------------
 board/freescale/mx53loco/mx53loco_video.c     | 114 ------
 .../mx53loco => k+p/kp_imx53}/imximage.cfg    |   0
 configs/kp_imx53_defconfig                    |   2 +-
 configs/mx53loco_defconfig                    |  43 --
 include/configs/mx53loco.h                    | 181 ---------
 11 files changed, 1 insertion(+), 741 deletions(-)
 delete mode 100644 board/freescale/mx53loco/Kconfig
 delete mode 100644 board/freescale/mx53loco/MAINTAINERS
 delete mode 100644 board/freescale/mx53loco/Makefile
 delete mode 100644 board/freescale/mx53loco/mx53loco.c
 delete mode 100644 board/freescale/mx53loco/mx53loco_video.c
 rename board/{freescale/mx53loco => k+p/kp_imx53}/imximage.cfg (100%)
 delete mode 100644 configs/mx53loco_defconfig
 delete mode 100644 include/configs/mx53loco.h

diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index bde37bb97e13..b2acf766134a 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -61,11 +61,6 @@ config TARGET_MX53EVK
 	select BOARD_LATE_INIT
 	select MX53
 
-config TARGET_MX53LOCO
-	bool "Support mx53loco"
-	select BOARD_LATE_INIT
-	select MX53
-
 config TARGET_MX53PPD
 	bool "Support mx53ppd"
 	select MX53
@@ -93,7 +88,6 @@ source "board/beckhoff/mx53cx9020/Kconfig"
 source "board/freescale/mx51evk/Kconfig"
 source "board/freescale/mx53ard/Kconfig"
 source "board/freescale/mx53evk/Kconfig"
-source "board/freescale/mx53loco/Kconfig"
 source "board/freescale/mx53smd/Kconfig"
 source "board/ge/mx53ppd/Kconfig"
 source "board/inversepath/usbarmory/Kconfig"
diff --git a/arch/arm/mach-imx/mx5/Makefile b/arch/arm/mach-imx/mx5/Makefile
index 40d1998637ca..9692f5568eef 100644
--- a/arch/arm/mach-imx/mx5/Makefile
+++ b/arch/arm/mach-imx/mx5/Makefile
@@ -10,4 +10,3 @@ obj-y += lowlevel_init.o
 
 # common files for mx53 dram initialization
 obj-$(CONFIG_TARGET_MX53CX9020) += mx53_dram.o
-obj-$(CONFIG_TARGET_MX53LOCO)   += mx53_dram.o
diff --git a/board/freescale/mx53loco/Kconfig b/board/freescale/mx53loco/Kconfig
deleted file mode 100644
index 5ca1672bf7a5..000000000000
--- a/board/freescale/mx53loco/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX53LOCO
-
-config SYS_BOARD
-	default "mx53loco"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_SOC
-	default "mx5"
-
-config SYS_CONFIG_NAME
-	default "mx53loco"
-
-endif
diff --git a/board/freescale/mx53loco/MAINTAINERS b/board/freescale/mx53loco/MAINTAINERS
deleted file mode 100644
index b4bd1a1842bd..000000000000
--- a/board/freescale/mx53loco/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX53LOCO BOARD
-M:	Jason Liu <jason.hui.liu@nxp.com>
-S:	Maintained
-F:	board/freescale/mx53loco/
-F:	include/configs/mx53loco.h
-F:	configs/mx53loco_defconfig
diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile
deleted file mode 100644
index d2ebd94dca1d..000000000000
--- a/board/freescale/mx53loco/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-# Jason Liu <r64343@freescale.com>
-
-obj-y			+= mx53loco.o
-obj-$(CONFIG_VIDEO)	+= mx53loco_video.o
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
deleted file mode 100644
index 1da263bb5d5f..000000000000
--- a/board/freescale/mx53loco/mx53loco.c
+++ /dev/null
@@ -1,367 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <asm/arch/clock.h>
-#include <env.h>
-#include <linux/errno.h>
-#include <asm/mach-imx/mx5_video.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <input.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <asm/gpio.h>
-#include <power/pmic.h>
-#include <dialog_pmic.h>
-#include <fsl_pmic.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-
-#define MX53LOCO_LCD_POWER		IMX_GPIO_NR(3, 24)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 get_board_rev(void)
-{
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[0];
-	struct fuse_bank0_regs *fuse =
-		(struct fuse_bank0_regs *)bank->fuse_regs;
-
-	int rev = readl(&fuse->gp[6]);
-
-	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
-		rev = 0;
-
-	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
-#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
-			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_uart(void)
-{
-	static const iomux_v3_cfg_t uart_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
-	/* request VBUS power enable pin, GPIO7_8 */
-	imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
-	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
-	return 0;
-}
-#endif
-
-static void setup_iomux_fec(void)
-{
-	static const iomux_v3_cfg_t fec_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
-			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
-	{MMC_SDHC1_BASE_ADDR},
-	{MMC_SDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret;
-
-	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
-	gpio_direction_input(IMX_GPIO_NR(3, 11));
-	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
-	gpio_direction_input(IMX_GPIO_NR(3, 13));
-
-	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
-		ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
-	else
-		ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
-
-	return ret;
-}
-
-#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
-				 PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
-				 PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(struct bd_info *bis)
-{
-	static const iomux_v3_cfg_t sd1_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
-		MX53_PAD_EIM_DA13__GPIO3_13,
-	};
-
-	static const iomux_v3_cfg_t sd2_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-				SD_CMD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
-		MX53_PAD_EIM_DA11__GPIO3_11,
-	};
-
-	u32 index;
-	int ret;
-
-	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
-	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(sd1_pads,
-							 ARRAY_SIZE(sd1_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(sd2_pads,
-							 ARRAY_SIZE(sd2_pads));
-			break;
-		default:
-			printf("Warning: you configured more ESDHC controller"
-				"(%d) as supported by the board(2)\n",
-				CONFIG_SYS_FSL_ESDHC_NUM);
-			return -EINVAL;
-		}
-		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
-#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c1_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
-}
-
-static int power_init(void)
-{
-	unsigned int val;
-	int ret;
-	struct pmic *p;
-
-	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
-		ret = pmic_dialog_init(I2C_PMIC);
-		if (ret)
-			return ret;
-
-		p = pmic_get("DIALOG_PMIC");
-		if (!p)
-			return -ENODEV;
-
-		env_set("fdt_file", "imx53-qsb.dtb");
-
-		/* Set VDDA to 1.25V */
-		val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
-		ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
-		if (ret) {
-			printf("Writing to BUCKCORE_REG failed: %d\n", ret);
-			return ret;
-		}
-
-		pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
-		val |= DA9052_SUPPLY_VBCOREGO;
-		ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
-		if (ret) {
-			printf("Writing to SUPPLY_REG failed: %d\n", ret);
-			return ret;
-		}
-
-		/* Set Vcc peripheral to 1.30V */
-		ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
-		if (ret) {
-			printf("Writing to BUCKPRO_REG failed: %d\n", ret);
-			return ret;
-		}
-
-		ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
-		if (ret) {
-			printf("Writing to SUPPLY_REG failed: %d\n", ret);
-			return ret;
-		}
-
-		return ret;
-	}
-
-	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
-		ret = pmic_init(I2C_0);
-		if (ret)
-			return ret;
-
-		p = pmic_get("FSL_PMIC");
-		if (!p)
-			return -ENODEV;
-
-		env_set("fdt_file", "imx53-qsrb.dtb");
-
-		/* Set VDDGP to 1.25V for 1GHz on SW1 */
-		pmic_reg_read(p, REG_SW_0, &val);
-		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
-		ret = pmic_reg_write(p, REG_SW_0, val);
-		if (ret) {
-			printf("Writing to REG_SW_0 failed: %d\n", ret);
-			return ret;
-		}
-
-		/* Set VCC as 1.30V on SW2 */
-		pmic_reg_read(p, REG_SW_1, &val);
-		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
-		ret = pmic_reg_write(p, REG_SW_1, val);
-		if (ret) {
-			printf("Writing to REG_SW_1 failed: %d\n", ret);
-			return ret;
-		}
-
-		/* Set global reset timer to 4s */
-		pmic_reg_read(p, REG_POWER_CTL2, &val);
-		val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
-		ret = pmic_reg_write(p, REG_POWER_CTL2, val);
-		if (ret) {
-			printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
-			return ret;
-		}
-
-		/* Set VUSBSEL and VUSBEN for USB PHY supply*/
-		pmic_reg_read(p, REG_MODE_0, &val);
-		val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
-		ret = pmic_reg_write(p, REG_MODE_0, val);
-		if (ret) {
-			printf("Writing to REG_MODE_0 failed: %d\n", ret);
-			return ret;
-		}
-
-		/* Set SWBST to 5V in auto mode */
-		val = SWBST_AUTO;
-		ret = pmic_reg_write(p, SWBST_CTRL, val);
-		if (ret) {
-			printf("Writing to SWBST_CTRL failed: %d\n", ret);
-			return ret;
-		}
-
-		return ret;
-	}
-
-	return -1;
-}
-
-static void clock_1GHz(void)
-{
-	int ret;
-	u32 ref_clk = MXC_HCLK;
-	/*
-	 * After increasing voltage to 1.25V, we can switch
-	 * CPU clock to 1GHz and DDR to 400MHz safely
-	 */
-	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
-	if (ret)
-		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
-
-	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
-	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
-	if (ret)
-		printf("CPU:   Switch DDR clock to 400MHz failed\n");
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-	setup_iomux_fec();
-	setup_iomux_lcd();
-
-	return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
-	return 1;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	mxc_set_sata_internal_clock();
-	setup_iomux_i2c();
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-	if (!power_init())
-		clock_1GHz();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: MX53 LOCO\n");
-
-	return 0;
-}
diff --git a/board/freescale/mx53loco/mx53loco_video.c b/board/freescale/mx53loco/mx53loco_video.c
deleted file mode 100644
index ff3fc8ce3e6f..000000000000
--- a/board/freescale/mx53loco/mx53loco_video.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <linux/list.h>
-#include <asm/gpio.h>
-#include <asm/arch/iomux-mx53.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-
-#define MX53LOCO_LCD_POWER		IMX_GPIO_NR(3, 24)
-
-static struct fb_videomode const claa_wvga = {
-	.name		= "CLAA07LC0ACW",
-	.refresh	= 57,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= 37037,
-	.left_margin	= 40,
-	.right_margin	= 60,
-	.upper_margin	= 10,
-	.lower_margin	= 10,
-	.hsync_len	= 20,
-	.vsync_len	= 10,
-	.sync		= 0,
-	.vmode		= FB_VMODE_NONINTERLACED
-};
-
-static struct fb_videomode const seiko_wvga = {
-	.name		= "Seiko-43WVF1G",
-	.refresh	= 60,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= 29851, /* picosecond (33.5 MHz) */
-	.left_margin	= 89,
-	.right_margin	= 164,
-	.upper_margin	= 23,
-	.lower_margin	= 10,
-	.hsync_len	= 10,
-	.vsync_len	= 10,
-	.sync		= 0,
-};
-
-void setup_iomux_lcd(void)
-{
-	static const iomux_v3_cfg_t lcd_pads[] = {
-		MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
-		MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
-		MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
-		MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
-		MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
-		MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
-		MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
-		MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
-		MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
-		MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
-		MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
-		MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
-		MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
-		MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
-		MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
-		MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
-		MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
-		MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
-		MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
-		MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
-		MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
-		MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
-		MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
-		MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
-		MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
-		MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
-		MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
-		MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-
-	/* Turn on GPIO backlight */
-	imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);
-	gpio_direction_output(MX53LOCO_LCD_POWER, 1);
-
-	/* Turn on display contrast */
-	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
-	gpio_direction_output(IMX_GPIO_NR(1, 1), 1);
-}
-
-int board_video_skip(void)
-{
-	int ret;
-	char const *e = env_get("panel");
-
-	if (e) {
-		if (strcmp(e, "seiko") == 0) {
-			ret = ipuv3_fb_init(&seiko_wvga, 0, IPU_PIX_FMT_RGB24);
-			if (ret)
-				printf("Seiko cannot be configured: %d\n", ret);
-			return ret;
-		}
-	}
-
-	/*
-	 * 'panel' env variable not found or has different value than 'seiko'
-	 *  Defaulting to claa lcd.
-	 */
-	ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
-	if (ret)
-		printf("CLAA cannot be configured: %d\n", ret);
-	return ret;
-}
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/k+p/kp_imx53/imximage.cfg
similarity index 100%
rename from board/freescale/mx53loco/imximage.cfg
rename to board/k+p/kp_imx53/imximage.cfg
diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index 717543805619..fd0405106b3c 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_OFFSET_REDUND=0x102000
 CONFIG_DEFAULT_DEVICE_TREE="imx53-kp"
 CONFIG_FIT=y
 CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/k+p/kp_imx53/imximage.cfg"
 CONFIG_SHOW_BOOT_PROGRESS=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR="."
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
deleted file mode 100644
index a1096a7f93f5..000000000000
--- a/configs/mx53loco_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX5=y
-CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_TARGET_MX53LOCO=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
-CONFIG_USE_PREBOOT=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_MX5=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_MCS7830=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_SPLASH_SCREEN=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
deleted file mode 100644
index a0dd33aecd3a..000000000000
--- a/include/configs/mx53loco.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * Configuration settings for Freescale MX53 low cost board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
-
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_MXC_UART_BASE	UART1_BASE
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	2
-
-/* Eth Configs */
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE	FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR	0x1F
-
-/* USB Configs */
-#define CONFIG_MXC_USB_PORT	1
-#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS	0
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_DIALOG_POWER
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
-
-/* Command definition */
-
-
-#define CONFIG_ETHPRIME		"FEC0"
-
-#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"script=boot.scr\0" \
-	"image=zImage\0" \
-	"fdt_addr=0x71000000\0" \
-	"boot_fdt=try\0" \
-	"ip_dyn=yes\0" \
-	"mmcdev=0\0" \
-	"mmcpart=1\0" \
-	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
-	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
-	"loadbootscript=" \
-		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0" \
-	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
-		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
-		"run netargs; " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
-				"else " \
-					"echo ERROR: Cannot load the DT; " \
-					"exit; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-	"mmc dev ${mmcdev}; if mmc rescan; then " \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loadimage; then " \
-				"run mmcboot; " \
-			"else run netboot; " \
-			"fi; " \
-		"fi; " \
-	"else run netboot; fi"
-
-#define CONFIG_ARP_TIMEOUT	200UL
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1			CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
-#define PHYS_SDRAM_2			CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
-#define PHYS_SDRAM_SIZE			(gd->ram_size)
-
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment starts at 768k = 768 * 1024 = 786432 */
-/*
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT		785408
-
-#ifdef CONFIG_CMD_SATA
-	#define CONFIG_SYS_SATA_MAX_DEVICE      1
-	#define CONFIG_DWC_AHSATA_PORT_ID       0
-	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
-	#define CONFIG_LBA48
-#endif
-
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO_LOGO
-
-#endif				/* __CONFIG_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 08/16] arm: Remove mx53loco board
  2021-02-10  2:42 ` [PATCH 08/16] arm: Remove mx53loco board Tom Rini
@ 2021-02-13 14:14   ` Fabio Estevam
  2021-02-13 16:14     ` Tom Rini
  2021-02-14  1:53     ` Fabio Estevam
  0 siblings, 2 replies; 38+ messages in thread
From: Fabio Estevam @ 2021-02-13 14:14 UTC (permalink / raw)
  To: u-boot

Hi Tom,

On Tue, Feb 9, 2021 at 11:44 PM Tom Rini <trini@konsulko.com> wrote:
>
> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.
>
> Cc: Jason Liu <jason.hui.liu@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>

I have patches converting this board to DM, but need to test on the
real hardware.

I will test them next week and if they work fine, I will submit the patches.

Please don't remove this board yet.

Thanks

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 08/16] arm: Remove mx53loco board
  2021-02-13 14:14   ` Fabio Estevam
@ 2021-02-13 16:14     ` Tom Rini
  2021-02-14  1:53     ` Fabio Estevam
  1 sibling, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-13 16:14 UTC (permalink / raw)
  To: u-boot

On Sat, Feb 13, 2021 at 11:14:53AM -0300, Fabio Estevam wrote:
> Hi Tom,
> 
> On Tue, Feb 9, 2021 at 11:44 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> > deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> > requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> > this board.
> >
> > Cc: Jason Liu <jason.hui.liu@nxp.com>
> > Signed-off-by: Tom Rini <trini@konsulko.com>
> 
> I have patches converting this board to DM, but need to test on the
> real hardware.
> 
> I will test them next week and if they work fine, I will submit the patches.
> 
> Please don't remove this board yet.

OK.  What might be helpful would be looking over configs/*mx[235]* and
running ./tools/rmboard.py and preemptively deleting everything I
haven't sent a patch for yet, that there's no longer interest in.
Thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 08/16] arm: Remove mx53loco board
  2021-02-13 14:14   ` Fabio Estevam
  2021-02-13 16:14     ` Tom Rini
@ 2021-02-14  1:53     ` Fabio Estevam
  1 sibling, 0 replies; 38+ messages in thread
From: Fabio Estevam @ 2021-02-14  1:53 UTC (permalink / raw)
  To: u-boot

Hi Tom,

On Sat, Feb 13, 2021 at 11:14 AM Fabio Estevam <festevam@gmail.com> wrote:

> I have patches converting this board to DM, but need to test on the
> real hardware.
>
> I will test them next week and if they work fine, I will submit the patches.

I managed to get access to an imx53-qsb and the conversion to DM worked well.

I have just submitted the series.

Regards,

Fabio Estevam

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 09/16] ppc: Remove MPC8349ITX board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (6 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 08/16] arm: Remove mx53loco board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-04-12  0:25   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 10/16] ppc: Remove MPC8544DS board Tom Rini
                   ` (7 subsequent siblings)
  15 siblings, 1 reply; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc83xx/Kconfig        |   6 -
 board/freescale/mpc8349itx/Kconfig      |  12 -
 board/freescale/mpc8349itx/MAINTAINERS  |   8 -
 board/freescale/mpc8349itx/Makefile     |   6 -
 board/freescale/mpc8349itx/README       | 186 ----------
 board/freescale/mpc8349itx/mpc8349itx.c | 401 ---------------------
 board/freescale/mpc8349itx/pci.c        | 104 ------
 configs/MPC8349ITXGP_defconfig          | 188 ----------
 configs/MPC8349ITX_LOWBOOT_defconfig    | 196 -----------
 configs/MPC8349ITX_defconfig            | 195 -----------
 include/configs/MPC8349ITX.h            | 441 ------------------------
 11 files changed, 1743 deletions(-)
 delete mode 100644 board/freescale/mpc8349itx/Kconfig
 delete mode 100644 board/freescale/mpc8349itx/MAINTAINERS
 delete mode 100644 board/freescale/mpc8349itx/Makefile
 delete mode 100644 board/freescale/mpc8349itx/README
 delete mode 100644 board/freescale/mpc8349itx/mpc8349itx.c
 delete mode 100644 board/freescale/mpc8349itx/pci.c
 delete mode 100644 configs/MPC8349ITXGP_defconfig
 delete mode 100644 configs/MPC8349ITX_LOWBOOT_defconfig
 delete mode 100644 configs/MPC8349ITX_defconfig
 delete mode 100644 include/configs/MPC8349ITX.h

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 2bae08e27863..f34acf7fa7f5 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -75,11 +75,6 @@ config TARGET_MPC8349EMDS_SDRAM
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_HAS_DDR2
 
-config TARGET_MPC8349ITX
-	bool "Support MPC8349ITX"
-	select ARCH_MPC8349
-	imply CMD_IRQ
-
 config TARGET_MPC837XEMDS
 	bool "Support MPC837XEMDS"
 	select ARCH_MPC837X
@@ -336,7 +331,6 @@ source "board/freescale/mpc8315erdb/Kconfig"
 source "board/freescale/mpc8323erdb/Kconfig"
 source "board/freescale/mpc832xemds/Kconfig"
 source "board/freescale/mpc8349emds/Kconfig"
-source "board/freescale/mpc8349itx/Kconfig"
 source "board/freescale/mpc837xemds/Kconfig"
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/ids/ids8313/Kconfig"
diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig
deleted file mode 100644
index ce3fffda7d82..000000000000
--- a/board/freescale/mpc8349itx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8349ITX
-
-config SYS_BOARD
-	default "mpc8349itx"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8349ITX"
-
-endif
diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS
deleted file mode 100644
index d0388ad6e55c..000000000000
--- a/board/freescale/mpc8349itx/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-MPC8349ITX BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc8349itx/
-F:	include/configs/MPC8349ITX.h
-F:	configs/MPC8349ITX_defconfig
-F:	configs/MPC8349ITX_LOWBOOT_defconfig
-F:	configs/MPC8349ITXGP_defconfig
diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile
deleted file mode 100644
index 803cba09ffb9..000000000000
--- a/board/freescale/mpc8349itx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-
-obj-y += mpc8349itx.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README
deleted file mode 100644
index 3012b837377d..000000000000
--- a/board/freescale/mpc8349itx/README
+++ /dev/null
@@ -1,186 +0,0 @@
-Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
----------------------------------------------------
-
-1.	Board Description
-
-	The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
-	the Freescale MPC8349E processor in a Mini-ITX form factor.
-
-	The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
-
-	A) One 8MB on-board flash EEPROM chip, instead of two.
-	B) No SATA controller
-	C) No Compact Flash slot
-	D) No Mini-PCI slot
-	E) No Vitesse 7385 5-port Ethernet switch
-	F) No 4-port USB Type-A interface
-
-2.	Board Switches and Jumpers
-
-2.0	Descriptions for all of the board jumpers can be found in the User
-	Guide.  Of particular interest to U-Boot developers is jumper J22:
-
-	Pos.	Name		Default		Description
-	-----------------------------------------------------------------------
-	A	LGPL0		ON (0)          HRCW source, bit 0
-	B       LGPL1           ON (0)          HRCW source, bit 1
-	C       LGPL3           ON (0)		HRCW source, bit 2
-	D       LGPL5           OFF (1)         PCI_SYNC_OUT frequency
-	E       BOOT1           ON (0)          Flash EEPROM boot device
-	F       PCI_M66EN       ON (0)          PCI 66MHz enable
-	G       I2C-WP          ON (0)          I2C EEPROM write protection
-	H       F_WP            OFF (1)         Flash EEPROM write protection
-
-	Jumper J22.E is only for the ITX, and it decides the configuration
-	of the flash chips.  If J22.E is ON (i.e. jumpered), then flash chip
-	U4 is located at address FE000000 and flash chip U7 is at FE800000.
-	If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
-
-	For U-Boot development, J22.E can be used to switch back-and-forth
-	between two U-Boot images.
-
-3.	Memory Map
-
-3.1.	The memory map should look pretty much like this:
-
-	0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
-	0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
-	0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
-	0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
-	0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
-	0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
-	0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
-	0xF001_0000 - 0xF001_FFFF Local bus expansion slot
-	0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
-	0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
-	0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
-
-3.2	Flash EEPROM layout.
-
-	On the ITX, jumper J22.E is used to determine which flash chips are
-	at which address.  When J22.E is switched, addresses from FE000000
-	to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
-
-	On the ITX, at the normal boot address (aka HIGHBOOT):
-
-	FE00_0000	HRCW
-	FE70_0000	Alternative U-Boot image
-	FE80_0000	Alternative HRCW
-	FEF0_0000	U-Boot image
-	FEFF_FFFF	End of flash
-
-	On the ITX, at the low boot address (LOWBOOT)
-
-	FE00_0000	HRCW and U-Boot image
-	FE04_0000	U-Boot environment variables
-	FE80_0000	Alternative HRCW and U-Boot image
-	FEFF_FFFF	End of flash
-
-	On the ITX-GP, the only option is LOWBOOT and there is only one chip
-
-	FE00_0000	HRCW and U-Boot image
-	FE04_0000	U-Boot environment variables
-	F7FF_FFFF	End of flash
-
-4. Definitions
-
-4.1 Explanation of NEW definitions in:
-
-	include/configs/MPC8349ITX.h
-
-	CONFIG_MPC83xx		MPC83xx family
-	CONFIG_MPC8349		MPC8349 specific
-	CONFIG_MPC8349ITX		MPC8349E-mITX
-
-5. Compilation
-
-	Assuming you're using BASH shell:
-
-		export CROSS_COMPILE=your-cross-compile-prefix
-		cd u-boot
-		make distclean
-
-		make MPC8349ITX_config
-	or:
-		make MPC8349ITXGP_config
-	or:
-		make MPC8349ITX_LOWBOOT_config
-
-		make
-
-6. Downloading and Flashing Images
-
-6.1 Download via tftp:
-
-	tftp $loadaddr <uboot>
-
-	where "<uboot>" is the path and filename, on the TFTP server, of
-	the U-Boot image.
-
-6.1 Reflash U-Boot Image using U-Boot
-
-	setenv uboot <uboot>
-	run tftpflash
-
-	where "<uboot>" is the path and filename, on the TFTP server, of
-	the U-Boot image.
-
-6.2 Using the HRCW to switch between two different U-Boot images on the ITX
-
-	Because the ITX has 16MB of flash, it is possible to keep two U-Boot
-	images in flash, and use the HRCW to specify which one is to be used
-	when the board boots.  This trick is especially effective with a
-	hardware debugger that can override the HRCW, such as the BDI-2000.
-
-	When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
-	at address FE000000.  When the BMS bit is 1, the ITX will boot the
-	image at address FEF00000.
-
-	Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
-	change the BMS bit whenever you want to boot the other image.
-
-	Step-by-step instructions:
-
-	1) Build an ITX image to be loaded at FEF00000
-
-		make distclean
-		make MPC8349ITX_config
-		make
-
-	2) Take the u-boot.bin image and flash it at FEF00000.
-
-		tftp $loadaddr u-boot.bin
-		protect off all
-		erase FEF00000 +$filesize
-		cp.b $loadaddr FEF00000 $filesize
-
-	3) Build an ITX image to be loaded at FE000000
-
-		make distclean
-		make MPC8349ITX_LOWBOOT_config
-		make
-
-	4) Take the u-boot.bin image and flash it at FE000000.
-
-		tftp $loadaddr u-boot.bin
-		protect off FE000000 +$filesize
-		erase FE000000 +$filesize
-		cp.b $loadaddr FE000000 $filesize
-
-	The HRCW in flash is currently set to boot the image at FE000000.
-
-	If you have a hardware debugger, configure it to set the HRCW to
-	B460A000 04040000 if you want to boot the image at FEF00000, or set
-	it to B060A000 04040000 if you want to boot the image at FE000000.
-
-	To change the HRCW in flash to boot the image at FEF00000, use these
-	U-Boot commands:
-
-		cp.b FE000000 1000 10000	; copy 1st flash sector to 1000
-		mw.b 1020 b4 8			; modify BMS bit
-		protect off FE000000 +10000
-		erase FE000000 +10000
-		cp.b 1000 FE000000 10000
-
-7. Notes
-	1) The console baudrate for MPC8349EITX is 115200bps.
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
deleted file mode 100644
index a265a8380fef..000000000000
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ /dev/null
@@ -1,401 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <log.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <vsc7385.h>
-#ifdef CONFIG_PCI
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#endif
-#include <spd_sdram.h>
-#include <asm/bitops.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <linux/delay.h>
-
-#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
-#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPD_EEPROM
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	/* The size of RAM, in bytes */
-	u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
-	u32 ddr_size_log2 = __ilog2(ddr_size);
-
-	im->sysconf.ddrlaw[0].ar =
-	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
-	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
-				CSBNDS_EA_SHIFT) & CSBNDS_EA);
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	/* Only one CS for DDR */
-	im->ddr.cs_config[1] = 0;
-	im->ddr.cs_config[2] = 0;
-	im->ddr.cs_config[3] = 0;
-
-	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
-	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
-
-	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
-	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
-
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
-	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
-	im->ddr.sdram_mode =
-	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
-	im->ddr.sdram_interval =
-	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
-						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-
-	udelay(200);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
-	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
-	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
-	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
-	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
-	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
-
-	return CONFIG_SYS_DDR_SIZE;
-}
-#endif
-
-#ifdef CONFIG_PCI
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
-	{
-	 PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 0x0f,
-	 PCI_ANY_ID,
-	 pci_cfgfunc_config_device,
-	 {
-	  PCI_ENET0_IOADDR,
-	  PCI_ENET0_MEMADDR,
-	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
-	 },
-	{}
-}
-#endif
-
-volatile static struct pci_controller hose[] = {
-	{
-#ifndef CONFIG_PCI_PNP
-	      config_table:pci_mpc83xxmitx_config_table,
-#endif
-	 },
-	{
-#ifndef CONFIG_PCI_PNP
-	      config_table:pci_mpc83xxmitx_config_table,
-#endif
-	 }
-};
-#endif				/* CONFIG_PCI */
-
-int dram_init(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-#ifdef CONFIG_DDR_ECC
-	volatile ddr83xx_t *ddr = &im->ddr;
-#endif
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -ENXIO;
-
-	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-#ifdef CONFIG_SPD_EEPROM
-	msize = spd_sdram();
-#else
-	msize = fixed_sdram();
-#endif
-
-#ifdef CONFIG_DDR_ECC
-	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
-		/* Unlike every other board, on the 83xx spd_sdram() returns
-		   megabytes instead of just bytes.  That's why we need to
-		   multiple by 1MB when calling ddr_enable_ecc(). */
-		ddr_enable_ecc(msize * 1048576);
-#endif
-
-	/* return total bus RAM size(bytes) */
-	gd->ram_size = msize * 1024 * 1024;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-#ifdef CONFIG_TARGET_MPC8349ITX
-	puts("Board: Freescale MPC8349E-mITX\n");
-#else
-	puts("Board: Freescale MPC8349E-mITX-GP\n");
-#endif
-
-	return 0;
-}
-
-/*
- * Implement a work-around for a hardware problem with compact
- * flash.
- *
- * Program the UPM if compact flash is enabled.
- */
-int misc_init_f(void)
-{
-#ifdef CONFIG_VSC7385_ENET
-	volatile u32 *vsc7385_cpuctrl;
-
-	/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
-	   default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
-	   means it is 0 when the IRQ is not active.  This makes the wire-AND
-	   logic always assert IRQ7 to CPU even if there is no request from the
-	   switch.  Since the compact flash and the switch share the same IRQ,
-	   the Linux kernel will think that the compact flash is requesting irq
-	   and get stuck when it tries to clear the IRQ.  Thus we need to set
-	   the L2_IRQ0 and L2_IRQ1 to active low.
-
-	   The following code sets the L1_IRQ and L2_IRQ polarity to active low.
-	   Without this code, compact flash will not work in Linux because
-	   unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
-	   don't enable compact flash for U-Boot.
-	 */
-
-	vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
-	*vsc7385_cpuctrl |= 0x0c;
-#endif
-
-#ifdef CONFIG_COMPACT_FLASH
-	/* UPM Table Configuration Code */
-	static uint UPMATable[] = {
-		0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
-		0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
-		0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
-	};
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
-	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-
-	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
-	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
-	 */
-	immap->im_lbc.mamr = 0x08404440;
-
-	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
-
-	puts("UPMA:  Configured for compact flash\n");
-#endif
-
-	return 0;
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * Make sure the EEPROM has the HRCW correctly programmed.
- * Make sure the RTC is correctly programmed.
- *
- * The MPC8349E-mITX can be configured to load the HRCW from
- * EEPROM instead of flash.  This is controlled via jumpers
- * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
- * jumpered), but if they're set to 001 or 010, then the HRCW is
- * read from the "I2C EEPROM".
- *
- * This function makes sure that the I2C EEPROM is programmed
- * correctly.
- *
- * If a VSC7385 microcode image is present, then upload it.
- */
-int misc_init_r(void)
-{
-	int rc = 0;
-
-#if defined(CONFIG_SYS_I2C)
-	unsigned int orig_bus = i2c_get_bus_num();
-	u8 i2c_data;
-
-#ifdef CONFIG_SYS_I2C_RTC_ADDR
-	u8 ds1339_data[17];
-#endif
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
-	static u8 eeprom_data[] =	/* HRCW data */
-	{
-		0xAA, 0x55, 0xAA,       /* Preamble */
-		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
-		0x02, 0x40,	        /* RCWL ADDR=0x0_0900 */
-		(CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
-		(CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
-		(CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
-		CONFIG_SYS_HRCW_LOW & 0xFF,
-		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
-		0x02, 0x41,	        /* RCWH ADDR=0x0_0904 */
-		(CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
-		(CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
-		(CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
-		CONFIG_SYS_HRCW_HIGH & 0xFF
-	};
-
-	u8 data[sizeof(eeprom_data)];
-#endif
-
-	printf("Board revision: ");
-	i2c_set_bus_num(1);
-	if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
-		printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
-	else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
-		printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
-	else {
-		printf("Unknown\n");
-		rc = 1;
-	}
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
-	i2c_set_bus_num(0);
-
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
-		if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
-			if (i2c_write
-			    (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
-			     sizeof(eeprom_data)) != 0) {
-				puts("Failure writing the HRCW to EEPROM via I2C.\n");
-				rc = 1;
-			}
-		}
-	} else {
-		puts("Failure reading the HRCW from EEPROM via I2C.\n");
-		rc = 1;
-	}
-#endif
-
-#ifdef CONFIG_SYS_I2C_RTC_ADDR
-	i2c_set_bus_num(1);
-
-	if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
-	    == 0) {
-
-		/* Work-around for MPC8349E-mITX bug #13601.
-		   If the RTC does not contain valid register values, the DS1339
-		   Linux driver will not work.
-		 */
-
-		/* Make sure status register bits 6-2 are zero */
-		ds1339_data[0x0f] &= ~0x7c;
-
-		/* Check for a valid day register value */
-		ds1339_data[0x03] &= ~0xf8;
-		if (ds1339_data[0x03] == 0) {
-			ds1339_data[0x03] = 1;
-		}
-
-		/* Check for a valid date register value */
-		ds1339_data[0x04] &= ~0xc0;
-		if ((ds1339_data[0x04] == 0) ||
-		    ((ds1339_data[0x04] & 0x0f) > 9) ||
-		    (ds1339_data[0x04] >= 0x32)) {
-			ds1339_data[0x04] = 1;
-		}
-
-		/* Check for a valid month register value */
-		ds1339_data[0x05] &= ~0x60;
-
-		if ((ds1339_data[0x05] == 0) ||
-		    ((ds1339_data[0x05] & 0x0f) > 9) ||
-		    ((ds1339_data[0x05] >= 0x13)
-		     && (ds1339_data[0x05] <= 0x19))) {
-			ds1339_data[0x05] = 1;
-		}
-
-		/* Enable Oscillator and rate select */
-		ds1339_data[0x0e] = 0x1c;
-
-		/* Work-around for MPC8349E-mITX bug #13330.
-		   Ensure that the RTC control register contains the value 0x1c.
-		   This affects SATA performance.
-		 */
-
-		if (i2c_write
-		    (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
-		     sizeof(ds1339_data))) {
-			puts("Failure writing to the RTC via I2C.\n");
-			rc = 1;
-		}
-	} else {
-		puts("Failure reading from the RTC via I2C.\n");
-		rc = 1;
-	}
-#endif
-
-	i2c_set_bus_num(orig_bus);
-#endif
-
-#ifdef CONFIG_VSC7385_IMAGE
-	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
-		CONFIG_VSC7385_IMAGE_SIZE)) {
-		puts("Failure uploading VSC7385 microcode.\n");
-		rc = 1;
-	}
-#endif
-
-	return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
deleted file mode 100644
index a09b6586882f..000000000000
--- a/board/freescale/mpc8349itx/pci.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <linux/delay.h>
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-
-static struct pci_region pci1_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
-		size: CONFIG_SYS_PCI2_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_IO_BASE,
-		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
-		size: CONFIG_SYS_PCI2_IO_SIZE,
-		flags: PCI_REGION_IO
-	},
-	{
-		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
-		size: CONFIG_SYS_PCI2_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-};
-#endif
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-	u8 reg8;
-
-#if defined(CONFIG_SYS_I2C)
-	i2c_set_bus_num(1);
-	/* Read the PCI_M66EN jumper setting */
-	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
-	    (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
-		if (reg8 & I2C_8574_PCI66)
-			clk->occr = 0xff000000;	/* 66 MHz PCI */
-		else
-			clk->occr = 0xff600001;	/* 33 MHz PCI */
-	} else {
-		clk->occr = 0xff600001;	/* 33 MHz PCI */
-	}
-#else
-	clk->occr = 0xff000000;	/* 66 MHz PCI */
-#endif
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
deleted file mode 100644
index 28e4ebf06f5b..000000000000
--- a/configs/MPC8349ITXGP_defconfig
+++ /dev/null
@@ -1,188 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666666
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8349ITX=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="PCI2_MEM"
-CONFIG_BAT3_BASE=0xA0000000
-CONFIG_BAT3_LENGTH_256_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="PCI2_MMIO"
-CONFIG_BAT4_BASE=0xB0000000
-CONFIG_BAT4_LENGTH_256_MBYTES=y
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_ICACHE_INHIBITED=y
-CONFIG_BAT4_ICACHE_GUARDED=y
-CONFIG_BAT4_DCACHE_INHIBITED=y
-CONFIG_BAT4_DCACHE_GUARDED=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_16_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="VSC7385"
-CONFIG_LBLAW1_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF0000000
-CONFIG_LBLAW3_NAME="CF"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="VSC7385"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_AM_128_KBYTES=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="LED"
-CONFIG_BR2_OR2_BASE=0xF9000000
-CONFIG_OR2_AM_2_MBYTES=y
-CONFIG_OR2_SCY_9=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CF"
-CONFIG_BR3_OR3_BASE=0xF0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_BR3_MACHINE_UPMA=y
-CONFIG_OR3_BI_BURSTINHIBIT=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSEC1EP_3=y
-CONFIG_SPCR_TSEC2EP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
-CONFIG_BOOTDELAY=6
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
deleted file mode 100644
index 46f7afc071fd..000000000000
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ /dev/null
@@ -1,196 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666666
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8349ITX=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="PCI2_MEM"
-CONFIG_BAT3_BASE=0xA0000000
-CONFIG_BAT3_LENGTH_256_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="PCI2_MMIO"
-CONFIG_BAT4_BASE=0xB0000000
-CONFIG_BAT4_LENGTH_256_MBYTES=y
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_ICACHE_INHIBITED=y
-CONFIG_BAT4_ICACHE_GUARDED=y
-CONFIG_BAT4_DCACHE_INHIBITED=y
-CONFIG_BAT4_DCACHE_GUARDED=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_16_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="VSC7385"
-CONFIG_LBLAW1_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF0000000
-CONFIG_LBLAW3_NAME="CF"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="VSC7385"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_AM_128_KBYTES=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="LED"
-CONFIG_BR2_OR2_BASE=0xF9000000
-CONFIG_OR2_AM_2_MBYTES=y
-CONFIG_OR2_SCY_9=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CF"
-CONFIG_BR3_OR3_BASE=0xF0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_BR3_MACHINE_UPMA=y
-CONFIG_OR3_BI_BURSTINHIBIT=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSEC1EP_3=y
-CONFIG_SPCR_TSEC2EP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="MPC8349E-mITX> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_SATA_SIL3114=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
deleted file mode 100644
index 1f70b756b0c6..000000000000
--- a/configs/MPC8349ITX_defconfig
+++ /dev/null
@@ -1,195 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFEF00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666666
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8349ITX=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="PCI2_MEM"
-CONFIG_BAT3_BASE=0xA0000000
-CONFIG_BAT3_LENGTH_256_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="PCI2_MMIO"
-CONFIG_BAT4_BASE=0xB0000000
-CONFIG_BAT4_LENGTH_256_MBYTES=y
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_ICACHE_INHIBITED=y
-CONFIG_BAT4_ICACHE_GUARDED=y
-CONFIG_BAT4_DCACHE_INHIBITED=y
-CONFIG_BAT4_DCACHE_GUARDED=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_16_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="VSC7385"
-CONFIG_LBLAW1_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF0000000
-CONFIG_LBLAW3_NAME="CF"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="VSC7385"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_AM_128_KBYTES=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="LED"
-CONFIG_BR2_OR2_BASE=0xF9000000
-CONFIG_OR2_AM_2_MBYTES=y
-CONFIG_OR2_SCY_9=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CF"
-CONFIG_BR3_OR3_BASE=0xF0000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_BR3_MACHINE_UPMA=y
-CONFIG_OR3_BI_BURSTINHIBIT=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSEC1EP_3=y
-CONFIG_SPCR_TSEC2EP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="MPC8349E-mITX> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFEF80000
-CONFIG_SATA_SIL3114=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
deleted file mode 100644
index f50cdd717cbe..000000000000
--- a/include/configs/MPC8349ITX.h
+++ /dev/null
@@ -1,441 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- */
-
-/*
- MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
-
- Memory map:
-
- 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
- 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
- 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
- 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
- 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
- 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
- 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
- 0xF001_0000-0xF001_FFFF Local bus expansion slot
- 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
- 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
- 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
-
- I2C address list:
-						Align.	Board
- Bus	Addr	Part No.	Description	Length	Location
- ----------------------------------------------------------------
- I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64
-
- I2C1	0x20	PCF8574		I2C Expander	0	U8
- I2C1	0x21	PCF8574		I2C Expander	0	U10
- I2C1	0x38	PCF8574A	I2C Expander	0	U8
- I2C1	0x39	PCF8574A	I2C Expander	0	U10
- I2C1	0x51	(DDR)		DDR EEPROM	1	U1
- I2C1	0x68	DS1339		RTC		1	U68
-
- Note that a given board has *either* a pair of 8574s or a pair of 8574As.
-*/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MISC_INIT_F
-
-/*
- * On-board devices
- */
-
-#ifdef CONFIG_TARGET_MPC8349ITX
-/* The CF card interface on the back of the board */
-#define CONFIG_COMPACT_FLASH
-#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
-#define CONFIG_SYS_USB_HOST	/* use the EHCI USB controller */
-#endif
-
-#include <linux/stringify.h>
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C
-
-/*
- * Device configurations
- */
-
-/* I2C */
-#ifdef CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-
-#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
-#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */
-
-#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
-#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
-#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
-#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* I2C1, DS1339 RTC*/
-#define SPD_EEPROM_ADDRESS		0x51	/* I2C1, DDR */
-
-/* Don't probe these addresses: */
-#define CONFIG_SYS_I2C_NOPROBES	{ {1, CONFIG_SYS_I2C_8574_ADDR1}, \
-				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
-				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
-				 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
-/* Bit definitions for the 8574[A] I2C expander */
-				/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
-#define I2C_8574_REVISION	0x03
-#define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
-#define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
-#define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
-#define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/
-
-#endif
-
-/* Compact Flash */
-#ifdef CONFIG_COMPACT_FLASH
-
-#define CONFIG_SYS_IDE_MAXBUS		1
-#define CONFIG_SYS_IDE_MAXDEVICE	1
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
-#define CONFIG_SYS_ATA_REG_OFFSET	0
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
-#define CONFIG_SYS_ATA_STRIDE		2
-
-/* If a CF card is not inserted, time out quickly */
-#define ATA_RESET_TIME	1
-
-#endif
-
-/*
- * SATA
- */
-#ifdef CONFIG_SATA_SIL3114
-
-#define CONFIG_SYS_SATA_MAX_DEVICE      4
-#define CONFIG_LBA48
-
-#endif
-
-#ifdef CONFIG_SYS_USB_HOST
-/*
- * Support USB
- */
-#define CONFIG_USB_EHCI_FSL
-
-/* Current USB implementation supports the only USB controller,
- * so we have to choose between the MPH or the DR ones */
-#if 1
-#define CONFIG_HAS_FSL_MPH_USB
-#else
-#define CONFIG_HAS_FSL_DR_USB
-#endif
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
-					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
-
-#ifdef CONFIG_SYS_I2C
-#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
-#endif
-
-/* No SPD? Then manually set up DDR parameters */
-#ifndef CONFIG_SPD_EEPROM
-    #define CONFIG_SYS_DDR_SIZE		256	/* Mb */
-    #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-					| CSCONFIG_ROW_BIT_13 \
-					| CSCONFIG_COL_BIT_10)
-
-    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
-    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
-#endif
-
-/*
- *Flash on the Local Bus
- */
-
-#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-/* 127 64KB sectors + 8 8KB sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT	135
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-
-/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
-boards, we say we have two, but don't display a message if we find only one. */
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	\
-		{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
-#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size in MB */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC2
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE		0xFEFFE000
-#define CONFIG_VSC7385_IMAGE_SIZE	8192
-
-#endif
-
-/*
- * BRx, ORx, LBLAWBARx, and LBLAWARx
- */
-
-
-/* Vitesse 7385 */
-
-#define CONFIG_SYS_VSC7385_BASE	0xF8000000
-
-#define CONFIG_SYS_LED_BASE	0xF9000000
-
-
-/* Compact Flash */
-
-#ifdef CONFIG_COMPACT_FLASH
-
-#define CONFIG_SYS_CF_BASE	0xF0000000
-
-
-#endif
-
-/*
- * U-Boot memory configuration
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONSOLE			ttyS0
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_MPC83XX_PCI2
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE	\
-			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE		0x01000000	/* 16M */
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE	\
-			(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE	\
-			(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS		\
-			(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE		0x01000000	/* 16M */
-#endif
-
-#ifndef CONFIG_PCI_PNP
-    #define PCI_ENET0_IOADDR	0x00000000
-    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
-    #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif
-
-/* TSEC */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_TSEC1
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME  "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
-#define TSEC1_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME  "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET	0x25000
-
-#define TSEC2_PHY_ADDR		4
-#define TSEC2_PHYIDX		0
-#define TSEC2_FLAGS		TSEC_GIGABIT
-#endif
-
-#define CONFIG_ETHPRIME		"Freescale TSEC"
-
-#endif
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Watchdog */
-#undef CONFIG_WATCHDOG		/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-				/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-/*
- * System performance
- */
-#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
-#define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */
-#define CONFIG_SYS_SCCR_USBDRCM	0	/* USB DR controller's clock */
-
-/*
- * System IO Config
- */
-/* Needed for gigabit to work on TSEC 1 */
-#define CONFIG_SYS_SICRH SICRH_TSOBI1
-				/* USB DR as device + USB MPH as host */
-#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1)
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_NETDEV		"eth0"
-
-/* Default path and filenames */
-#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
-#define CONFIG_BOOTFILE		"uImage"
-				/* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH	"u-boot.bin"
-
-#ifdef CONFIG_TARGET_MPC8349ITX
-#define CONFIG_FDTFILE		"mpc8349emitx.dtb"
-#else
-#define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
-#endif
-
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"console=" __stringify(CONSOLE) "\0"			\
-	"netdev=" CONFIG_NETDEV "\0"					\
-	"uboot=" CONFIG_UBOOTPATH "\0"					\
-	"tftpflash=tftpboot $loadaddr $uboot; "				\
-		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" +$filesize; "	\
-		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize; "	\
-		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize\0"	\
-	"fdtaddr=780000\0"						\
-	"fdtfile=" CONFIG_FDTFILE "\0"
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
-	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
-	" console=$console,$baudrate $othbootargs; "			\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw"				\
-	" console=$console,$baudrate $othbootargs; "			\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 09/16] ppc: Remove MPC8349ITX board
  2021-02-10  2:42 ` [PATCH 09/16] ppc: Remove MPC8349ITX board Tom Rini
@ 2021-04-12  0:25   ` Tom Rini
  0 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-04-12  0:25 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:50PM -0500, Tom Rini wrote:

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.
> 
> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 10/16] ppc: Remove MPC8544DS board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (7 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 09/16] ppc: Remove MPC8349ITX board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-11 10:34   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 11/16] ppc: Remove MPC8572DS board Tom Rini
                   ` (6 subsequent siblings)
  15 siblings, 2 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc85xx/Kconfig      |   6 -
 board/freescale/mpc8544ds/Kconfig     |  12 -
 board/freescale/mpc8544ds/MAINTAINERS |   6 -
 board/freescale/mpc8544ds/Makefile    |  10 -
 board/freescale/mpc8544ds/README      | 122 --------
 board/freescale/mpc8544ds/ddr.c       |  56 ----
 board/freescale/mpc8544ds/law.c       |  17 --
 board/freescale/mpc8544ds/mpc8544ds.c | 321 --------------------
 board/freescale/mpc8544ds/tlb.c       |  74 -----
 configs/MPC8544DS_defconfig           |  52 ----
 include/configs/MPC8544DS.h           | 408 --------------------------
 11 files changed, 1084 deletions(-)
 delete mode 100644 board/freescale/mpc8544ds/Kconfig
 delete mode 100644 board/freescale/mpc8544ds/MAINTAINERS
 delete mode 100644 board/freescale/mpc8544ds/Makefile
 delete mode 100644 board/freescale/mpc8544ds/README
 delete mode 100644 board/freescale/mpc8544ds/ddr.c
 delete mode 100644 board/freescale/mpc8544ds/law.c
 delete mode 100644 board/freescale/mpc8544ds/mpc8544ds.c
 delete mode 100644 board/freescale/mpc8544ds/tlb.c
 delete mode 100644 configs/MPC8544DS_defconfig
 delete mode 100644 include/configs/MPC8544DS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index c1a377067106..28c9f113d3f5 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -52,11 +52,6 @@ config TARGET_MPC8541CDS
 	bool "Support MPC8541CDS"
 	select ARCH_MPC8541
 
-config TARGET_MPC8544DS
-	bool "Support MPC8544DS"
-	select ARCH_MPC8544
-	imply PANIC_HANG
-
 config TARGET_MPC8548CDS
 	bool "Support MPC8548CDS"
 	select ARCH_MPC8548
@@ -1443,7 +1438,6 @@ config SYS_FSL_LBC_CLK_DIV
 
 source "board/freescale/corenet_ds/Kconfig"
 source "board/freescale/mpc8541cds/Kconfig"
-source "board/freescale/mpc8544ds/Kconfig"
 source "board/freescale/mpc8548cds/Kconfig"
 source "board/freescale/mpc8555cds/Kconfig"
 source "board/freescale/mpc8568mds/Kconfig"
diff --git a/board/freescale/mpc8544ds/Kconfig b/board/freescale/mpc8544ds/Kconfig
deleted file mode 100644
index c3e25b89a028..000000000000
--- a/board/freescale/mpc8544ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8544DS
-
-config SYS_BOARD
-	default "mpc8544ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8544DS"
-
-endif
diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS
deleted file mode 100644
index 74e7249e4734..000000000000
--- a/board/freescale/mpc8544ds/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8544DS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8544ds/
-F:	include/configs/MPC8544DS.h
-F:	configs/MPC8544DS_defconfig
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile
deleted file mode 100644
index 1693ae84330e..000000000000
--- a/board/freescale/mpc8544ds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y	+= mpc8544ds.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8544ds/README b/board/freescale/mpc8544ds/README
deleted file mode 100644
index b49c3c07c405..000000000000
--- a/board/freescale/mpc8544ds/README
+++ /dev/null
@@ -1,122 +0,0 @@
-Overview
---------
-The MPC8544DS system is similar to the 85xx CDS systems such
-as the MPC8548CDS due to the similar E500 core.  However, it
-is placed on the same board as the 8641 HPCN system.
-
-
-Flash Banks
------------
-Like the 85xx CDS systems, the 8544 DS board has two flash banks.
-They are both present on boot, but there locations can be swapped
-using the dip-switch SW10, bit 2.
-
-However, unlike the CDS systems, but similar to the 8641 HPCN
-board, a runtime reset through the FPGA can also affect a swap
-on the flash bank mappings for the next reset cycle.
-
-Irrespective of the switch SW10[2], booting is always from the
-boot bank at 0xfff8_0000.
-
-
-Memory Map
-----------
-
-0xff80_0000 - 0xffbf_ffff	Alternate bank		4MB
-0xffc0_0000 - 0xffff_ffff	Boot bank		4MB
-
-0xffb8_0000			Alternate image start	512KB
-0xfff8_0000			Boot image start	512KB
-
-
-Flashing Images
----------------
-
-For example, to place a new image in the alternate flash bank
-and then reset with that new image temporarily, use this:
-
-    tftp 1000000 u-boot.bin.8544ds
-    erase ffb80000 ffbfffff
-    cp.b 1000000 ffb80000 80000
-    pixis_reset altbank
-
-
-To overwrite the image in the boot flash bank:
-
-    tftp 1000000 u-boot.bin.8544ds
-    protect off all
-    erase fff80000 ffffffff
-    cp.b 1000000 fff80000 80000
-
-Other example U-Boot image and flash manipulations examples
-can be found in the README.mpc85xxcds file as well.
-
-
-The pixis_reset command
------------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer.  When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
-	pixis_reset
-	pixis_reset altbank
-	pixis_reset altbank wd
-	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
-	/* reset to current bank, like "reset" command */
-	pixis_reset
-
-	/* reset board but use the to alternate flash bank */
-	pixis_reset altbank
-
-	/* reset board, use alternate flash bank with watchdog timer enabled*/
-	pixis_reset altbank wd
-
-	/* reset board to alternate bank with frequency changed.
-	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
-	 */
-	pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
-
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
-    dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
-
-Likely, that .dts file will come from here;
-
-    linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
-
-After placing the DTB file in your TFTP disk area,
-you can download that dtb file using a command like:
-
-    tftp 900000 mpc8544ds.dtb
-
-Burn it to flash if you want.
-
-
-Booting Linux
--------------
-
-Place a linux uImage in the TFTP disk area too.
-
-    tftp 1000000 uImage.8544
-    tftp 900000 mpc8544ds.dtb
-    bootm 1000000 - 900000
-
-Watch your ethact, netdev and bootargs U-Boot environment variables.
-You may want to do something like this too:
-
-    setenv ethact eTSEC3
-    setenv netdev eth1
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
deleted file mode 100644
index c4d985347b3f..000000000000
--- a/board/freescale/mpc8544ds/ddr.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twot_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
deleted file mode 100644
index 52cec7fbb598..000000000000
--- a/board/freescale/mpc8544ds/law.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
deleted file mode 100644
index 30ed7083657f..000000000000
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ /dev/null
@@ -1,321 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-
-#include "../common/sgmii_riser.h"
-
-int checkboard (void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-	u8 vboot;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	if ((uint)&gur->porpllsr != 0xe00e0000) {
-		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
-	}
-	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	vboot = in_8(pixis_base + PIXIS_VBOOT);
-	if (vboot & PIXIS_VBOOT_FMAP)
-		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
-	else
-		puts ("Promjet\n");
-
-	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
-	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
-	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
-	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
-void pci_init_board(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info;
-	u32 devdisr, pordevsr, io_sel;
-	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno = 0;
-
-	int pcie_ep, pcie_configured;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-	puts("\n");
-
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-		/* contains both PCIE3 MEM & IO space */
-		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
-				LAW_TRGT_IF_PCIE_3);
-		SET_STD_PCIE_INFO(pci_info, 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
-
-		/* outbound memory */
-		pci_set_region(&pcie3_hose.regions[0],
-			       CONFIG_SYS_PCIE3_MEM_BUS2,
-			       CONFIG_SYS_PCIE3_MEM_PHYS2,
-			       CONFIG_SYS_PCIE3_MEM_SIZE2,
-			       PCI_REGION_MEM);
-
-		pcie3_hose.region_count = 1;
-
-		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info.regs);
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pcie3_hose, first_free_busno);
-
-		/*
-		 * Activate ULI1575 legacy chip by performing a fake
-		 * memory access.  Needed to make ULI RTC work.
-		 */
-		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	SET_STD_PCIE_INFO(pci_info, 1);
-	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
-#else
-	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-	SET_STD_PCIE_INFO(pci_info, 2);
-	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
-#else
-	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCI1
-	pci_speed = 66666000;
-	pci_32 = 1;
-	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
-			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
-			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info.regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-
-int last_stage_init(void)
-{
-	return 0;
-}
-
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
-	u8 i, go_bit, rd_clks;
-	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	go_bit = in_8(pixis_base + PIXIS_VCTL);
-	go_bit &= 0x01;
-
-	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
-	rd_clks &= 0x1C;
-
-	/*
-	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
-	 * should we be using the AUX register. Remember, we also set the
-	 * GO bit to boot from the alternate bank on the on-board flash
-	 */
-
-	if (go_bit) {
-		if (rd_clks == 0x1c)
-			i = in_8(pixis_base + PIXIS_AUX);
-		else
-			i = in_8(pixis_base + PIXIS_SPD);
-	} else {
-		i = in_8(pixis_base + PIXIS_SPD);
-	}
-
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33333333;
-		break;
-	case 1:
-		val = 40000000;
-		break;
-	case 2:
-		val = 50000000;
-		break;
-	case 3:
-		val = 66666666;
-		break;
-	case 4:
-		val = 83000000;
-		break;
-	case 5:
-		val = 100000000;
-		break;
-	case 6:
-		val = 133333333;
-		break;
-	case 7:
-		val = 166666666;
-		break;
-	}
-
-	return val;
-}
-
-
-#define MIIM_CIS8204_SLED_CON		0x1b
-#define MIIM_CIS8204_SLEDCON_INIT	0x1115
-/*
- * Hack to write all 4 PHYs with the LED values
- */
-int board_phy_config(struct phy_device *phydev)
-{
-	static int do_once;
-	uint phyid;
-	struct mii_dev *bus = phydev->bus;
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-	if (do_once)
-		return 0;
-
-	for (phyid = 0; phyid < 4; phyid++)
-		bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
-				MIIM_CIS8204_SLEDCON_INIT);
-
-	do_once = 1;
-
-	return 0;
-}
-
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	if (is_serdes_configured(SGMII_TSEC1)) {
-		puts("eTSEC1 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	if (is_serdes_configured(SGMII_TSEC3)) {
-		puts("eTSEC3 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-
-		return 0;
-	}
-
-	if (is_serdes_configured(SGMII_TSEC1) ||
-	    is_serdes_configured(SGMII_TSEC3)) {
-		fsl_sgmii_riser_init(tsec_info, num);
-	}
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
deleted file mode 100644
index 7bd462934aa5..000000000000
--- a/board/freescale/mpc8544ds/tlb.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	/*
-	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_64M, 1),
-	/*
-	 * TLB 1:	1G	Non-cacheable, guarded
-	 * 0x80000000	1G	PCIE  8,9,a,b
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1G, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe100_0000	255M	PCI IO range
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
deleted file mode 100644
index 82f14d812262..000000000000
--- a/configs/MPC8544DS_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8544DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF70000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_RTL8139=y
-CONFIG_TSEC_ENET=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
deleted file mode 100644
index f4f41da4988b..000000000000
--- a/include/configs/MPC8544DS.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8544ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PCI1		1	/* PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache */
-#define CONFIG_BTB			/* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS	1
-
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
- *
- * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
- *
- * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
- *
- * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
- * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
- *
- * Localbus cacheable
- *
- * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
- * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
- *
- * Localbus non-cacheable
- *
- * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
- * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
- * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
- *
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */
-
-#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */
-
-#define CONFIG_SYS_BR0_PRELIM		0xff801001
-#define CONFIG_SYS_BR1_PRELIM		0xfe801001
-
-#define CONFIG_SYS_OR0_PRELIM		0xff806e65
-#define CONFIG_SYS_OR1_PRELIM		0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000
-
-#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
-
-#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
-					 * register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
-#define PIXIS_VSPEED2_TSEC1SER	0x2
-#define PIXIS_VSPEED2_TSEC3SER	0x1
-#define PIXIS_VCFGEN1_TSEC1SER	0x20
-#define PIXIS_VCFGEN1_TSEC3SER	0x40
-#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
-#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK      1
-#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
-#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
-#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
-#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
-#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME		"ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
-	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
-	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* CONFIG_SCSI_AHCI */
-
-#endif	/* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER	1
-#define SGMII_RISER_PHY_OFFSET	0x1c
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC3_PHY_ADDR		1
-
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX		0
-#define TSEC3_PHYIDX		0
-
-#define CONFIG_ETHPRIME		"eTSEC1"
-#endif	/* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE			0
-#endif
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_IPADDR	192.168.1.251
-
-#define CONFIG_HOSTNAME	"8544ds_unknown"
-#define CONFIG_ROOTPATH	"/nfs/mpc85xx"
-#define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
-#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */
-
-#define CONFIG_SERVERIP	192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK	255.255.0.0
-
-#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"netdev=eth0\0"						\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-"tftpflash=tftpboot $loadaddr $uboot; "			\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"				\
-"ramdiskaddr=2000000\0"			\
-"ramdiskfile=8544ds/ramdisk.uboot\0"		\
-"fdtaddr=1e00000\0"				\
-"fdtfile=8544ds/mpc8544ds.dtb\0"		\
-"bdev=sda3\0"
-
-#define CONFIG_NFSBOOTCOMMAND		\
- "setenv bootargs root=/dev/nfs rw "	\
- "nfsroot=$serverip:$rootpath "		\
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND		\
- "setenv bootargs root=/dev/ram rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $ramdiskaddr $ramdiskfile;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		\
- "setenv bootargs root=/dev/$bdev rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#endif	/* __CONFIG_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 10/16] ppc: Remove MPC8544DS board
  2021-02-10  2:42 ` [PATCH 10/16] ppc: Remove MPC8544DS board Tom Rini
@ 2021-02-11 10:34   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Priyanka Jain @ 2021-02-11 10:34 UTC (permalink / raw)
  To: u-boot

>-----Original Message-----
>From: Tom Rini <trini@konsulko.com>
>Sent: Wednesday, February 10, 2021 8:13 AM
>To: u-boot at lists.denx.de
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Subject: [PATCH 10/16] ppc: Remove MPC8544DS board
>
>This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.
>The deadline for this conversion was the v2019.07 release.  The use of
>CONFIG_AHCI requires CONFIG_DM.  The deadline for this conversion was
>v2020.01.  Remove this board.
>
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Signed-off-by: Tom Rini <trini@konsulko.com>
>---
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 10/16] ppc: Remove MPC8544DS board
  2021-02-10  2:42 ` [PATCH 10/16] ppc: Remove MPC8544DS board Tom Rini
  2021-02-11 10:34   ` Priyanka Jain
@ 2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-15 15:44 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:51PM -0500, Tom Rini wrote:

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.
> 
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 11/16] ppc: Remove MPC8572DS board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (8 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 10/16] ppc: Remove MPC8544DS board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-11 10:34   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 12/16] ppc: Remove MPC8610HPCD board Tom Rini
                   ` (5 subsequent siblings)
  15 siblings, 2 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc85xx/Kconfig      |   9 -
 board/freescale/common/pixis.h        |  29 --
 board/freescale/mpc8572ds/Kconfig     |  12 -
 board/freescale/mpc8572ds/MAINTAINERS |   7 -
 board/freescale/mpc8572ds/Makefile    |  10 -
 board/freescale/mpc8572ds/README      | 166 -------
 board/freescale/mpc8572ds/ddr.c       | 166 -------
 board/freescale/mpc8572ds/law.c       |  19 -
 board/freescale/mpc8572ds/mpc8572ds.c | 260 -----------
 board/freescale/mpc8572ds/tlb.c       |  87 ----
 configs/MPC8572DS_36BIT_defconfig     |  56 ---
 configs/MPC8572DS_defconfig           |  54 ---
 include/configs/MPC8572DS.h           | 600 --------------------------
 13 files changed, 1475 deletions(-)
 delete mode 100644 board/freescale/mpc8572ds/Kconfig
 delete mode 100644 board/freescale/mpc8572ds/MAINTAINERS
 delete mode 100644 board/freescale/mpc8572ds/Makefile
 delete mode 100644 board/freescale/mpc8572ds/README
 delete mode 100644 board/freescale/mpc8572ds/ddr.c
 delete mode 100644 board/freescale/mpc8572ds/law.c
 delete mode 100644 board/freescale/mpc8572ds/mpc8572ds.c
 delete mode 100644 board/freescale/mpc8572ds/tlb.c
 delete mode 100644 configs/MPC8572DS_36BIT_defconfig
 delete mode 100644 configs/MPC8572DS_defconfig
 delete mode 100644 include/configs/MPC8572DS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 28c9f113d3f5..870ab800e86b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -68,14 +68,6 @@ config TARGET_MPC8569MDS
 	bool "Support MPC8569MDS"
 	select ARCH_MPC8569
 
-config TARGET_MPC8572DS
-	bool "Support MPC8572DS"
-	select ARCH_MPC8572
-# Use DDR3 controller with DDR2 DIMMs on this board
-	select SYS_FSL_DDRC_GEN3
-	imply SCSI
-	imply PANIC_HANG
-
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
 	select ARCH_P1010
@@ -1442,7 +1434,6 @@ source "board/freescale/mpc8548cds/Kconfig"
 source "board/freescale/mpc8555cds/Kconfig"
 source "board/freescale/mpc8568mds/Kconfig"
 source "board/freescale/mpc8569mds/Kconfig"
-source "board/freescale/mpc8572ds/Kconfig"
 source "board/freescale/p1010rdb/Kconfig"
 source "board/freescale/p1_p2_rdb_pc/Kconfig"
 source "board/freescale/p2041rdb/Kconfig"
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
index 40053c45bb75..f927f2c754da 100644
--- a/board/freescale/common/pixis.h
+++ b/board/freescale/common/pixis.h
@@ -72,35 +72,6 @@ typedef struct pixis {
 	u8 res2[34];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_TARGET_MPC8572DS)
-typedef struct pixis {
-	u8 id;
-	u8 ver;
-	u8 pver;
-	u8 csr;
-	u8 rst;
-	u8 pwr1;
-	u8 aux1;
-	u8 spd;
-	u8 aux2;
-	u8 res[7];
-	u8 vctl;
-	u8 vstat;
-	u8 vcfgen0;
-	u8 vcfgen1;
-	u8 vcore0;
-	u8 res1;
-	u8 vboot;
-	u8 vspeed[3];
-	u8 res2[2];
-	u8 sclk[3];
-	u8 dclk[3];
-	u8 res3[2];
-	u8 watch;
-	u8 led;
-	u8 res4[25];
-} __attribute__ ((packed)) pixis_t;
-
 #elif defined(CONFIG_TARGET_MPC8610HPCD)
 typedef struct pixis {
 	u8 id;
diff --git a/board/freescale/mpc8572ds/Kconfig b/board/freescale/mpc8572ds/Kconfig
deleted file mode 100644
index 38132cf3feba..000000000000
--- a/board/freescale/mpc8572ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8572DS
-
-config SYS_BOARD
-	default "mpc8572ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8572DS"
-
-endif
diff --git a/board/freescale/mpc8572ds/MAINTAINERS b/board/freescale/mpc8572ds/MAINTAINERS
deleted file mode 100644
index d7e9b1f41f41..000000000000
--- a/board/freescale/mpc8572ds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8572DS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8572ds/
-F:	include/configs/MPC8572DS.h
-F:	configs/MPC8572DS_defconfig
-F:	configs/MPC8572DS_36BIT_defconfig
diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile
deleted file mode 100644
index 5318e3be7280..000000000000
--- a/board/freescale/mpc8572ds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y	+= mpc8572ds.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8572ds/README b/board/freescale/mpc8572ds/README
deleted file mode 100644
index f1ffdd173087..000000000000
--- a/board/freescale/mpc8572ds/README
+++ /dev/null
@@ -1,166 +0,0 @@
-Overview
---------
-MPC8572DS is a high-performance computing, evaluation and development platform
-supporting the mpc8572 PowerTM processor.
-
-Building U-Boot
------------
-	make MPC8572DS_config
-	make
-
-Flash Banks
------------
-MPC8572DS board has two flash banks. They are both present on boot, but their
-locations can be swapped using the dip-switch SW9[1:2].
-
-Booting is always from the boot bank at 0xec00_0000.
-
-
-Memory Map
-----------
-
-0xe800_0000 - 0xebff_ffff	Alternate bank		64MB
-0xec00_0000 - 0xefff_ffff	Boot bank		64MB
-
-0xebf8_0000 - 0xebff_ffff	Alternate U-Boot address	512KB
-0xeff8_0000 - 0xefff_ffff	Boot U-Boot address		512KB
-
-
-Flashing Images
----------------
-
-To place a new U-Boot image in the alternate flash bank and then reset with that
- new image temporarily, use this:
-
-	tftp 1000000 u-boot.bin
-	erase ebf80000 ebffffff
-	cp.b 1000000 ebf80000 80000
-	pixis_reset altbank
-
-
-To program the image in the boot flash bank:
-
-	tftp 1000000 u-boot.bin
-	protect off all
-	erase eff80000 ffffffff
-	cp.b 1000000 eff80000 80000
-
-
-The pixis_reset command
------------------------
-The command - "pixis_reset", is introduced to reset mpc8572ds board
-using the FPGA sequencer.  When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
-	pixis_reset
-	pixis_reset altbank
-	pixis_reset altbank wd
-	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples:
-
-	/* reset to current bank, like "reset" command */
-	pixis_reset
-
-	/* reset board but use the to alternate flash bank */
-	pixis_reset altbank
-
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
-	dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
-
-Likely, that .dts file will come from here;
-
-	linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
-
-
-Booting Linux
--------------
-
-Place a linux uImage in the TFTP disk area.
-
-	tftp 1000000 uImage.8572
-	tftp c00000 mpc8572ds.dtb
-	bootm 1000000 - c00000
-
-
-Implementing AMP(Asymmetric MultiProcessing)
--------------
-1. Build kernel image for core0:
-
-	a. $ make 85xx/mpc8572_ds_defconfig
-
-	b. $ make menuconfig
-	   - un-select "Processor support"->"Symetric multi-processing support"
-
-	c. $ make uImage
-
-	d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
-
-2. Build kernel image for core1:
-
-	a. $ make 85xx/mpc8572_ds_defconfig
-
-	b. $ make menuconfig
-	   - Un-select "Processor support"->"Symetric multi-processing support"
-	   - Select "Advanced setup" -> " Prompt for advanced kernel
-	     configuration options"
-		- Select "Set physical address where the kernel is loaded" and
-		  set it to 0x20000000, assuming core1 will start from 512MB.
-		- Select "Set custom page offset address"
-		- Select "Set custom kernel base address"
-		- Select "Set maximum low memory"
-	   - "Exit" and save the selection.
-
-	c. $ make uImage
-
-	d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
-
-3. Create dtb for core0:
-
-	$ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
-
-4. Create dtb for core1:
-
-	$ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
-
-5. Bring up two cores separately:
-
-	a. Power on the board, under U-Boot prompt:
-		=> setenv <serverip>
-		=> setenv <ipaddr>
-		=> setenv bootargs root=/dev/ram rw console=ttyS0,115200
-	b. Bring up core1's kernel first:
-		=> setenv bootm_low 0x20000000
-		=> setenv bootm_size 0x10000000
-		=> tftp 21000000 8572/uImage.core1
-		=> tftp 22000000 8572/ramdiskfile
-		=> tftp 20c00000 8572/mpc8572ds_core1.dtb
-		=> interrupts off
-		=> bootm start 21000000 22000000 20c00000
-		=> bootm loados
-		=> bootm ramdisk
-		=> bootm fdt
-		=> fdt boardsetup
-		=> fdt chosen $initrd_start $initrd_end
-		=> bootm prep
-		=> cpu 1 release $bootm_low - $fdtaddr -
-	c. Bring up core0's kernel(on the same U-Boot console):
-		=> setenv bootm_low 0
-		=> setenv bootm_size 0x20000000
-		=> tftp 1000000 8572/uImage.core0
-		=> tftp 2000000 8572/ramdiskfile
-		=> tftp c00000 8572/mpc8572ds_core0.dtb
-		=> bootm 1000000 2000000 c00000
-
-Please note only core0 will run U-Boot, core1 starts kernel directly after
-"cpu release" command is issued.
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
deleted file mode 100644
index 11ca08d1a0b9..000000000000
--- a/board/freescale/mpc8572ds/ddr.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
- * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
- * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
- * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
- * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
- *
- * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{2,  333,    8,   7,    5,  0},
-	{2,  400,    8,   9,    5,  0},
-	{2,  549,    8,  11,    5,  0},
-	{2,  680,    8,  10,    5,  0},
-	{2,  850,    8,  12,    5,  1},
-	{1,  333,    6,   7,    3,  0},
-	{1,  400,    6,   9,    3,  0},
-	{1,  549,    6,  11,    3,  0},
-	{1,  680,    1,  10,    5,  0},
-	{1,  850,    1,  12,    5,  0},
-	{}
-};
-
-static const struct board_specific_parameters udimm1[] = {
-	/*
-	 * memory controller 1
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{2,  333,    8,  7,    5,  0},
-	{2,  400,    8,  9,    5,  0},
-	{2,  549,    8, 11,    5,  0},
-	{2,  680,    8, 11,    5,  0},
-	{2,  850,    8, 13,    5,  1},
-	{1,  333,    6,  7,    3,  0},
-	{1,  400,    6,  9,    3,  0},
-	{1,  549,    6, 11,    3,  0},
-	{1,  680,    1, 11,    6,  0},
-	{1,  850,    1, 13,    6,  0},
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-	udimm1,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{2,  333,    4,   7,    3,  0},
-	{2,  400,    4,   9,    3,  0},
-	{2,  549,    4,  11,    3,  0},
-	{2,  680,    4,  10,    3,  0},
-	{2,  850,    4,  12,    3,  1},
-	{}
-};
-
-static const struct board_specific_parameters rdimm1[] = {
-	/*
-	 * memory controller 1
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{2,  333,     4,  7,    3,  0},
-	{2,  400,     4,  9,    3,  0},
-	{2,  549,     4, 11,    3,  0},
-	{2,  680,     4, 11,    3,  0},
-	{2,  850,     4, 13,    3,  1},
-	{}
-};
-
-static const struct board_specific_parameters *rdimms[] = {
-	rdimm0,
-	rdimm1,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 1) {
-		printf("Wrong parameter for controller number %d", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	if (popts->registered_dimm_en)
-		pbsp = rdimms[ctrl_num];
-	else
-		pbsp = udimms[ctrl_num];
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->twot_en = pbsp->force_2t;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp->clk_adjust;
-		popts->cpo_override = pbsp->cpo;
-		popts->write_data_delay = pbsp->write_data_delay;
-		popts->twot_en = pbsp->force_2t;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
deleted file mode 100644
index 10d1572c5de6..000000000000
--- a/board/freescale/mpc8572ds/law.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
deleted file mode 100644
index 97e73533ab4b..000000000000
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ /dev/null
@@ -1,260 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <tsec.h>
-#include <fsl_mdio.h>
-#include <netdev.h>
-
-#include "../common/sgmii_riser.h"
-
-int checkboard (void)
-{
-	u8 vboot;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	printf("Board: MPC8572DS Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	vboot = in_8(pixis_base + PIXIS_VBOOT);
-	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
-		case PIXIS_VBOOT_LBMAP_NOR0:
-			puts ("vBank: 0\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_PJET:
-			puts ("Promjet\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NAND:
-			puts ("NAND\n");
-			break;
-		case PIXIS_VBOOT_LBMAP_NOR1:
-			puts ("vBank: 1\n");
-			break;
-	}
-
-	return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
-	uint d_init;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-
-#if defined (CONFIG_DDR_ECC)
-	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
-	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
-	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-#endif
-	asm("sync;isync");
-
-	udelay(500);
-
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	d_init = 1;
-	debug("DDR - 1st controller: memory initializing\n");
-	/*
-	 * Poll until memory is initialized.
-	 * 512 Meg at 400 might hit this 200 times or so.
-	 */
-	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
-		udelay(1000);
-	}
-	debug("DDR: memory initialized\n\n");
-	asm("sync; isync");
-	udelay(500);
-#endif
-
-	return 512 * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	struct pci_controller *hose;
-
-	fsl_pcie_init_board(0);
-
-	hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
-
-	if (hose) {
-		u32 temp32;
-		u8 uli_busno = hose->first_busno + 2;
-
-		/*
-		 * Activate ULI1575 legacy chip by performing a fake
-		 * memory access.  Needed to make ULI RTC work.
-		 * Device 1d has the first on-board memory BAR.
-		 */
-		pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
-				PCI_BASE_ADDRESS_1, &temp32);
-
-		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
-			void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
-					temp32, 4, 0);
-			debug(" uli1572 read to %p\n", p);
-			in_be32(p);
-		}
-	}
-}
-#endif
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2; /* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */
-
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[4];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	if (is_serdes_configured(SGMII_TSEC1)) {
-		puts("eTSEC1 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	if (is_serdes_configured(SGMII_TSEC2)) {
-		puts("eTSEC2 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	if (is_serdes_configured(SGMII_TSEC3)) {
-		puts("eTSEC3 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC4
-	SET_STD_TSEC_INFO(tsec_info[num], 4);
-	if (is_serdes_configured(SGMII_TSEC4)) {
-		puts("eTSEC4 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-
-		return 0;
-	}
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_init(tsec_info, num);
-#endif
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
deleted file mode 100644
index 99b136b04297..000000000000
--- a/board/freescale/mpc8572ds/tlb.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* W**G* - Flash/promjet, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_NAND_SPL
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-
-	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_1M, 1),
-
-	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
-	/* *I*G - L2SRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
-			CONFIG_SYS_INIT_L2_ADDR_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 9, BOOKE_PAGESZ_256K, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-			CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 10, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
deleted file mode 100644
index 44d90fbe0e94..000000000000
--- a/configs/MPC8572DS_36BIT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8572DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SCSI_AHCI=y
-CONFIG_SYS_FSL_DDR2=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
deleted file mode 100644
index b8fa7d4ff9a0..000000000000
--- a/configs/MPC8572DS_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8572DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SCSI_AHCI=y
-CONFIG_SYS_FSL_DDR2=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
deleted file mode 100644
index 731d4a5a4141..000000000000
--- a/include/configs/MPC8572DS.h
+++ /dev/null
@@ -1,600 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8572ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-
-#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk() /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache */
-#define CONFIG_BTB			/* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS	1
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS		0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS		CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE		(512 << 10)
-#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR		0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	2
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
-#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3		0x00020000
-#define CONFIG_SYS_DDR_TIMING_0		0x00260802
-#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
-#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
-#define CONFIG_SYS_DDR_MODE_1		0x00440462
-#define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
-#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2		0x24400000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
-#define CONFIG_SYS_DDR_SBE		0x00010000
-
-/*
- * Make sure required options are set
- */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
- * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
- * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
- * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
- * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
- * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
- * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
- * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
- * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
-	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
-
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_HWCONFIG			/* enable hwconfig */
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS	0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS	PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
-
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version@offset 2 */
-#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_PWR		0x5	/* PIXIS Power status register */
-#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VSTAT		0x11	/* VELA Status Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VBOOT_LBMAP	0xc0	/* VBOOT - CFG_LBMAP */
-#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
-#define PIXIS_VBOOT_LBMAP_PJET	0x01	/* cfg_lbmap - boot from projet */
-#define PIXIS_VBOOT_LBMAP_NAND	0x02	/* cfg_lbmap - boot from NAND */
-#define PIXIS_VBOOT_LBMAP_NOR1	0x03	/* cfg_lbmap - boot from NOR 1 */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
-#define PIXIS_VWATCH		0x24    /* Watchdog Register */
-#define PIXIS_LED		0x25    /* LED Register */
-
-#define PIXIS_SPD_SYSCLK_MASK		0x7		/* SYSCLK option */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
-#define PIXIS_VSPEED2_TSEC1SER	0x8
-#define PIXIS_VSPEED2_TSEC2SER	0x4
-#define PIXIS_VSPEED2_TSEC3SER	0x2
-#define PIXIS_VSPEED2_TSEC4SER	0x1
-#define PIXIS_VCFGEN1_TSEC1SER	0x20
-#define PIXIS_VCFGEN1_TSEC2SER	0x20
-#define PIXIS_VCFGEN1_TSEC3SER	0x20
-#define PIXIS_VCFGEN1_TSEC4SER	0x20
-#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
-					| PIXIS_VSPEED2_TSEC2SER \
-					| PIXIS_VSPEED2_TSEC3SER \
-					| PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
-					| PIXIS_VCFGEN1_TSEC2SER \
-					| PIXIS_VCFGEN1_TSEC3SER \
-					| PIXIS_VCFGEN1_TSEC4SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
-
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE		0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-#endif
-#else
-#define CONFIG_SYS_NAND_BASE		0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-#endif
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
-				CONFIG_SYS_NAND_BASE + 0x40000, \
-				CONFIG_SYS_NAND_BASE + 0x80000,\
-				CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE    4
-#define CONFIG_NAND_FSL_ELBC	1
-#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
-#define CONFIG_SYS_NAND_MAX_OOBFREE	5
-#define CONFIG_SYS_NAND_MAX_ECCPOS	56
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
-		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
-			       | OR_FCM_PGS	       /* Large Page*/ \
-			       | OR_FCM_CSCT \
-			       | OR_FCM_CST \
-			       | OR_FCM_CHT \
-			       | OR_FCM_SCY_1 \
-			       | OR_FCM_TRLX \
-			       | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
-			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-#define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM	1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_NAME		"ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
-	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
-	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* SCSI */
-
-#endif	/* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC2	1
-#define CONFIG_TSEC2_NAME	"eTSEC2"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-#define CONFIG_TSEC4	1
-#define CONFIG_TSEC4_NAME	"eTSEC4"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER	1
-#define SGMII_RISER_PHY_OFFSET	0x1c
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
-#endif
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC3_PHY_ADDR		2
-#define TSEC4_PHY_ADDR		3
-
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
-
-#define CONFIG_ETHPRIME		"eTSEC1"
-#endif	/* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE			0
-#endif
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR		192.168.1.254
-
-#define CONFIG_HOSTNAME		"unknown"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0"		\
-"netdev=eth0\0"						\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
-"tftpflash=tftpboot $loadaddr $uboot; "			\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"				\
-"ramdiskaddr=2000000\0"			\
-"ramdiskfile=8572ds/ramdisk.uboot\0"		\
-"fdtaddr=1e00000\0"				\
-"fdtfile=8572ds/mpc8572ds.dtb\0"		\
-"bdev=sda3\0"
-
-#define CONFIG_HDBOOT				\
- "setenv bootargs root=/dev/$bdev rw "		\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"			\
- "tftp $fdtaddr $fdtfile;"			\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND		\
- "setenv bootargs root=/dev/nfs rw "	\
- "nfsroot=$serverip:$rootpath "		\
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND		\
- "setenv bootargs root=/dev/ram rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $ramdiskaddr $ramdiskfile;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
-
-#endif	/* __CONFIG_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 11/16] ppc: Remove MPC8572DS board
  2021-02-10  2:42 ` [PATCH 11/16] ppc: Remove MPC8572DS board Tom Rini
@ 2021-02-11 10:34   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Priyanka Jain @ 2021-02-11 10:34 UTC (permalink / raw)
  To: u-boot



>-----Original Message-----
>From: Tom Rini <trini@konsulko.com>
>Sent: Wednesday, February 10, 2021 8:13 AM
>To: u-boot at lists.denx.de
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Subject: [PATCH 11/16] ppc: Remove MPC8572DS board
>
>This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.
>The deadline for this conversion was the v2019.07 release.  The use of
>CONFIG_AHCI requires CONFIG_DM.  The deadline for this conversion was
>v2020.01.  Remove this board.
>
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Signed-off-by: Tom Rini <trini@konsulko.com>
>---
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 11/16] ppc: Remove MPC8572DS board
  2021-02-10  2:42 ` [PATCH 11/16] ppc: Remove MPC8572DS board Tom Rini
  2021-02-11 10:34   ` Priyanka Jain
@ 2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-15 15:44 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:52PM -0500, Tom Rini wrote:

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.
> 
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 12/16] ppc: Remove MPC8610HPCD board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (9 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 11/16] ppc: Remove MPC8572DS board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-11 10:33   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 13/16] ppc: Remove MPC8641HPCN board Tom Rini
                   ` (4 subsequent siblings)
  15 siblings, 2 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc86xx/Kconfig              |   6 -
 board/freescale/common/pixis.h                |  30 -
 board/freescale/mpc8610hpcd/Kconfig           |  12 -
 board/freescale/mpc8610hpcd/MAINTAINERS       |   6 -
 board/freescale/mpc8610hpcd/Makefile          |   7 -
 board/freescale/mpc8610hpcd/README            |  73 ---
 board/freescale/mpc8610hpcd/ddr.c             |  56 --
 board/freescale/mpc8610hpcd/law.c             |  21 -
 board/freescale/mpc8610hpcd/mpc8610hpcd.c     | 335 -----------
 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c |  72 ---
 configs/MPC8610HPCD_defconfig                 |  37 --
 include/configs/MPC8610HPCD.h                 | 559 ------------------
 12 files changed, 1214 deletions(-)
 delete mode 100644 board/freescale/mpc8610hpcd/Kconfig
 delete mode 100644 board/freescale/mpc8610hpcd/MAINTAINERS
 delete mode 100644 board/freescale/mpc8610hpcd/Makefile
 delete mode 100644 board/freescale/mpc8610hpcd/README
 delete mode 100644 board/freescale/mpc8610hpcd/ddr.c
 delete mode 100644 board/freescale/mpc8610hpcd/law.c
 delete mode 100644 board/freescale/mpc8610hpcd/mpc8610hpcd.c
 delete mode 100644 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
 delete mode 100644 configs/MPC8610HPCD_defconfig
 delete mode 100644 include/configs/MPC8610HPCD.h

diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 0f253051f26d..294485794bdf 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -13,11 +13,6 @@ config TARGET_SBC8641D
 	select ARCH_MPC8641
 	select BOARD_EARLY_INIT_F
 
-config TARGET_MPC8610HPCD
-	bool "Support MPC8610HPCD"
-	select ARCH_MPC8610
-	select BOARD_EARLY_INIT_F
-
 config TARGET_MPC8641HPCN
 	bool "Support MPC8641HPCN"
 	select ARCH_MPC8641
@@ -62,7 +57,6 @@ config SYS_FSL_NUM_LAWS
 		Number of local access windows. This is fixed per SoC.
 		If not sure, do not change.
 
-source "board/freescale/mpc8610hpcd/Kconfig"
 source "board/freescale/mpc8641hpcn/Kconfig"
 source "board/sbc8641d/Kconfig"
 source "board/xes/xpedite517x/Kconfig"
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
index f927f2c754da..36c94862a55b 100644
--- a/board/freescale/common/pixis.h
+++ b/board/freescale/common/pixis.h
@@ -72,36 +72,6 @@ typedef struct pixis {
 	u8 res2[34];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_TARGET_MPC8610HPCD)
-typedef struct pixis {
-	u8 id;
-	u8 ver;	/* also called arch */
-	u8 pver;
-	u8 csr;
-	u8 rst;
-	u8 pwr;
-	u8 aux;
-	u8 spd;
-	u8 brdcfg0;
-	u8 brdcfg1;
-	u8 res[4];
-	u8 led;
-	u8 serno;
-	u8 vctl;
-	u8 vstat;
-	u8 vcfgen0;
-	u8 vcfgen1;
-	u8 vcore0;
-	u8 res1;
-	u8 vboot;
-	u8 vspeed[2];
-	u8 res2;
-	u8 sclk[3];
-	u8 res3;
-	u8 watch;
-	u8 res4[33];
-} __attribute__ ((packed)) pixis_t;
-
 #elif defined(CONFIG_TARGET_MPC8641HPCN)
 typedef struct pixis {
 	u8 id;
diff --git a/board/freescale/mpc8610hpcd/Kconfig b/board/freescale/mpc8610hpcd/Kconfig
deleted file mode 100644
index 8f713beaa842..000000000000
--- a/board/freescale/mpc8610hpcd/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8610HPCD
-
-config SYS_BOARD
-	default "mpc8610hpcd"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8610HPCD"
-
-endif
diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS
deleted file mode 100644
index 9b1e0cd4e56b..000000000000
--- a/board/freescale/mpc8610hpcd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8610HPCD BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8610hpcd/
-F:	include/configs/MPC8610HPCD.h
-F:	configs/MPC8610HPCD_defconfig
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
deleted file mode 100644
index 3a02a0641690..000000000000
--- a/board/freescale/mpc8610hpcd/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright 2007 Freescale Semiconductor, Inc.
-
-obj-y	+= mpc8610hpcd.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
-obj-y	+= law.o
-obj-$(CONFIG_FSL_DIU_FB)	+= mpc8610hpcd_diu.o
diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README
deleted file mode 100644
index 066e625d484d..000000000000
--- a/board/freescale/mpc8610hpcd/README
+++ /dev/null
@@ -1,73 +0,0 @@
-Freescale MPC8610HPCD board
-===========================
-
-
-Building U-Boot
----------------
-
-    $ make MPC8610HPCD_config
-    Configuring for MPC8610HPCD board...
-
-    $ make
-
-
-Flashing U-Boot
----------------
-The flash is 128M starting at 0xF800_0000.
-
-The alternate image is at 0xFBF0_0000
-The      boot image is at 0xFFF0_0000.
-
-
-To Flash U-Boot into the booting bank:
-
-	tftp 1000000 u-boot.bin
-	protect off all
-	erase fff00000 +$filesize
-	cp.b 1000000 fff00000 $filesize
-
-
-To Flash U-Boot into the alternate bank
-
-	tftp 1000000 u-boot.bin
-	erase fbf00000 +$filesize
-	cp.b 1000000 fbf00000 $filesize
-
-
-pixis_reset command
--------------------
-A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
-using the FPGA sequencer.  When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
-	pixis_reset
-	pixis_reset altbank
-	pixis_reset altbank wd
-	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
-	/* reset to current bank, like "reset" command */
-	pixis_reset
-
-	/* reset board but use the to alternate flash bank */
-	pixis_reset altbank
-
-	/* reset board, use alternate flash bank with watchdog timer enabled*/
-	pixis_reset altbank wd
-
-	/* reset board to alternate bank with frequency changed.
-	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
-	 */
-	pixis-reset altbank cf 40 2.5 10
-
-
-DIP Switch Settings
--------------------
-To manually switch the flash banks using the DIP switch
-settings, toggle both SW6:1 and SW6:2.
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
deleted file mode 100644
index c4d985347b3f..000000000000
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twot_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
deleted file mode 100644
index 7bf5e6815d7b..000000000000
--- a/board/freescale/mpc8610hpcd/law.c
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
-#endif
-	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
deleted file mode 100644
index 52bf4da98eaa..000000000000
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ /dev/null
@@ -1,335 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void sdram_init(void);
-phys_size_t fixed_sdram(void);
-int mpc8610hpcd_diu_init(void);
-
-
-/* called before any console output */
-int board_early_init_f(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-
-	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 tmp_val, version;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	/*Do not use 8259PIC*/
-	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
-	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
-
-	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
-	version = in_8(pixis_base + PIXIS_PVER);
-	if(version >= 0x07) {
-		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
-		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
-	}
-
-	/* Using this for DIU init before the driver in linux takes over
-	 *  Enable the TFP410 Encoder (I2C address 0x38)
-	 */
-
-	tmp_val = 0xBF;
-	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
-	tmp_val = 0x10;
-	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	/*
-	 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
-	 * bank and LBMAP=00 is the alternate bank.  However, the pixis
-	 * altbank code can only set bits, not clear them, so we treat 00 as
-	 * the normal bank and 11 as the alternate.
-	 */
-	switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
-	case 0:
-		puts("vBank: Standard\n");
-		break;
-	case 0x40:
-		puts("Promjet\n");
-		break;
-	case 0x80:
-		puts("NAND\n");
-		break;
-	case 0xC0:
-		puts("vBank: Alternate\n");
-		break;
-	}
-
-	mcm->abcr |= 0x00010000; /* 0 */
-	mcm->hpmr3 = 0x80000008; /* 4c */
-	mcm->hpmr0 = 0;
-	mcm->hpmr1 = 0;
-	mcm->hpmr2 = 0;
-	mcm->hpmr4 = 0;
-	mcm->hpmr5 = 0;
-
-	return 0;
-}
-
-
-int dram_init(void)
-{
-	phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size = fixed_sdram();
-#endif
-
-	setup_ddr_bat(dram_size);
-
-	debug(" DDR: ");
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
-	uint d_init;
-
-	ddr->cs0_bnds = 0x0000001f;
-	ddr->cs0_config = 0x80010202;
-
-	ddr->timing_cfg_3 = 0x00000000;
-	ddr->timing_cfg_0 = 0x00260802;
-	ddr->timing_cfg_1 = 0x3935d322;
-	ddr->timing_cfg_2 = 0x14904cc8;
-	ddr->sdram_mode = 0x00480432;
-	ddr->sdram_mode_2 = 0x00000000;
-	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
-	ddr->sdram_data_init = 0xDEADBEEF;
-	ddr->sdram_clk_cntl = 0x03800000;
-	ddr->sdram_cfg_2 = 0x04400010;
-
-#if defined(CONFIG_DDR_ECC)
-	ddr->err_int_en = 0x0000000d;
-	ddr->err_disable = 0x00000000;
-	ddr->err_sbe = 0x00010000;
-#endif
-	asm("sync;isync");
-
-	udelay(500);
-
-	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
-
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	d_init = 1;
-	debug("DDR - 1st controller: memory initializing\n");
-	/*
-	 * Poll until memory is initialized.
-	 * 512 Meg at 400 might hit this 200 times or so.
-	 */
-	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
-		udelay(1000);
-
-	debug("DDR: memory initialized\n\n");
-	asm("sync; isync");
-	udelay(500);
-#endif
-
-	return 512 * 1024 * 1024;
-#endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-
-#endif
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
-	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
-	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-				 PCI_ENET0_MEMADDR,
-				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
-	{}
-};
-#endif
-
-
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI */
-
-void pci_init_board(void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	struct fsl_pci_info pci_info;
-	u32 devdisr;
-	int first_free_busno;
-	int pci_agent;
-
-	devdisr = in_be32(&gur->devdisr);
-
-	first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
-	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: connected to PCI slots as %s" \
-			" (base address %lx)\n",
-			pci_agent ? "Agent" : "Host",
-			pci_info.regs);
-#ifndef CONFIG_PCI_PNP
-		pci1_hose.config_table = pci_mpc86xxcts_config_table;
-#endif
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
-#endif
-
-	fsl_pcie_init_board(first_free_busno);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-	return 0;
-}
-#endif
-
-/*
- * get_board_sys_clk
- * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
-	u8 i;
-	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	i = in_8(pixis_base + PIXIS_SPD);
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33333000;
-		break;
-	case 1:
-		val = 39999600;
-		break;
-	case 2:
-		val = 49999500;
-		break;
-	case 3:
-		val = 66666000;
-		break;
-	case 4:
-		val = 83332500;
-		break;
-	case 5:
-		val = 99999000;
-		break;
-	case 6:
-		val = 133332000;
-		break;
-	case 7:
-		val = 166665000;
-		break;
-	}
-
-	return val;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	out_8(pixis_base + PIXIS_RST, 0);
-
-	while (1)
-		;
-}
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
deleted file mode 100644
index 9b96d0d33f29..000000000000
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- * Authors: York Sun <yorksun@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_diu_fb.h>
-#include "../common/pixis.h"
-
-#define PX_BRDCFG0_DLINK	0x10
-#define PX_BRDCFG0_DVISEL	0x08
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
-	unsigned long speed_ccb, temp, pixval;
-
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000/pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-	debug("DIU pixval = %lu\n", pixval);
-
-	/* Modify PXCLK in GUTS CLKDVDR */
-	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
-	temp = *guts_clkdvdr & 0x2000FFFF;
-	*guts_clkdvdr = temp;				/* turn off clock */
-	*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
-	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	const char *name;
-	int gamma_fix = 0;
-	u32 pixel_format = 0x88883316;
-	u8 temp;
-
-	temp = in_8(&pixis->brdcfg0);
-
-	if (strncmp(port, "dlvds", 5) == 0) {
-		/* Dual link LVDS */
-		gamma_fix = 1;
-		temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL);
-		name = "Dual-Link LVDS";
-	} else if (strncmp(port, "lvds", 4) == 0) {
-		/* Single link LVDS */
-		temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK;
-		name = "Single-Link LVDS";
-	} else {
-		/* DVI */
-		if (in_8(&pixis->ver) == 1)	/* Board version */
-			pixel_format = 0x88882317;
-		temp |= PX_BRDCFG0_DVISEL;
-		name = "DVI";
-	}
-
-	printf("DIU:   Switching to %s monitor @ %ux%u\n", name, xres, yres);
-	out_8(&pixis->brdcfg0, temp);
-
-	return fsl_diu_init(xres, yres, pixel_format, gamma_fix);
-}
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
deleted file mode 100644
index b9ef56620480..000000000000
--- a/configs/MPC8610HPCD_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8610HPCD=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
deleted file mode 100644
index f444be0d868b..000000000000
--- a/include/configs/MPC8610HPCD.h
+++ /dev/null
@@ -1,559 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * MPC8610HPCD board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
-
-/* video */
-#define CONFIG_FSL_DIU_FB
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR		0xff800000
-#endif
-
-/*
- * virtual address to be used for temporary mappings.  There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA	0xc0000000
-
-#define CONFIG_PCI1		1	/* PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
-#define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
-#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
-#define CONFIG_ALTIVEC		1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT		0
-#define L2_ENABLE	(L2CR_L2E |0x00100000 )
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
-#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
-
-#if 0 /* TODO */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
-#define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400010
-
-#define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
-#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
-#define CONFIG_SYS_DDR_SBE		0x000f0000
-
-#endif
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
-#define CONFIG_SYS_FLASH_BASE2		0xf8000000
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-
-#define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
-
-#define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
-#if 0 /* TODO */
-#define CONFIG_SYS_BR2_PRELIM		0xf0000000
-#define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
-#endif
-#define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xe8000000	/* PIXIS registers */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE	256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE	8192
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI1_IO_BUS	0x0000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
-
-/* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_NAME		"ULI"
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
-
-/* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#define CONFIG_ULI526X
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI		1
-#define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
-
-#if !defined(CONFIG_PCI_PNP)
-#define PCI_ENET0_IOADDR	0xe0000000
-#define PCI_ENET0_MEMADDR	0xe0000000
-#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
-#endif
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif	/* CONFIG_PCI */
-
-/*
- * BAT0		2G	Cacheable, non-guarded
- * 0x0000_0000	2G	DDR
- */
-#define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
-
-/*
- * BAT1		1G	Cache-inhibited, guarded
- * 0x8000_0000	256M	PCI-1 Memory
- * 0xa000_0000	256M	PCI-Express 1 Memory
- * 0x9000_0000	256M	PCI-Express 2 Memory
- */
-
-#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
-
-/*
- * BAT2		16M	Cache-inhibited, guarded
- * 0xe100_0000	1M	PCI-1 I/O
- */
-
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
-
-/*
- * BAT3		4M	Cache-inhibited, guarded
- * 0xe000_0000	4M	CCSR
- */
-
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT \
-				       | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4		32M	Cache-inhibited, guarded
- * 0xe200_0000	1M	PCI-Express 2 I/O
- * 0xe300_0000	1M	PCI-Express 1 I/O
- */
-
-#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
-
-/*
- * BAT5		128K	Cacheable, non-guarded
- * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
-
-/*
- * BAT6		256M	Cache-inhibited, guarded
- * 0xf000_0000	256M	FLASH
- */
-#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7		4M	Cache-inhibited, guarded
- * 0xe800_0000	4M	PIXIS
- */
-#define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
-			| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_WATCHDOG			/* watchdog enabled */
-#define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_IPADDR		192.168.1.100
-
-#define CONFIG_HOSTNAME		"unknown"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
-
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		0x10000000
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
-	"echo e;md ${a}e00 9\0" \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
-	"pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
-	"pci w.w $b.0 56 ffff\0"	\
- "pci1err=setenv a e0008; run pcierr\0"	\
- "pci1errc=setenv a e0008; run pcierrc\0"
-#else
-#define	PCI_ENV ""
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
-	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0"	\
- "pcie2regs=setenv a e0009; run pciereg\0"	\
- "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
-	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
-	"pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
-	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
-	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
- "pcie1err=setenv a e000a; run pcieerr\0"	\
- "pcie2err=setenv a e0009; run pcieerr\0"	\
- "pcie1errc=setenv a e000a; run pcieerrc\0"	\
- "pcie2errc=setenv a e0009; run pcieerrc\0"
-#else
-#define	PCIE_ENV ""
-#endif
-
-#define DMA_ENV \
- "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
-	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
- "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
-	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
- "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
-	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
- "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
-	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
-
-#ifdef ENV_DEBUG
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"netdev=eth0\0"							\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-"tftpflash=tftpboot $loadaddr $uboot; "				\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"						\
-"ramdiskaddr=0x18000000\0"					\
-"ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
-"fdtaddr=0x17c00000\0"						\
-"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
-"bdev=sda3\0"					\
-"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
-"maxcpus=1"	\
-"eoi=mw e00400b0 0\0"						\
-"iack=md e00400a0 1\0"						\
-"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
-	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
-	"md ${a}f00 5\0" \
-"ddr1regs=setenv a e0002; run ddrreg\0" \
-"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
-	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
-	"md ${a}e60 1; md ${a}ef0 1d\0" \
-"guregs=setenv a e00e0; run gureg\0" \
-"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
-"mcmregs=setenv a e0001; run mcmreg\0" \
-"diuregs=md e002c000 1d\0" \
-"dium=mw e002c01c\0" \
-"diuerr=md e002c014 1\0" \
-"pmregs=md e00e1000 2b\0" \
-"lawregs=md e0000c08 4b\0" \
-"lbcregs=md e0005000 36\0" \
-"dma0regs=md e0021100 12\0" \
-"dma1regs=md e0021180 12\0" \
-"dma2regs=md e0021200 12\0" \
-"dma3regs=md e0021280 12\0" \
- PCI_ENV \
- PCIE_ENV \
- DMA_ENV
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"netdev=eth0\0"						\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
-	"consoledev=ttyS0\0"					\
-	"ramdiskaddr=0x18000000\0"				\
-	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
-	"fdtaddr=0x17c00000\0"					\
-	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
-	"bdev=sda3\0"
-#endif
-
-#define CONFIG_NFSBOOTCOMMAND					\
- "setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=$serverip:$rootpath "				\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"		\
- "tftp $loadaddr $bootfile;"					\
- "tftp $fdtaddr $fdtfile;"					\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw "				\
-	"console=$consoledev,$baudrate $othbootargs;"		\
- "tftp $ramdiskaddr $ramdiskfile;"				\
- "tftp $loadaddr $bootfile;"					\
- "tftp $fdtaddr $fdtfile;"					\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		\
- "setenv bootargs root=/dev/$bdev rw "	\
-	"console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#endif	/* __CONFIG_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 12/16] ppc: Remove MPC8610HPCD board
  2021-02-10  2:42 ` [PATCH 12/16] ppc: Remove MPC8610HPCD board Tom Rini
@ 2021-02-11 10:33   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Priyanka Jain @ 2021-02-11 10:33 UTC (permalink / raw)
  To: u-boot

>-----Original Message-----
>From: Tom Rini <trini@konsulko.com>
>Sent: Wednesday, February 10, 2021 8:13 AM
>To: u-boot at lists.denx.de
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Subject: [PATCH 12/16] ppc: Remove MPC8610HPCD board
>
>This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.
>The deadline for this conversion was the v2019.07 release.  The use of
>CONFIG_AHCI requires CONFIG_DM.  The deadline for this conversion was
>v2020.01.  Remove this board.
>
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Signed-off-by: Tom Rini <trini@konsulko.com>
>---
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 12/16] ppc: Remove MPC8610HPCD board
  2021-02-10  2:42 ` [PATCH 12/16] ppc: Remove MPC8610HPCD board Tom Rini
  2021-02-11 10:33   ` Priyanka Jain
@ 2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-15 15:44 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:53PM -0500, Tom Rini wrote:

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.
> 
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 13/16] ppc: Remove MPC8641HPCN board
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (10 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 12/16] ppc: Remove MPC8610HPCD board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-11 10:33   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 14/16] boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabled Tom Rini
                   ` (3 subsequent siblings)
  15 siblings, 2 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc86xx/Kconfig          |   7 -
 board/freescale/common/pixis.h            |  24 -
 board/freescale/mpc8641hpcn/Kconfig       |  12 -
 board/freescale/mpc8641hpcn/MAINTAINERS   |   7 -
 board/freescale/mpc8641hpcn/Makefile      |   8 -
 board/freescale/mpc8641hpcn/README        | 186 -------
 board/freescale/mpc8641hpcn/ddr.c         | 107 ----
 board/freescale/mpc8641hpcn/law.c         |  43 --
 board/freescale/mpc8641hpcn/mpc8641hpcn.c | 247 ---------
 configs/MPC8641HPCN_36BIT_defconfig       |  48 --
 configs/MPC8641HPCN_defconfig             |  48 --
 include/configs/MPC8641HPCN.h             | 632 ----------------------
 12 files changed, 1369 deletions(-)
 delete mode 100644 board/freescale/mpc8641hpcn/Kconfig
 delete mode 100644 board/freescale/mpc8641hpcn/MAINTAINERS
 delete mode 100644 board/freescale/mpc8641hpcn/Makefile
 delete mode 100644 board/freescale/mpc8641hpcn/README
 delete mode 100644 board/freescale/mpc8641hpcn/ddr.c
 delete mode 100644 board/freescale/mpc8641hpcn/law.c
 delete mode 100644 board/freescale/mpc8641hpcn/mpc8641hpcn.c
 delete mode 100644 configs/MPC8641HPCN_36BIT_defconfig
 delete mode 100644 configs/MPC8641HPCN_defconfig
 delete mode 100644 include/configs/MPC8641HPCN.h

diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 294485794bdf..7de42b5f2576 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -13,12 +13,6 @@ config TARGET_SBC8641D
 	select ARCH_MPC8641
 	select BOARD_EARLY_INIT_F
 
-config TARGET_MPC8641HPCN
-	bool "Support MPC8641HPCN"
-	select ARCH_MPC8641
-	select FSL_DDR_INTERACTIVE
-	imply SCSI
-
 config TARGET_XPEDITE517X
 	bool "Support xpedite517x"
 	select ARCH_MPC8641
@@ -57,7 +51,6 @@ config SYS_FSL_NUM_LAWS
 		Number of local access windows. This is fixed per SoC.
 		If not sure, do not change.
 
-source "board/freescale/mpc8641hpcn/Kconfig"
 source "board/sbc8641d/Kconfig"
 source "board/xes/xpedite517x/Kconfig"
 
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
index 36c94862a55b..049f1967c595 100644
--- a/board/freescale/common/pixis.h
+++ b/board/freescale/common/pixis.h
@@ -72,30 +72,6 @@ typedef struct pixis {
 	u8 res2[34];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_TARGET_MPC8641HPCN)
-typedef struct pixis {
-	u8 id;
-	u8 ver;
-	u8 pver;
-	u8 csr;
-	u8 rst;
-	u8 pwr;
-	u8 aux;
-	u8 spd;
-	u8 res[8];
-	u8 vctl;
-	u8 vstat;
-	u8 vcfgen0;
-	u8 vcfgen1;
-	u8 vcore0;
-	u8 res1;
-	u8 vboot;
-	u8 vspeed[2];
-	u8 vclkh;
-	u8 vclkl;
-	u8 watch;
-	u8 res3[36];
-} __attribute__ ((packed)) pixis_t;
 #else
 #error Need to define pixis_t for this board
 #endif
diff --git a/board/freescale/mpc8641hpcn/Kconfig b/board/freescale/mpc8641hpcn/Kconfig
deleted file mode 100644
index ae45d6333748..000000000000
--- a/board/freescale/mpc8641hpcn/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8641HPCN
-
-config SYS_BOARD
-	default "mpc8641hpcn"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8641HPCN"
-
-endif
diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS
deleted file mode 100644
index c95721876751..000000000000
--- a/board/freescale/mpc8641hpcn/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8641HPCN BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8641hpcn/
-F:	include/configs/MPC8641HPCN.h
-F:	configs/MPC8641HPCN_defconfig
-F:	configs/MPC8641HPCN_36BIT_defconfig
diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile
deleted file mode 100644
index 86b87193dd66..000000000000
--- a/board/freescale/mpc8641hpcn/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y	+= mpc8641hpcn.o
-obj-y	+= law.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8641hpcn/README b/board/freescale/mpc8641hpcn/README
deleted file mode 100644
index 77909a838332..000000000000
--- a/board/freescale/mpc8641hpcn/README
+++ /dev/null
@@ -1,186 +0,0 @@
-Freescale MPC8641HPCN board
-===========================
-
-Created 05/24/2006 Haiying Wang
--------------------------------
-
-1. Building U-Boot
-------------------
-The 86xx HPCN code base is known to compile using:
-    Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
-
-    $ make MPC8641HPCN_config
-    Configuring for MPC8641HPCN board...
-
-    $ make
-
-
-2. Switch and Jumper Setting
-----------------------------
-Jumpers:
-	J14 Pins 1-2 (near plcc32 socket)
-
-Switches:
-	SW1(1-5) = 01100	CONFIG_SYS_COREPLL	= 01000 :: CORE =   2:1
-						  01100 :: CORE = 2.5:1
-						  10000 :: CORE =   3:1
-						  11100 :: CORE = 3.5:1
-						  10100 :: CORE =   4:1
-						  01110 :: CORE = 4.5:1
-	SW1(6-8) = 001		CONFIG_SYS_SYSCLK	= 000	:: SYSCLK = 33MHz
-						  001	:: SYSCLK = 40MHz
-
-	SW2(1-4) = 1100		CONFIG_SYS_CCBPLL	= 0010	:: 2X
-						  0100	:: 4X
-						  0110	:: 6X
-						  1000	:: 8X
-						  1010	:: 10X
-						  1100	:: 12X
-						  1110	:: 14X
-						  0000	:: 16X
-	SW2(5-8) = 1110		CONFIG_SYS_BOOTLOC	= 1110	:: boot 16-bit localbus
-
-	SW3(1-7) = 0011000	CONFIG_SYS_VID		= 0011000 :: VCORE = 1.2V
-						  0100000 :: VCORE = 1.11V
-	SW3(8)	 = 0		VCC_PLAT	= 0	:: VCC_PLAT = 1.2V
-						  1	:: VCC_PLAT = 1.0V
-
-	SW4(1-2) = 11		CONFIG_SYS_HOSTMODE	= 11	:: both prots host/root
-	SW4(3-4) = 11		CONFIG_SYS_BOOTSEQ	= 11	:: no boot seq
-	SW4(5-8) = 0011		CONFIG_SYS_IOPORT	= 0011	:: both PEX
-
-	SW5(1)	 = 1		CONFIG_SYS_FLASHMAP	= 1	:: boot from flash
-						  0	:: boot from PromJet
-	SW5(2)	 = 1		CONFIG_SYS_FLASHBANK	= 1	:: swap upper/lower
-							 halves (virtual banks)
-						  0	:: normal
-	SW5(3)	 = 0		CONFIG_SYS_FLASHWP	= 0	:: not protected
-	SW5(4)	 = 0		CONFIG_SYS_PORTDIV	= 1	:: 2:1 for PD4
-							   1:1 for PD6
-	SW5(5-6) = 11		CONFIG_SYS_PIXISOPT	= 11	:: s/w determined
-	SW5(7-8) = 11		CONFIG_SYS_LADOPT	= 11	:: s/w determined
-
-	SW6(1)	 = 1		CONFIG_SYS_CPUBOOT	= 1	:: no boot holdoff
-	SW6(2)	 = 1		CONFIG_SYS_BOOTADDR	= 1	:: no traslation
-	SW6(3-5) = 000		CONFIG_SYS_REFCLKSEL	= 000	:: 100MHZ
-	SW6(6)	 = 1		CONFIG_SYS_SERROM_ADDR= 1	::
-	SW6(7)	 = 1		CONFIG_SYS_MEMDEBUG	= 1	::
-	SW6(8)	 = 1		CONFIG_SYS_DDRDEBUG	= 1	::
-
-	SW8(1)	 = 1		ACZ_SYNC	= 1	:: 48MHz on TP49
-	SW8(2)	 = 1		ACB_SYNC	= 1	:: THRMTRIP disabled
-	SW8(3)	 = 1		ACZ_SDOUT	= 1	:: p4 mode
-	SW8(4)	 = 1		ACB_SDOUT	= 1	:: PATA freq. = 133MHz
-	SW8(5)	 = 0		SUSLED		= 0	:: SouthBridge Mode
-	SW8(6)	 = 0		SPREAD		= 0	:: REFCLK SSCG Disabled
-	SW8(7)	 = 1		ACPWR		= 1	:: non-battery
-	SW8(8)	 = 0		CONFIG_SYS_IDWP	= 0	:: write enable
-
-
-3. Flash U-Boot
----------------
-The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
-It is possible to use either half to boot using U-Boot.  Switch 5 bit 2
-is used for this purpose.
-
-0xEF800000 to 0xEFBFFFFF - 4MB
-0xEFC00000 to 0xEFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xEFF00000.
-When this bit is 1, U-Boot is at 0xEFB00000.
-
-Use the above mentioned flash commands to program the other half, and
-use switch 5, bit 2 to alternate between the halves.  Note: The booting
-version of U-Boot will always be at 0xEFF00000.
-
-To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
-
-	tftp 1000000 u-boot.bin
-	protect off all
-	erase eff00000 +$filesize
-	cp.b 1000000 eff00000 $filesize
-
-or use tftpflash command:
-	run tftpflash
-
-To Flash U-Boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
-
-	tftp 1000000 u-boot.bin
-	erase efb00000 +$filesize
-	cp.b 1000000 efb00000 $filesize
-
-
-4. Memory Map
--------------
-NOTE:  RIO and PCI are mutually exclusive, so they share an address
-
-For 32-bit U-Boot, devices are mapped so that the virtual address ==
-the physical address, and the map looks liks this:
-
-	Memory Range			Device		Size
-	------------			------		----
-	0x0000_0000	0x7fff_ffff	DDR		2G
-	0x8000_0000	0x9fff_ffff	RIO MEM		512M
-	0x8000_0000	0x9fff_ffff	PCI1/PEX1 MEM	512M
-	0xa000_0000	0xbfff_ffff	PCI2/PEX2 MEM	512M
-	0xffe0_0000	0xffef_ffff	CCSR		1M
-	0xffdf_0000	0xffdf_7fff	PIXIS		8K
-	0xffdf_8000	0xffdf_ffff	CF		8K
-	0xf840_0000	0xf840_3fff	Stack space	32K
-	0xffc0_0000	0xffc0_ffff	PCI1/PEX1 IO	64K
-	0xffc1_0000	0xffc1_ffff	PCI2/PEX2 IO	64K
-	0xef80_0000	0xefff_ffff	Flash		8M
-
-For 36-bit-enabled U-Boot, the virtual map is the same as for 32-bit.
-However, the physical map is altered to reside in 36-bit space, as follows.
-Addresses are no longer mapped with VA == PA.  All accesses from
-software use the VA; the PA is only used for setting up windows
-and mappings. Note that with the exception of PCI MEM and RIO, the low
- 32 bits are the same as the VA above; only the top 4 bits vary:
-
-	Memory Range			Device		Size
-	------------			------		----
-	0x0_0000_0000	0x0_7fff_ffff	DDR		2G
-	0xc_0000_0000	0xc_1fff_ffff	RIO MEM		512M
-	0xc_0000_0000	0xc_1fff_ffff	PCI1/PEX1 MEM	512M
-	0xc_2000_0000	0xc_3fff_ffff	PCI2/PEX2 MEM	512M
-	0xf_ffe0_0000	0xf_ffef_ffff	CCSR		1M
-	0xf_ffdf_0000	0xf_ffdf_7fff	PIXIS		8K
-	0xf_ffdf_8000	0xf_ffdf_ffff	CF		8K
-	0x0_f840_0000	0xf_f840_3fff	Stack space	32K
-	0xf_ffc0_0000	0xf_ffc0_ffff	PCI1/PEX1 IO	64K
-	0xf_ffc1_0000	0xf_ffc1_ffff	PCI2/PEX2 IO	64K
-	0xf_ef80_0000	0xf_efff_ffff	Flash		8M
-
-5. pixis_reset command
---------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer.  When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
-	pixis_reset
-	pixis_reset altbank
-	pixis_reset altbank wd
-	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
-	/* reset to current bank, like "reset" command */
-	pixis_reset
-
-	/* reset board but use the to alternate flash bank */
-	pixis_reset altbank
-
-	/* reset board, use alternate flash bank with watchdog timer enabled*/
-	pixis_reset altbank wd
-
-	/* reset board to alternate bank with frequency changed.
-	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
-	 */
-	pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
deleted file mode 100644
index df7e3eceed70..000000000000
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008,2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 cpo;
-	u32 write_data_delay;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-const struct board_specific_parameters dimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{4,  333,    7,   7,     3},
-	{4,  549,    7,   9,     3},
-	{4,  650,    7,  10,     4},
-	{2,  333,    7,   7,     3},
-	{2,  549,    7,   9,     3},
-	{2,  650,    7,  10,     4},
-	{1,  333,    7,   7,     3},
-	{1,  549,    7,   9,     3},
-	{1,  650,    7,  10,     4},
-	{}
-};
-
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-const struct board_specific_parameters *dimms[] = {
-	dimm0,
-	dimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			dimm_params_t *pdimm,
-			unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	unsigned int i;
-	ulong ddr_freq;
-
-	if (ctrl_num > 1) {
-		printf("Wrong parameter for controller number %d", ctrl_num);
-		return;
-	}
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-		if (pdimm[i].n_ranks)
-			break;
-	}
-	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)    /* no DIMM */
-		return;
-
-	pbsp = dimms[ctrl_num];
-
-	/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm[i].n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	/* 2T timing enable */
-	popts->twot_en = 1;
-}
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
deleted file mode 100644
index b73d66088318..000000000000
--- a/board/freescale/mpc8641hpcn/law.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000     0x9fff_ffff     PCIE1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCIE2 MEM                512M
- * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
- * endif
- * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
- * 0xffc0_0000     0xffc0_ffff     PCIE1 IO                 64K
- * 0xffc1_0000     0xffc1_ffff     PCIE2 IO                 64K
- * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
- * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
- * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR doesn't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-#endif
-	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
deleted file mode 100644
index 0f9aea469b11..000000000000
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ /dev/null
@@ -1,247 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t fixed_sdram(void);
-
-int checkboard(void)
-{
-	u8 vboot;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	vboot = in_8(pixis_base + PIXIS_VBOOT);
-	if (vboot & PIXIS_VBOOT_FMAP)
-		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
-	else
-		puts ("Promjet\n");
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size = fixed_sdram();
-#endif
-
-	setup_ddr_bat(dram_size);
-
-	debug("    DDR: ");
-	gd->ram_size = dram_size;
-
-	return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t
-fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-	ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
-	ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
-
-#if defined (CONFIG_DDR_ECC)
-	ddr->err_disable = 0x0000008D;
-	ddr->err_sbe = 0x00ff0000;
-#endif
-	asm("sync;isync");
-
-	udelay(500);
-
-#if defined (CONFIG_DDR_ECC)
-	/* Enable ECC checking */
-	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-#else
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-#endif
-	asm("sync; isync");
-
-	udelay(500);
-#endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif	/* !defined(CONFIG_SPD_EEPROM) */
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCIE1
-		/*
-		 * Activate ULI1575 legacy chip by performing a fake
-		 * memory access.  Needed to make ULI RTC work.
-		 */
-		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
-				       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
-#endif /* CONFIG_PCIE1 */
-}
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	int off;
-	u64 *tmp;
-	int addrcells;
-
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-	/*
-	 * Warn if it looks like the device tree doesn't match u-boot.
-	 * This is just an estimation, based on the location of CCSR,
-	 * which is defined by the "reg" property in the soc node.
-	 */
-	off = fdt_path_offset(blob, "/soc8641");
-	addrcells = fdt_address_cells(blob, 0);
-	tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
-
-	if (tmp) {
-		u64 addr;
-
-		if (addrcells == 1)
-			addr = *(u32 *)tmp;
-		else
-			addr = *tmp;
-
-		if (addr != CONFIG_SYS_CCSRBAR_PHYS)
-			printf("WARNING: The CCSRBAR address in your .dts "
-			       "does not match the address of the CCSR "
-			       "in u-boot.  This means your .dts might "
-			       "be old.\n");
-	}
-
-	return 0;
-}
-#endif
-
-
-/*
- * get_board_sys_clk
- *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
-	u8 i, go_bit, rd_clks;
-	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	go_bit = in_8(pixis_base + PIXIS_VCTL);
-	go_bit &= 0x01;
-
-	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
-	rd_clks &= 0x1C;
-
-	/*
-	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
-	 * should we be using the AUX register. Remember, we also set the
-	 * GO bit to boot from the alternate bank on the on-board flash
-	 */
-
-	if (go_bit) {
-		if (rd_clks == 0x1c)
-			i = in_8(pixis_base + PIXIS_AUX);
-		else
-			i = in_8(pixis_base + PIXIS_SPD);
-	} else {
-		i = in_8(pixis_base + PIXIS_SPD);
-	}
-
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33000000;
-		break;
-	case 1:
-		val = 40000000;
-		break;
-	case 2:
-		val = 50000000;
-		break;
-	case 3:
-		val = 66000000;
-		break;
-	case 4:
-		val = 83000000;
-		break;
-	case 5:
-		val = 100000000;
-		break;
-	case 6:
-		val = 134000000;
-		break;
-	case 7:
-		val = 166000000;
-		break;
-	}
-
-	return val;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	/* Initialize TSECs */
-	cpu_eth_init(bis);
-	return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	out_8(pixis_base + PIXIS_RST, 0);
-
-	while (1)
-		;
-}
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
deleted file mode 100644
index 2c093b9bade4..000000000000
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xeff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8641HPCN=y
-CONFIG_PHYS_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=8
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
deleted file mode 100644
index a37fad031960..000000000000
--- a/configs/MPC8641HPCN_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xeff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8641HPCN=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=8
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
deleted file mode 100644
index e6e1e7943c7a..000000000000
--- a/include/configs/MPC8641HPCN.h
+++ /dev/null
@@ -1,632 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2006, 2010-2011 Freescale Semiconductor.
- *
- * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
- */
-
-/*
- * MPC8641HPCN board configuration file
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc. in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
-
-/*
- * default CCSRBAR is at 0xff700000
- * assume U-Boot is less than 0.5MB
- */
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
-#endif
-
-/*
- * virtual address to be used for temporary mappings.  There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA	0xe0000000
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-
-#define CONFIG_PCIE1		1	/* PCIE controller 1 (ULI bridge) */
-#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot) */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
-
-#define CONFIG_ALTIVEC		1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT		0
-#define L2_ENABLE	(L2CR_L2E)
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
-#endif
-
-/*
- * With the exception of PCI Memory and Rapid IO, most devices will simply
- * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
- * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
-#else
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
-
-/* Physical addresses */
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
-			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
-
-#define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	2
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/*
- * I2C addresses of SPD EEPROMs
- */
-#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
-#define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
-#define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
-
-/*
- * These are used when DDR doesn't use SPD.
- */
-#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x39357322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
-#define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06090100
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400000
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
-#define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
-			    CONFIG_SYS_PHYS_ADDR_HIGH)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
-				 | 0x00001001)	/* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
-
-#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
-				 | 0x00001001)	/* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
-
-#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
-				 | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
-
-/*
- * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
- * The PIXIS and CF by themselves aren't large enough to take up the 128k
- * required for the smallest BAT mapping, so there's a 64k hole.
- */
-#define CONFIG_SYS_LBC_BASE		0xffde0000
-#define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
-#define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
-#define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
-						    CONFIG_SYS_PHYS_ADDR_HIGH)
-#define PIXIS_SIZE		0x00008000	/* 32k */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
-
-/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
-#define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
-#define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
-
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef	CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE	256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-
-/*
- * RapidIO MMU
- */
-#define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
-			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-
-#define CONFIG_SYS_PCIE1_NAME		"ULI"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
-			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
-#define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
-#define CONFIG_SYS_PCIE1_IO_PHYS \
-	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
-			    CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
-
-#ifdef CONFIG_PHYS_64BIT
-/*
- * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
- * This will increase the amount of PCI address space available for
- * for mapping RAM.
- */
-#define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#endif
-#define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
-#define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
-					 + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
-					 + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
-					 + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
-					 + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI			1
-#define CONFIG_USB_OHCI_NEW		1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif	/* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_TSEC1		1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC2		1
-#define CONFIG_TSEC2_NAME	"eTSEC2"
-#define CONFIG_TSEC3		1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-#define CONFIG_TSEC4		1
-#define CONFIG_TSEC4_NAME	"eTSEC4"
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC3_PHY_ADDR		2
-#define TSEC4_PHY_ADDR		3
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME		"eTSEC1"
-
-#endif	/* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_PHYS_64BIT
-#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
-#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
-
-/* Put physical address into the BAT format */
-#define BAT_PHYS_ADDR(low, high) \
-	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
-/* Convert high/low pairs to actual 64-bit value */
-#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
-#else
-/* 32-bit systems just ignore the "high" bits */
-#define BAT_PHYS_ADDR(low, high)        (low)
-#define PAIRED_PHYS_TO_PHYS(low, high)  (low)
-#endif
-
-/*
- * BAT0		DDR
- */
-#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-
-/*
- * BAT1		LBC (PIXIS/CF)
- */
-#define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
-				 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
-
-/* if CONFIG_PCI:
- * BAT2		PCIE1 and PCIE1 MEM
- * if CONFIG_RIO
- * BAT2		Rapidio Memory
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
-#else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
-				 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
-					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
-#endif
-
-/*
- * BAT3		CCSR Space
- */
-#define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
-					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
-				 | BATU_VP)
-#define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
-					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT \
-				       | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
-				       | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4		PCIE1_IO and PCIE2_IO
- */
-#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
-				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
-
-/*
- * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
-
-/*
- * BAT6		FLASH
- */
-#define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_CACHEINHIBIT \
-				 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
-				 | BATU_VP)
-#define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
-					       CONFIG_SYS_PHYS_ADDR_HIGH) \
-				 | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
-				 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7		FREE - used later for tmp mappings
- */
-#define CONFIG_SYS_DBAT7L 0x00000000
-#define CONFIG_SYS_DBAT7U 0x00000000
-#define CONFIG_SYS_IBAT7L 0x00000000
-#define CONFIG_SYS_IBAT7U 0x00000000
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-    #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HAS_ETH0		1
-#define CONFIG_HAS_ETH1		1
-#define CONFIG_HAS_ETH2		1
-#define CONFIG_HAS_ETH3		1
-
-#define CONFIG_IPADDR		192.168.1.100
-
-#define CONFIG_HOSTNAME		"unknown"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		0x10000000
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-	"tftpflash=tftpboot $loadaddr $uboot; "				\
-		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" +$filesize; "	\
-		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize; "	\
-		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-			" +$filesize; "	\
-		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-			" $filesize\0"	\
-	"consoledev=ttyS0\0"						\
-	"ramdiskaddr=0x18000000\0"						\
-	"ramdiskfile=your.ramdisk.u-boot\0"				\
-	"fdtaddr=0x17c00000\0"						\
-	"fdtfile=mpc8641_hpcn.dtb\0"					\
-	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
-	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
-	"maxcpus=2"
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-	      "nfsroot=$serverip:$rootpath "				\
-	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	      "console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-	      "console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
-
-#endif	/* __CONFIG_H */
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 13/16] ppc: Remove MPC8641HPCN board
  2021-02-10  2:42 ` [PATCH 13/16] ppc: Remove MPC8641HPCN board Tom Rini
@ 2021-02-11 10:33   ` Priyanka Jain
  2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Priyanka Jain @ 2021-02-11 10:33 UTC (permalink / raw)
  To: u-boot



>-----Original Message-----
>From: Tom Rini <trini@konsulko.com>
>Sent: Wednesday, February 10, 2021 8:13 AM
>To: u-boot at lists.denx.de
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Subject: [PATCH 13/16] ppc: Remove MPC8641HPCN board
>
>This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.
>The deadline for this conversion was the v2019.07 release.  The use of
>CONFIG_AHCI requires CONFIG_DM.  The deadline for this conversion was
>v2020.01.  Remove this board.
>
>Cc: Priyanka Jain <priyanka.jain@nxp.com>
>Signed-off-by: Tom Rini <trini@konsulko.com>
>---
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 13/16] ppc: Remove MPC8641HPCN board
  2021-02-10  2:42 ` [PATCH 13/16] ppc: Remove MPC8641HPCN board Tom Rini
  2021-02-11 10:33   ` Priyanka Jain
@ 2021-02-15 15:44   ` Tom Rini
  1 sibling, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-15 15:44 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:54PM -0500, Tom Rini wrote:

> This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
> deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
> requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
> this board.
> 
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 14/16] boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabled
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (11 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 13/16] ppc: Remove MPC8641HPCN board Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-02-10  2:42 ` [PATCH 15/16] drivers: ata: Remove mvsata_ide driver Tom Rini
                   ` (2 subsequent siblings)
  15 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

There are a number of platforms that depend on a SATA driver that has
been converted to require AHCI but the platforms themselves are behind
on other migrations that would make it trivial to enable AHCI.  Disable
SATA in these cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc83xx/Kconfig              |  2 --
 arch/powerpc/cpu/mpc85xx/Kconfig              | 20 -------------------
 configs/MPC8315ERDB_defconfig                 |  1 -
 configs/MPC837XERDB_SLAVE_defconfig           |  1 -
 configs/MPC837XERDB_defconfig                 |  1 -
 configs/cgtqmx6eval_defconfig                 |  1 -
 ...trolcenterd_36BIT_SDCARD_DEVELOP_defconfig |  1 -
 configs/controlcenterd_36BIT_SDCARD_defconfig |  1 -
 configs/udoo_defconfig                        |  1 -
 include/configs/udoo.h                        |  1 -
 10 files changed, 30 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index f34acf7fa7f5..b19c3cefabab 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -79,8 +79,6 @@ config TARGET_MPC837XEMDS
 	bool "Support MPC837XEMDS"
 	select ARCH_MPC837X
 	select BOARD_EARLY_INIT_F
-	imply CMD_SATA
-	imply FSL_SATA
 
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 870ab800e86b..4d3d310d07b4 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -45,7 +45,6 @@ config TARGET_P5040DS
 	select PHYS_64BIT
 	select ARCH_P5040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_MPC8541CDS
@@ -75,7 +74,6 @@ config TARGET_P1010RDB_PA
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	imply CMD_EEPROM
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_P1010RDB_PB
@@ -85,7 +83,6 @@ config TARGET_P1010RDB_PB
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	imply CMD_EEPROM
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_P1020RDB_PC
@@ -154,7 +151,6 @@ config TARGET_T1040RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T1040D4RDB
@@ -163,7 +159,6 @@ config TARGET_T1040D4RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T1042RDB
@@ -172,7 +167,6 @@ config TARGET_T1042RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 
 config TARGET_T1042D4RDB
 	bool "Support T1042D4RDB"
@@ -180,7 +174,6 @@ config TARGET_T1042D4RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T1042RDB_PI
@@ -189,7 +182,6 @@ config TARGET_T1042RDB_PI
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
-	imply CMD_SATA
 	imply PANIC_HANG
 
 config TARGET_T2080QDS
@@ -528,10 +520,8 @@ config ARCH_P1010
 	imply CMD_EEPROM
 	imply CMD_MTDPARTS
 	imply CMD_NAND
-	imply CMD_SATA
 	imply CMD_PCI
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_P1011
 	bool
@@ -791,9 +781,7 @@ config ARCH_P5020
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_ELBC
-	imply CMD_SATA
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_P5040
 	bool
@@ -816,9 +804,7 @@ config ARCH_P5040
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_ELBC
-	imply CMD_SATA
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_QEMU_E500
 	bool
@@ -886,9 +872,7 @@ config ARCH_T1040
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
-	imply CMD_SATA
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_T1042
 	bool
@@ -910,9 +894,7 @@ config ARCH_T1042
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
-	imply CMD_SATA
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_T2080
 	bool
@@ -985,10 +967,8 @@ config ARCH_T4160
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
 	select FSL_IFC
-	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
-	imply FSL_SATA
 
 config ARCH_T4240
 	bool
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index f03fec92f867..1a8983584e9e 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -118,7 +118,6 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
index ea84564d9af8..388779bec1c3 100644
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ b/configs/MPC837XERDB_SLAVE_defconfig
@@ -111,7 +111,6 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_MII=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 0d8ec8e9cafd..4c3076bb54b6 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -152,7 +152,6 @@ CONFIG_CMD_IMLS=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_MII=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 26f74662f80a..e92dcb637c8d 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -37,7 +37,6 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index 41785d09d0fc..4414563f1875 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -24,7 +24,6 @@ CONFIG_CMD_EEPROM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index 777f5aee41f8..24f7a8dbffeb 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -24,7 +24,6 @@ CONFIG_CMD_EEPROM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_MII=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index f72b9645dac3..d70a6ca41ce1 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -24,7 +24,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index b4fbf8c6383d..e250c7e9d922 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -65,7 +65,6 @@
 
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
-	func(SATA, sata, 0) \
 	func(DHCP, dhcp, na)
 
 #include <config_distro_bootcmd.h>
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 15/16] drivers: ata: Remove mvsata_ide driver
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (12 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 14/16] boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabled Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-04-12  0:25   ` Tom Rini
  2021-02-10  2:42 ` [PATCH 16/16] ata: Make LIBATA means AHCI is enabled mandatory Tom Rini
  2021-04-12  0:24 ` [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
  15 siblings, 1 reply; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

The mvsata_ide driver was due for DM conversion by v2019.07.  As that
has long passed, remove the driver and disable it in the boards which
had enabled it.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 Makefile                                     |  10 -
 arch/arm/mach-kirkwood/include/mach/config.h |   2 -
 configs/dns325_defconfig                     |   1 -
 configs/dreamplug_defconfig                  |   1 -
 configs/ds109_defconfig                      |   1 -
 configs/edminiv2_defconfig                   |   1 -
 configs/goflexhome_defconfig                 |   1 -
 configs/guruplug_defconfig                   |   1 -
 configs/ib62x0_defconfig                     |   1 -
 configs/nas220_defconfig                     |   1 -
 configs/nsa310s_defconfig                    |   1 -
 drivers/ata/Kconfig                          |   6 -
 drivers/ata/Makefile                         |   1 -
 drivers/ata/mvsata_ide.c                     | 199 -------------------
 include/configs/dns325.h                     |   8 -
 include/configs/dreamplug.h                  |   7 -
 include/configs/ds109.h                      |   7 -
 include/configs/edminiv2.h                   |   3 -
 include/configs/goflexhome.h                 |   7 -
 include/configs/guruplug.h                   |   7 -
 include/configs/ib62x0.h                     |   3 -
 include/configs/nas220.h                     |   8 -
 include/configs/nsa310s.h                    |   2 -
 include/configs/sheevaplug.h                 |   3 -
 scripts/config_whitelist.txt                 |   2 -
 25 files changed, 284 deletions(-)
 delete mode 100644 drivers/ata/mvsata_ide.c

diff --git a/Makefile b/Makefile
index ebbedb1fb1af..9d6ac5e16fe5 100644
--- a/Makefile
+++ b/Makefile
@@ -1064,16 +1064,6 @@ ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
 	@echo >&2 "===================================================="
 endif
 endif
-ifeq ($(CONFIG_MVSATA_IDE),y)
-	@echo >&2 "===================== WARNING ======================"
-	@echo >&2 "This board does use CONFIG_MVSATA_IDE which is not"
-	@echo >&2 "ported to driver-model (DM) yet. Please update the storage"
-	@echo >&2 "controller driver to use CONFIG_AHCI before the v2019.07"
-	@echo >&2 "release."
-	@echo >&2 "Failure to update by the deadline may result in board removal."
-	@echo >&2 "See doc/driver-model/migration.rst for more info."
-	@echo >&2 "===================================================="
-endif
 ifeq ($(CONFIG_LIBATA),y)
 ifneq ($(CONFIG_AHCI),y)
 	@echo >&2 "===================== WARNING ======================"
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index 3bd032e08790..ef68fc86b22e 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -74,8 +74,6 @@
  */
 #ifdef CONFIG_IDE
 #define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT1
 /* Needs byte-swapping for ATA data register */
 #define CONFIG_IDE_SWAP_IO
 /* Data, registers and alternate blocks are at the same offset */
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index a5fe9cd33160..493c802d5208 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -36,7 +36,6 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
 CONFIG_BLK=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index 2c27726fcde4..b4dedc9e59b1 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -34,7 +34,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000
 CONFIG_ENV_ADDR=0x100000
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
 CONFIG_BLK=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
index e412e3f5937c..77c094b76637 100644
--- a/configs/ds109_defconfig
+++ b/configs/ds109_defconfig
@@ -30,7 +30,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000
 CONFIG_ENV_ADDR=0x3D0000
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
 CONFIG_BLK=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index 916775e9ed17..0aacb35e44c4 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xFFF84000
 CONFIG_NETCONSOLE=y
-CONFIG_MVSATA_IDE=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index b271822dcbfd..6e3e6325e921 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -37,7 +37,6 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
 CONFIG_BLK=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index f7e934bcf89e..a3fe98cabf7a 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -38,7 +38,6 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
 CONFIG_BLK=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 1fbf03442d0c..57ccfe71fbd7 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NETCONSOLE=y
-CONFIG_MVSATA_IDE=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index e89b6b9e14d6..3e031604eec2 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -38,7 +38,6 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
 CONFIG_BLK=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index bec1707ddc13..e4cf1c470e05 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NETCONSOLE=y
-CONFIG_MVSATA_IDE=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 3914f996d91c..9ff4b8736c1f 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -83,12 +83,6 @@ config FSL_SATA
 	  Enable this driver to support the SATA controller found in
 	  some Freescale PowerPC SoCs.
 
-config MVSATA_IDE
-	bool "Enable Marvell SATA controller driver support via IDE interface"
-	help
-	  Enable this driver to support the SATA controller found in
-	  some Marvell SoCs, running in IDE compatibility mode using PIO.
-
 config SATA_MV
 	bool "Enable Marvell SATA controller driver support"
 	select AHCI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 98fb4807008e..4811b2f82c4e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 obj-$(CONFIG_FSL_SATA) += fsl_sata.o
 obj-$(CONFIG_LIBATA) += libata.o
-obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
 obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
 obj-$(CONFIG_SATA_MV) += sata_mv.o
diff --git a/drivers/ata/mvsata_ide.c b/drivers/ata/mvsata_ide.c
deleted file mode 100644
index 41f9a91617d4..000000000000
--- a/drivers/ata/mvsata_ide.c
+++ /dev/null
@@ -1,199 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#if defined(CONFIG_ARCH_ORION5X)
-#include <asm/arch/orion5x.h>
-#elif defined(CONFIG_ARCH_KIRKWOOD)
-#include <asm/arch/soc.h>
-#elif defined(CONFIG_ARCH_MVEBU)
-#include <linux/mbus.h>
-#endif
-
-/* SATA port registers */
-struct mvsata_port_registers {
-	u32 reserved0[10];
-	u32 edma_cmd;
-	u32 reserved1[181];
-	/* offset 0x300 : ATA Interface registers */
-	u32 sstatus;
-	u32 serror;
-	u32 scontrol;
-	u32 ltmode;
-	u32 phymode3;
-	u32 phymode4;
-	u32 reserved2[5];
-	u32 phymode1;
-	u32 phymode2;
-	u32 bist_cr;
-	u32 bist_dw1;
-	u32 bist_dw2;
-	u32 serrorintrmask;
-};
-
-/*
- * Sanity checks:
- * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
- * - for ide_preinit to make sense, we need at least one of
- *   CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
- * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
- * Fail with an explanation message if these conditions are not met.
- * This is particularly important for CONFIG_IDE_PREINIT, because
- * its lack would not cause a build error.
- */
-
-#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
-#error CONFIG_SYS_ATA_BASE_ADDR must be defined
-#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
-   && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
-#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
-   must be defined
-#elif !defined(CONFIG_IDE_PREINIT)
-#error CONFIG_IDE_PREINIT must be defined
-#endif
-
-/*
- * Masks and values for SControl DETection and Interface Power Management,
- * and for SStatus DETection.
- */
-
-#define MVSATA_EDMA_CMD_ATA_RST		0x00000004
-#define MVSATA_SCONTROL_DET_MASK		0x0000000F
-#define MVSATA_SCONTROL_DET_NONE		0x00000000
-#define MVSATA_SCONTROL_DET_INIT		0x00000001
-#define MVSATA_SCONTROL_IPM_MASK		0x00000F00
-#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED	0x00000300
-#define MVSATA_SCONTROL_MASK \
-	(MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
-#define MVSATA_PORT_INIT \
-	(MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
-#define MVSATA_PORT_USE \
-	(MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
-#define MVSATA_SSTATUS_DET_MASK			0x0000000F
-#define MVSATA_SSTATUS_DET_DEVCOMM		0x00000003
-
-/*
- * Status codes to return to client callers. Currently, callers ignore
- * exact value and only care for zero or nonzero, so no need to make this
- * public, it is only #define'd for clarity.
- * If/when standard negative codes are implemented in U-Boot, then these
- * #defines should be moved to, or replaced by ones from, the common list
- * of status codes.
- */
-
-#define MVSATA_STATUS_OK	0
-#define MVSATA_STATUS_TIMEOUT	-1
-
-/*
- * Registers for SATA MBUS memory windows
- */
-
-#define MVSATA_WIN_CONTROL(w)	(MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
-#define MVSATA_WIN_BASE(w)	(MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
-
-/*
- * Initialize SATA memory windows for Armada XP
- */
-
-#ifdef CONFIG_ARCH_MVEBU
-static void mvsata_ide_conf_mbus_windows(void)
-{
-	const struct mbus_dram_target_info *dram;
-	int i;
-
-	dram = mvebu_mbus_dram_info();
-
-	/* Disable windows, Set Size/Base to 0  */
-	for (i = 0; i < 4; i++) {
-		writel(0, MVSATA_WIN_CONTROL(i));
-		writel(0, MVSATA_WIN_BASE(i));
-	}
-
-	for (i = 0; i < dram->num_cs; i++) {
-		const struct mbus_dram_window *cs = dram->cs + i;
-		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
-				(dram->mbus_dram_target_id << 4) | 1,
-				MVSATA_WIN_CONTROL(i));
-		writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
-	}
-}
-#endif
-
-/*
- * Initialize one MVSATAHC port: set SControl's IPM to "always active"
- * and DET to "reset", then wait for SStatus's DET to become "device and
- * comm ok" (or time out after 50 us if no device), then set SControl's
- * DET back to "no action".
- */
-
-static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
-{
-	u32 control;
-	u32 status;
-	u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
-
-	/* Hard reset */
-	writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
-	udelay(25); /* taken from original marvell port */
-	writel(0, &port->edma_cmd);
-
-	/* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
-	control = readl(&port->scontrol);
-	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
-	writel(control, &port->scontrol);
-	/* Toggle control DET back to 0 (normal operation) */
-	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
-	writel(control, &port->scontrol);
-	/* wait for status DET to become 3 (device and communication OK) */
-	while (--timeleft) {
-		status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
-		if (status == MVSATA_SSTATUS_DET_DEVCOMM)
-			break;
-		udelay(1);
-	}
-	/* return success or time-out error depending on time left */
-	if (!timeleft)
-		return MVSATA_STATUS_TIMEOUT;
-	return MVSATA_STATUS_OK;
-}
-
-/*
- * ide_preinit() will be called by ide_init in cmd_ide.c and will
- * reset the MVSTATHC ports needed by the board.
- */
-
-int ide_preinit(void)
-{
-	int ret = MVSATA_STATUS_TIMEOUT;
-	int status;
-
-#ifdef CONFIG_ARCH_MVEBU
-	mvsata_ide_conf_mbus_windows();
-#endif
-
-	/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
-#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
-	status = mvsata_ide_initialize_port(
-		(struct mvsata_port_registers *)
-		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
-	if (status == MVSATA_STATUS_OK)
-		ret = MVSATA_STATUS_OK;
-#endif
-	/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
-#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
-	status = mvsata_ide_initialize_port(
-		(struct mvsata_port_registers *)
-		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
-	if (status == MVSATA_STATUS_OK)
-		ret = MVSATA_STATUS_OK;
-#endif
-	/* Return success if at least one port initialization succeeded */
-	return ret;
-}
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
index ea8d28b5b536..8990efb3f68b 100644
--- a/include/configs/dns325.h
+++ b/include/configs/dns325.h
@@ -35,14 +35,6 @@
 #define CONFIG_MVGBE_PORTS		{1, 0} /* enable port 0 only */
 #endif
 
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
-#endif
-
 /*
  * Enable GPI0 support
  */
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
index 09bac0177902..9106203ebc46 100644
--- a/include/configs/dreamplug.h
+++ b/include/configs/dreamplug.h
@@ -52,11 +52,4 @@
 #define CONFIG_PHY_BASE_ADR	0
 #endif /* CONFIG_CMD_NET */
 
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
 #endif /* _CONFIG_DREAMPLUG_H */
diff --git a/include/configs/ds109.h b/include/configs/ds109.h
index 1f033ababf6e..ea563b04d1a8 100644
--- a/include/configs/ds109.h
+++ b/include/configs/ds109.h
@@ -54,11 +54,4 @@
 #define CONFIG_PHY_BASE_ADR	8
 #endif /* CONFIG_CMD_NET */
 
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
 #endif /* _CONFIG_DS109_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index dd16e3fbda43..949ff55624d6 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -122,9 +122,6 @@
  */
 #ifdef CONFIG_IDE
 #define __io
-#define CONFIG_IDE_PREINIT
-/* ED Mini V has an IDE-compatible SATA connector for port 1 */
-#define CONFIG_MVSATA_IDE_USE_PORT1
 /* Needs byte-swapping for ATA data register */
 #define CONFIG_IDE_SWAP_IO
 /* Data, registers and alternate blocks are at the same offset */
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index 51325047ecda..a18e7869b08f 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -72,11 +72,4 @@
 #define CONFIG_PHY_BASE_ADR	0
 #endif /* CONFIG_CMD_NET */
 
-/*
- *  * SATA Driver configuration
- *   */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
 #endif /* _CONFIG_GOFLEXHOME_H */
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 1e1e5da4d52f..8de888fe7e06 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -66,11 +66,4 @@
 #define CONFIG_PHY_BASE_ADR	0
 #endif /* CONFIG_CMD_NET */
 
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
 #endif /* _CONFIG_GURUPLUG_H */
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
index 41483a2f7e40..ba859a9a2499 100644
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -56,9 +56,6 @@
  */
 #ifdef CONFIG_IDE
 #define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT0
-#define CONFIG_MVSATA_IDE_USE_PORT1
 #define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
 #define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
 #endif /* CONFIG_IDE */
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
index b95c7fc3be77..1fd5471ac5ff 100644
--- a/include/configs/nas220.h
+++ b/include/configs/nas220.h
@@ -80,14 +80,6 @@
 #define CONFIG_JFFS2_NAND
 #define CONFIG_JFFS2_LZO
 
-/*
- * SATA
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
-#endif
-
 /*
  * EFI partition
  */
diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h
index 1cb0d68b5af2..e38c65a48583 100644
--- a/include/configs/nsa310s.h
+++ b/include/configs/nsa310s.h
@@ -48,8 +48,6 @@
 /* SATA driver configuration */
 #ifdef CONFIG_IDE
 #define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT0
 #define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
 #endif /* CONFIG_IDE */
 
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index e1f8fb8ac84b..bb11fd66c467 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -63,9 +63,6 @@
  */
 #ifdef CONFIG_IDE
 #define __io
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT0
-#define CONFIG_MVSATA_IDE_USE_PORT1
 #define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
 #define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
 #endif /* CONFIG_IDE */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c6a831249569..5e725f4dccec 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1096,8 +1096,6 @@ CONFIG_MVEBU_MMC
 CONFIG_MVGBE_PORTS
 CONFIG_MVMFP_V2
 CONFIG_MVS
-CONFIG_MVSATA_IDE_USE_PORT0
-CONFIG_MVSATA_IDE_USE_PORT1
 CONFIG_MV_ETH_RXQ
 CONFIG_MV_I2C_NUM
 CONFIG_MV_I2C_REG
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 15/16] drivers: ata: Remove mvsata_ide driver
  2021-02-10  2:42 ` [PATCH 15/16] drivers: ata: Remove mvsata_ide driver Tom Rini
@ 2021-04-12  0:25   ` Tom Rini
  0 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-04-12  0:25 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:56PM -0500, Tom Rini wrote:

> The mvsata_ide driver was due for DM conversion by v2019.07.  As that
> has long passed, remove the driver and disable it in the boards which
> had enabled it.
> 
> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

* [PATCH 16/16] ata: Make LIBATA means AHCI is enabled mandatory.
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (13 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 15/16] drivers: ata: Remove mvsata_ide driver Tom Rini
@ 2021-02-10  2:42 ` Tom Rini
  2021-04-12  0:24 ` [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
  15 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-02-10  2:42 UTC (permalink / raw)
  To: u-boot

The migration deadline for having LIBATA mean that AHCI is also enabled
was v2019.07.  As that has long since passed, adjust the Kconfig
dependencies.

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 Makefile            | 11 -----------
 drivers/ata/Kconfig |  6 ++++--
 2 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/Makefile b/Makefile
index 9d6ac5e16fe5..a71b66c8449a 100644
--- a/Makefile
+++ b/Makefile
@@ -1064,17 +1064,6 @@ ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
 	@echo >&2 "===================================================="
 endif
 endif
-ifeq ($(CONFIG_LIBATA),y)
-ifneq ($(CONFIG_AHCI),y)
-	@echo >&2 "===================== WARNING ======================"
-	@echo >&2 "This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
-	@echo >&2 "enabled. Please update the storage controller driver to use"
-	@echo >&2 "CONFIG_AHCI before the v2019.07 release."
-	@echo >&2 "Failure to update by the deadline may result in board removal."
-	@echo >&2 "See doc/driver-model/migration.rst for more info."
-	@echo >&2 "===================================================="
-endif
-endif
 ifeq ($(CONFIG_PCI),y)
 ifneq ($(CONFIG_DM_PCI),y)
 	@echo >&2 "===================== WARNING ======================"
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9ff4b8736c1f..5bbd76a3c70c 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -77,8 +77,9 @@ config DWC_AHSATA_AHCI
 
 config FSL_SATA
 	bool "Enable Freescale SATA controller driver support"
+	select AHCI
 	select LIBATA
-	select AHCI if BLK
+	depends on BLK
 	help
 	  Enable this driver to support the SATA controller found in
 	  some Freescale PowerPC SoCs.
@@ -94,8 +95,9 @@ config SATA_MV
 
 config SATA_SIL
 	bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver support"
+	select AHCI
 	select LIBATA
-	select AHCI if BLK
+	depends on BLK
 	help
 	  Enable this driver to support the SIL3131, SIL3132 and SIL3124
 	  SATA controllers.
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 38+ messages in thread

* [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI
  2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
                   ` (14 preceding siblings ...)
  2021-02-10  2:42 ` [PATCH 16/16] ata: Make LIBATA means AHCI is enabled mandatory Tom Rini
@ 2021-04-12  0:24 ` Tom Rini
  15 siblings, 0 replies; 38+ messages in thread
From: Tom Rini @ 2021-04-12  0:24 UTC (permalink / raw)
  To: u-boot

On Tue, Feb 09, 2021 at 09:42:42PM -0500, Tom Rini wrote:

> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 38+ messages in thread

end of thread, other threads:[~2021-04-12  0:25 UTC | newest]

Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-10  2:42 [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini
2021-02-10  2:42 ` [PATCH 02/16] am57xx_hs_evm_usb: Enable AHCI and BLK Tom Rini
2021-04-12  0:24   ` Tom Rini
2021-02-10  2:42 ` [PATCH 03/16] ata: DWC_AHSATA depends on BLK Tom Rini
2021-04-12  0:25   ` Tom Rini
2021-02-10  2:42 ` [PATCH 04/16] ppc: configs: Remove a few non-updated build configurations Tom Rini
2021-02-10  2:42 ` [PATCH 05/16] arm: Remove highbank board Tom Rini
2021-02-19 13:04   ` André Przywara
2021-02-19 13:30     ` Tom Rini
2021-02-10  2:42 ` [PATCH 06/16] arm: Remove dms-ba16 board Tom Rini
2021-04-12  0:25   ` Tom Rini
2021-02-10  2:42 ` [PATCH 07/16] arm: Remove ot1200 board Tom Rini
2021-02-17  9:58   ` Christian Gmeiner
2021-03-01 14:47     ` Christian Gmeiner
2021-04-12  0:25   ` Tom Rini
2021-02-10  2:42 ` [PATCH 08/16] arm: Remove mx53loco board Tom Rini
2021-02-13 14:14   ` Fabio Estevam
2021-02-13 16:14     ` Tom Rini
2021-02-14  1:53     ` Fabio Estevam
2021-02-10  2:42 ` [PATCH 09/16] ppc: Remove MPC8349ITX board Tom Rini
2021-04-12  0:25   ` Tom Rini
2021-02-10  2:42 ` [PATCH 10/16] ppc: Remove MPC8544DS board Tom Rini
2021-02-11 10:34   ` Priyanka Jain
2021-02-15 15:44   ` Tom Rini
2021-02-10  2:42 ` [PATCH 11/16] ppc: Remove MPC8572DS board Tom Rini
2021-02-11 10:34   ` Priyanka Jain
2021-02-15 15:44   ` Tom Rini
2021-02-10  2:42 ` [PATCH 12/16] ppc: Remove MPC8610HPCD board Tom Rini
2021-02-11 10:33   ` Priyanka Jain
2021-02-15 15:44   ` Tom Rini
2021-02-10  2:42 ` [PATCH 13/16] ppc: Remove MPC8641HPCN board Tom Rini
2021-02-11 10:33   ` Priyanka Jain
2021-02-15 15:44   ` Tom Rini
2021-02-10  2:42 ` [PATCH 14/16] boards: Disable CMD_SATA on platforms that no longer have a SATA driver enabled Tom Rini
2021-02-10  2:42 ` [PATCH 15/16] drivers: ata: Remove mvsata_ide driver Tom Rini
2021-04-12  0:25   ` Tom Rini
2021-02-10  2:42 ` [PATCH 16/16] ata: Make LIBATA means AHCI is enabled mandatory Tom Rini
2021-04-12  0:24 ` [PATCH 01/16] ls1012aqds_tfa_SECURE_BOOT: Remove unused CONFIG_SCSI_AHCI Tom Rini

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