* [PATCH] target/riscv: fix exception index on instruction access fault
@ 2021-04-13 16:30 Emmanuel Blot
2021-04-14 3:42 ` Palmer Dabbelt
0 siblings, 1 reply; 5+ messages in thread
From: Emmanuel Blot @ 2021-04-13 16:30 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-riscv, Emmanuel Blot
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
---
target/riscv/cpu_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 21c54ef5613..4e107b1bd23 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -691,8 +691,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
if (access_type == MMU_DATA_STORE) {
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
- } else {
+ } else if (access_type == MMU_DATA_LOAD) {
cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+ } else {
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
}
env->badaddr = addr;
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] target/riscv: fix exception index on instruction access fault
2021-04-13 16:30 [PATCH] target/riscv: fix exception index on instruction access fault Emmanuel Blot
@ 2021-04-14 3:42 ` Palmer Dabbelt
0 siblings, 0 replies; 5+ messages in thread
From: Palmer Dabbelt @ 2021-04-14 3:42 UTC (permalink / raw)
To: emmanuel.blot; +Cc: Alistair Francis, qemu-riscv, emmanuel.blot
On Tue, 13 Apr 2021 09:30:00 PDT (-0700), emmanuel.blot@sifive.com wrote:
> When no MMU is used and the guest code attempts to fetch an instruction
> from an invalid memory location, the exception index defaults to a data
> load access fault, rather an instruction access fault.
> ---
> target/riscv/cpu_helper.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 21c54ef5613..4e107b1bd23 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -691,8 +691,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
>
> if (access_type == MMU_DATA_STORE) {
> cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> - } else {
> + } else if (access_type == MMU_DATA_LOAD) {
> cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
> + } else {
> + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
> }
>
> env->badaddr = addr;
You need a Signed-off-by, but otherwise
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Thanks!
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] target/riscv: fix exception index on instruction access fault
2021-04-20 0:56 ` Alistair Francis
@ 2021-04-20 3:06 ` Alistair Francis
0 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2021-04-20 3:06 UTC (permalink / raw)
To: Emmanuel Blot; +Cc: Alistair Francis, qemu-devel@nongnu.org Developers
On Tue, Apr 20, 2021 at 10:56 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Sat, Apr 17, 2021 at 12:48 AM Emmanuel Blot <emmanuel.blot@sifive.com> wrote:
> >
> > When no MMU is used and the guest code attempts to fetch an instruction
> > from an invalid memory location, the exception index defaults to a data
> > load access fault, rather an instruction access fault.
> >
> > Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> Alistair
>
> >
> > ---
> > target/riscv/cpu_helper.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 21c54ef5613..4e107b1bd23 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -691,8 +691,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs,
> > hwaddr physaddr,
> >
> > if (access_type == MMU_DATA_STORE) {
> > cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> > - } else {
> > + } else if (access_type == MMU_DATA_LOAD) {
> > cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
> > + } else {
> > + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
> > }
> >
> > env->badaddr = addr;
> > --
> > 2.31.1
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] target/riscv: fix exception index on instruction access fault
2021-04-16 14:17 ` [PATCH] target/riscv: fix exception index on instruction access fault Emmanuel Blot
@ 2021-04-20 0:56 ` Alistair Francis
2021-04-20 3:06 ` Alistair Francis
0 siblings, 1 reply; 5+ messages in thread
From: Alistair Francis @ 2021-04-20 0:56 UTC (permalink / raw)
To: Emmanuel Blot; +Cc: Alistair Francis, qemu-devel@nongnu.org Developers
On Sat, Apr 17, 2021 at 12:48 AM Emmanuel Blot <emmanuel.blot@sifive.com> wrote:
>
> When no MMU is used and the guest code attempts to fetch an instruction
> from an invalid memory location, the exception index defaults to a data
> load access fault, rather an instruction access fault.
>
> Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
> target/riscv/cpu_helper.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 21c54ef5613..4e107b1bd23 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -691,8 +691,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs,
> hwaddr physaddr,
>
> if (access_type == MMU_DATA_STORE) {
> cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> - } else {
> + } else if (access_type == MMU_DATA_LOAD) {
> cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
> + } else {
> + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
> }
>
> env->badaddr = addr;
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] target/riscv: fix exception index on instruction access fault
2021-04-15 13:41 Emmanuel Blot
@ 2021-04-16 14:17 ` Emmanuel Blot
2021-04-20 0:56 ` Alistair Francis
0 siblings, 1 reply; 5+ messages in thread
From: Emmanuel Blot @ 2021-04-16 14:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
---
target/riscv/cpu_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 21c54ef5613..4e107b1bd23 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -691,8 +691,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs,
hwaddr physaddr,
if (access_type == MMU_DATA_STORE) {
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
- } else {
+ } else if (access_type == MMU_DATA_LOAD) {
cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+ } else {
+ cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
}
env->badaddr = addr;
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-04-20 3:07 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2021-04-13 16:30 [PATCH] target/riscv: fix exception index on instruction access fault Emmanuel Blot
2021-04-14 3:42 ` Palmer Dabbelt
2021-04-15 13:41 Emmanuel Blot
2021-04-16 14:17 ` [PATCH] target/riscv: fix exception index on instruction access fault Emmanuel Blot
2021-04-20 0:56 ` Alistair Francis
2021-04-20 3:06 ` Alistair Francis
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