* [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
@ 2021-04-16 7:51 ` Zev Weiss
0 siblings, 0 replies; 9+ messages in thread
From: Zev Weiss @ 2021-04-16 7:51 UTC (permalink / raw)
To: Joel Stanley
Cc: openbmc, Zev Weiss, Rob Herring, Andrew Jeffery, devicetree,
linux-arm-kernel, linux-aspeed, linux-kernel
This device-tree was merged with a provisional vuart IRQ-polarity
property that was still under review and ended up taking a somewhat
different form. This patch updates it to match the final form of the
new vuart properties, which additionally allow specifying the SIRQ
number and LPC address.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
The relevant aspeed-vuart patches [0] have been merged into Greg KH's
tty-next tree, so I figure it's probably okay to proceed with the
corresponding dts adjustments now.
[0] https://lore.kernel.org/openbmc/20210412034712.16778-1-zev@bewilderbeest.net/
arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
index dcab6e78dfa4..8be40c8283af 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
@@ -4,6 +4,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/{
model = "ASRock E3C246D4I BMC";
@@ -73,7 +74,8 @@ &uart5 {
&vuart {
status = "okay";
- aspeed,sirq-active-high;
+ aspeed,lpc-io-reg = <0x2f8>;
+ aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
&mac0 {
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
@ 2021-04-16 7:51 ` Zev Weiss
0 siblings, 0 replies; 9+ messages in thread
From: Zev Weiss @ 2021-04-16 7:51 UTC (permalink / raw)
To: Joel Stanley
Cc: devicetree, linux-aspeed, Zev Weiss, Andrew Jeffery, openbmc,
linux-kernel, Rob Herring, linux-arm-kernel
This device-tree was merged with a provisional vuart IRQ-polarity
property that was still under review and ended up taking a somewhat
different form. This patch updates it to match the final form of the
new vuart properties, which additionally allow specifying the SIRQ
number and LPC address.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
The relevant aspeed-vuart patches [0] have been merged into Greg KH's
tty-next tree, so I figure it's probably okay to proceed with the
corresponding dts adjustments now.
[0] https://lore.kernel.org/openbmc/20210412034712.16778-1-zev@bewilderbeest.net/
arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
index dcab6e78dfa4..8be40c8283af 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
@@ -4,6 +4,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/{
model = "ASRock E3C246D4I BMC";
@@ -73,7 +74,8 @@ &uart5 {
&vuart {
status = "okay";
- aspeed,sirq-active-high;
+ aspeed,lpc-io-reg = <0x2f8>;
+ aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
&mac0 {
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
2021-04-16 7:51 ` Zev Weiss
(?)
@ 2021-04-27 3:59 ` Andrew Jeffery
-1 siblings, 0 replies; 9+ messages in thread
From: Andrew Jeffery @ 2021-04-27 3:59 UTC (permalink / raw)
To: Zev Weiss, Joel Stanley
Cc: openbmc, Rob Herring, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
On Fri, 16 Apr 2021, at 17:21, Zev Weiss wrote:
> This device-tree was merged with a provisional vuart IRQ-polarity
> property that was still under review and ended up taking a somewhat
> different form. This patch updates it to match the final form of the
> new vuart properties, which additionally allow specifying the SIRQ
> number and LPC address.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
@ 2021-04-27 3:59 ` Andrew Jeffery
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jeffery @ 2021-04-27 3:59 UTC (permalink / raw)
To: Zev Weiss, Joel Stanley
Cc: openbmc, Rob Herring, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
On Fri, 16 Apr 2021, at 17:21, Zev Weiss wrote:
> This device-tree was merged with a provisional vuart IRQ-polarity
> property that was still under review and ended up taking a somewhat
> different form. This patch updates it to match the final form of the
> new vuart properties, which additionally allow specifying the SIRQ
> number and LPC address.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
@ 2021-04-27 3:59 ` Andrew Jeffery
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jeffery @ 2021-04-27 3:59 UTC (permalink / raw)
To: Zev Weiss, Joel Stanley
Cc: devicetree, linux-aspeed, openbmc, linux-kernel, Rob Herring,
linux-arm-kernel
On Fri, 16 Apr 2021, at 17:21, Zev Weiss wrote:
> This device-tree was merged with a provisional vuart IRQ-polarity
> property that was still under review and ended up taking a somewhat
> different form. This patch updates it to match the final form of the
> new vuart properties, which additionally allow specifying the SIRQ
> number and LPC address.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
2021-04-16 7:51 ` Zev Weiss
(?)
@ 2021-07-01 3:12 ` Joel Stanley
-1 siblings, 0 replies; 9+ messages in thread
From: Joel Stanley @ 2021-07-01 3:12 UTC (permalink / raw)
To: Zev Weiss
Cc: OpenBMC Maillist, Rob Herring, Andrew Jeffery, devicetree,
Linux ARM, linux-aspeed, Linux Kernel Mailing List
On Fri, 16 Apr 2021 at 07:52, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> This device-tree was merged with a provisional vuart IRQ-polarity
> property that was still under review and ended up taking a somewhat
> different form. This patch updates it to match the final form of the
> new vuart properties, which additionally allow specifying the SIRQ
> number and LPC address.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: ca03042f0f12 ("serial: 8250_aspeed_vuart: add aspeed,
lpc-io-reg and aspeed, lpc-interrupts DT properties")
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
>
> The relevant aspeed-vuart patches [0] have been merged into Greg KH's
> tty-next tree, so I figure it's probably okay to proceed with the
> corresponding dts adjustments now.
>
> [0] https://lore.kernel.org/openbmc/20210412034712.16778-1-zev@bewilderbeest.net/
>
> arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> index dcab6e78dfa4..8be40c8283af 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> @@ -4,6 +4,7 @@
> #include "aspeed-g5.dtsi"
> #include <dt-bindings/gpio/aspeed-gpio.h>
> #include <dt-bindings/i2c/i2c.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
>
> /{
> model = "ASRock E3C246D4I BMC";
> @@ -73,7 +74,8 @@ &uart5 {
>
> &vuart {
> status = "okay";
> - aspeed,sirq-active-high;
> + aspeed,lpc-io-reg = <0x2f8>;
> + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> &mac0 {
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
@ 2021-07-01 3:12 ` Joel Stanley
0 siblings, 0 replies; 9+ messages in thread
From: Joel Stanley @ 2021-07-01 3:12 UTC (permalink / raw)
To: Zev Weiss
Cc: OpenBMC Maillist, Rob Herring, Andrew Jeffery, devicetree,
Linux ARM, linux-aspeed, Linux Kernel Mailing List
On Fri, 16 Apr 2021 at 07:52, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> This device-tree was merged with a provisional vuart IRQ-polarity
> property that was still under review and ended up taking a somewhat
> different form. This patch updates it to match the final form of the
> new vuart properties, which additionally allow specifying the SIRQ
> number and LPC address.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: ca03042f0f12 ("serial: 8250_aspeed_vuart: add aspeed,
lpc-io-reg and aspeed, lpc-interrupts DT properties")
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
>
> The relevant aspeed-vuart patches [0] have been merged into Greg KH's
> tty-next tree, so I figure it's probably okay to proceed with the
> corresponding dts adjustments now.
>
> [0] https://lore.kernel.org/openbmc/20210412034712.16778-1-zev@bewilderbeest.net/
>
> arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> index dcab6e78dfa4..8be40c8283af 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> @@ -4,6 +4,7 @@
> #include "aspeed-g5.dtsi"
> #include <dt-bindings/gpio/aspeed-gpio.h>
> #include <dt-bindings/i2c/i2c.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
>
> /{
> model = "ASRock E3C246D4I BMC";
> @@ -73,7 +74,8 @@ &uart5 {
>
> &vuart {
> status = "okay";
> - aspeed,sirq-active-high;
> + aspeed,lpc-io-reg = <0x2f8>;
> + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> &mac0 {
> --
> 2.31.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] ARM: dts: aspeed: update e3c246d4i vuart properties
@ 2021-07-01 3:12 ` Joel Stanley
0 siblings, 0 replies; 9+ messages in thread
From: Joel Stanley @ 2021-07-01 3:12 UTC (permalink / raw)
To: Zev Weiss
Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist,
Linux Kernel Mailing List, Rob Herring, Linux ARM
On Fri, 16 Apr 2021 at 07:52, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> This device-tree was merged with a provisional vuart IRQ-polarity
> property that was still under review and ended up taking a somewhat
> different form. This patch updates it to match the final form of the
> new vuart properties, which additionally allow specifying the SIRQ
> number and LPC address.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: ca03042f0f12 ("serial: 8250_aspeed_vuart: add aspeed,
lpc-io-reg and aspeed, lpc-interrupts DT properties")
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
>
> The relevant aspeed-vuart patches [0] have been merged into Greg KH's
> tty-next tree, so I figure it's probably okay to proceed with the
> corresponding dts adjustments now.
>
> [0] https://lore.kernel.org/openbmc/20210412034712.16778-1-zev@bewilderbeest.net/
>
> arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> index dcab6e78dfa4..8be40c8283af 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> @@ -4,6 +4,7 @@
> #include "aspeed-g5.dtsi"
> #include <dt-bindings/gpio/aspeed-gpio.h>
> #include <dt-bindings/i2c/i2c.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
>
> /{
> model = "ASRock E3C246D4I BMC";
> @@ -73,7 +74,8 @@ &uart5 {
>
> &vuart {
> status = "okay";
> - aspeed,sirq-active-high;
> + aspeed,lpc-io-reg = <0x2f8>;
> + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> &mac0 {
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread