* [Intel-gfx] [PATCH 1/8] drm/i915: Collect dbuf device info into a sub-struct
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 2/8] drm/i915: Handle dbuf bypass path allocation earlier Ville Syrjala
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Collect the related dbuf information into a struct.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 16 ++++++++--------
drivers/gpu/drm/i915/intel_device_info.h | 6 ++++--
drivers/gpu/drm/i915/intel_pm.c | 14 +++++++-------
4 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0af1dee1ac95..0e433a0e1fce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+ int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
struct i915_power_domains *power_domains = &dev_priv->power_domains;
enum dbuf_slice slice;
@@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
{
- const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+ int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
enum dbuf_slice slice;
for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e7b94db63d..484d2633894a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -647,8 +647,8 @@ static const struct intel_device_info chv_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .ddb_size = 896, \
- .num_supported_dbuf_slices = 1
+ .dbuf.size = 896, \
+ .dbuf.num_slices = 1
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
- .num_supported_dbuf_slices = 1, \
+ .dbuf.num_slices = 1, \
.display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = {
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
- .ddb_size = 512,
+ .dbuf.size = 512,
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
.display.ver = 10,
- .ddb_size = 1024,
+ .dbuf.size = 1024,
GLK_COLORS,
};
@@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = {
#define GEN10_FEATURES \
GEN9_FEATURES, \
GEN(10), \
- .ddb_size = 1024, \
+ .dbuf.size = 1024, \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
@@ -830,8 +830,8 @@ static const struct intel_device_info cnl_info = {
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
GEN(11), \
- .ddb_size = 2048, \
- .num_supported_dbuf_slices = 2, \
+ .dbuf.size = 2048, \
+ .dbuf.num_slices = 2, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8ab4fa6c7fdd..74591e4f9c44 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -196,8 +196,10 @@ struct intel_device_info {
#undef DEFINE_FLAG
} display;
- u16 ddb_size; /* in blocks */
- u8 num_supported_dbuf_slices; /* number of DBuf slices */
+ struct {
+ u16 size; /* in blocks */
+ u8 num_slices;
+ } dbuf;
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eaf4c072ade0..ced1eb32cb78 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3637,10 +3637,10 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{
int i;
- int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+ int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
u8 enabled_slices_mask = 0;
- for (i = 0; i < max_slices; i++) {
+ for (i = 0; i < num_slices; i++) {
if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
enabled_slices_mask |= BIT(i);
}
@@ -4030,7 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
static int intel_dbuf_size(struct drm_i915_private *dev_priv)
{
- int ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+ int ddb_size = INTEL_INFO(dev_priv)->dbuf.size;
drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
@@ -4043,7 +4043,7 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv)
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
{
return intel_dbuf_size(dev_priv) /
- INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+ INTEL_INFO(dev_priv)->dbuf.num_slices;
}
static void
@@ -4070,8 +4070,8 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
{
u32 slice_mask = 0;
u16 ddb_size = intel_dbuf_size(dev_priv);
- u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
- u16 slice_size = ddb_size / num_supported_slices;
+ int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ u16 slice_size = ddb_size / num_slices;
u16 start_slice;
u16 end_slice;
@@ -5828,7 +5828,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
"Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
+ INTEL_INFO(dev_priv)->dbuf.num_slices);
}
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
--
2.26.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915: Handle dbuf bypass path allocation earlier
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 1/8] drm/i915: Collect dbuf device info into a sub-struct Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 3/8] drm/i915: Store dbuf slice mask in device info Ville Syrjala
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We always reserve the same 4 dbuf blocks for the bypass path
allocation, so might as well do that when declaring the dbuf
size.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 8 ++++----
drivers/gpu/drm/i915/intel_pm.c | 9 +--------
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 484d2633894a..981d12702c49 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -647,7 +647,7 @@ static const struct intel_device_info chv_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .dbuf.size = 896, \
+ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.num_slices = 1
#define SKL_PLATFORM \
@@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = {
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
- .dbuf.size = 512,
+ .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ \
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
.display.ver = 10,
- .dbuf.size = 1024,
+ .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
GLK_COLORS,
};
@@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = {
#define GEN10_FEATURES \
GEN9_FEATURES, \
GEN(10), \
- .dbuf.size = 1024, \
+ .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ced1eb32cb78..8d6ee5ad761e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4030,14 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
static int intel_dbuf_size(struct drm_i915_private *dev_priv)
{
- int ddb_size = INTEL_INFO(dev_priv)->dbuf.size;
-
- drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
-
- if (DISPLAY_VER(dev_priv) < 11)
- return ddb_size - 4; /* 4 blocks for bypass path allocation */
-
- return ddb_size;
+ return INTEL_INFO(dev_priv)->dbuf.size;
}
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
--
2.26.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915: Store dbuf slice mask in device info
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 1/8] drm/i915: Collect dbuf device info into a sub-struct Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 2/8] drm/i915: Handle dbuf bypass path allocation earlier Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 4/8] drm/i915: Use intel_dbuf_slice_size() Ville Syrjala
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's just store the dbuf slice information as a bitmask
in the device info. Makes life a little easier later.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 6 +++---
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++----
drivers/gpu/drm/i915/intel_pm.h | 1 +
5 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0e433a0e1fce..0435103082eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
struct i915_power_domains *power_domains = &dev_priv->power_domains;
enum dbuf_slice slice;
@@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
{
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
enum dbuf_slice slice;
for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 981d12702c49..15eb078fe6bb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -648,7 +648,7 @@ static const struct intel_device_info chv_info = {
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
- .dbuf.num_slices = 1
+ .dbuf.slice_mask = BIT(DBUF_S1)
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
- .dbuf.num_slices = 1, \
+ .dbuf.slice_mask = BIT(DBUF_S1), \
.display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -831,7 +831,7 @@ static const struct intel_device_info cnl_info = {
}, \
GEN(11), \
.dbuf.size = 2048, \
- .dbuf.num_slices = 2, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 74591e4f9c44..6aefe4fde197 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -198,7 +198,7 @@ struct intel_device_info {
struct {
u16 size; /* in blocks */
- u8 num_slices;
+ u8 slice_mask;
} dbuf;
/* Register offsets for the various display pipes and transcoders */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8d6ee5ad761e..88eb54241b9f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3637,7 +3637,7 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{
int i;
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
u8 enabled_slices_mask = 0;
for (i = 0; i < num_slices; i++) {
@@ -4033,10 +4033,15 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv)
return INTEL_INFO(dev_priv)->dbuf.size;
}
+int intel_dbuf_num_slices(struct drm_i915_private *dev_priv)
+{
+ return hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
+}
+
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
{
return intel_dbuf_size(dev_priv) /
- INTEL_INFO(dev_priv)->dbuf.num_slices;
+ intel_dbuf_num_slices(dev_priv);
}
static void
@@ -4063,7 +4068,7 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
{
u32 slice_mask = 0;
u16 ddb_size = intel_dbuf_size(dev_priv);
- int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices;
+ int num_slices = intel_dbuf_num_slices(dev_priv);
u16 slice_size = ddb_size / num_slices;
u16 start_slice;
u16 end_slice;
@@ -5821,7 +5826,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
"Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- INTEL_INFO(dev_priv)->dbuf.num_slices);
+ intel_dbuf_num_slices(dev_priv));
}
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 669c8d505677..7dc11dec8984 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -38,6 +38,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
+int intel_dbuf_num_slices(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
--
2.26.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915: Use intel_dbuf_slice_size()
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (2 preceding siblings ...)
2021-04-16 17:10 ` [Intel-gfx] [PATCH 3/8] drm/i915: Store dbuf slice mask in device info Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 5/8] drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST Ville Syrjala
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use intel_dbuf_slice_size() instead of hand rolling it.
Also clean up some of the types.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88eb54241b9f..38e2ba45bfd8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4066,12 +4066,9 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
const struct skl_ddb_entry *entry)
{
- u32 slice_mask = 0;
- u16 ddb_size = intel_dbuf_size(dev_priv);
- int num_slices = intel_dbuf_num_slices(dev_priv);
- u16 slice_size = ddb_size / num_slices;
- u16 start_slice;
- u16 end_slice;
+ int slice_size = intel_dbuf_slice_size(dev_priv);
+ enum dbuf_slice start_slice, end_slice;
+ u8 slice_mask = 0;
if (!skl_ddb_entry_size(entry))
return 0;
--
2.26.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 5/8] drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (3 preceding siblings ...)
2021-04-16 17:10 ` [Intel-gfx] [PATCH 4/8] drm/i915: Use intel_dbuf_slice_size() Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 6/8] drm/i915: Polish for_each_dbuf_slice() Ville Syrjala
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use intel_de_rmw() instead of hand rolling it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0435103082eb..528fbede0ee7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4757,14 +4757,9 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
{
i915_reg_t reg = DBUF_CTL_S(slice);
bool state;
- u32 val;
- val = intel_de_read(dev_priv, reg);
- if (enable)
- val |= DBUF_POWER_REQUEST;
- else
- val &= ~DBUF_POWER_REQUEST;
- intel_de_write(dev_priv, reg, val);
+ intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST,
+ enable ? DBUF_POWER_REQUEST : 0);
intel_de_posting_read(dev_priv, reg);
udelay(10);
--
2.26.3
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915: Polish for_each_dbuf_slice()
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (4 preceding siblings ...)
2021-04-16 17:10 ` [Intel-gfx] [PATCH 5/8] drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 7/8] drm/i915: Add enabledisable() Ville Syrjala
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that we have the dbuf slice mask stored in the device info
let's use it for for_each_dbuf_slice_in_mask*().
With this we cal also rip out intel_dbuf_size() and
intel_dbuf_num_slices().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 11 +++---
drivers/gpu/drm/i915/display/intel_display.h | 9 ++---
.../drm/i915/display/intel_display_power.c | 13 ++++---
drivers/gpu/drm/i915/intel_pm.c | 34 +++++++------------
4 files changed, 29 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 20dbc3759d27..969169743630 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -390,7 +390,6 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
const struct intel_crtc_state *crtc_state;
struct intel_crtc *crtc;
int max_bw = 0;
- int slice_id;
enum pipe pipe;
int i;
@@ -418,6 +417,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
unsigned int data_rate = crtc_state->data_rate[plane_id];
unsigned int dbuf_mask = 0;
+ enum dbuf_slice slice;
dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc);
dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);
@@ -435,8 +435,8 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
* pessimistic, which shouldn't pose any significant
* problem anyway.
*/
- for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
- crtc_bw->used_bw[slice_id] += data_rate;
+ for_each_dbuf_slice_in_mask(dev_priv, slice, dbuf_mask)
+ crtc_bw->used_bw[slice] += data_rate;
}
}
@@ -445,10 +445,11 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
for_each_pipe(dev_priv, pipe) {
struct intel_dbuf_bw *crtc_bw;
+ enum dbuf_slice slice;
crtc_bw = &new_bw_state->dbuf_bw[pipe];
- for_each_dbuf_slice(slice_id) {
+ for_each_dbuf_slice(dev_priv, slice) {
/*
* Current experimental observations show that contrary
* to BSpec we get underruns once we exceed 64 * CDCLK
@@ -457,7 +458,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
* bumped up all the time we calculate CDCLK according
* to this formula for overall bw consumed by slices.
*/
- max_bw += crtc_bw->used_bw[slice_id];
+ max_bw += crtc_bw->used_bw[slice];
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 105294ec2dcc..b68bcd502206 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -188,12 +188,13 @@ enum plane_id {
for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
-#define for_each_dbuf_slice_in_mask(__slice, __mask) \
+#define for_each_dbuf_slice(__dev_priv, __slice) \
for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
- for_each_if((BIT(__slice)) & (__mask))
+ for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
-#define for_each_dbuf_slice(__slice) \
- for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1)
+#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
+ for_each_dbuf_slice((__dev_priv), (__slice)) \
+ for_each_if((__mask) & BIT(__slice))
enum port {
PORT_NONE = -1,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 528fbede0ee7..0fb4864a191a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4772,13 +4772,13 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- int num_slices = intel_dbuf_num_slices(dev_priv);
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ u8 slice_mask = INTEL_INFO(dev_priv)->dbuf.slice_mask;
enum dbuf_slice slice;
- drm_WARN(&dev_priv->drm, req_slices & ~(BIT(num_slices) - 1),
- "Invalid set of dbuf slices (0x%x) requested (num dbuf slices %d)\n",
- req_slices, num_slices);
+ drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
+ "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n",
+ req_slices, slice_mask);
drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n",
req_slices);
@@ -4792,7 +4792,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
*/
mutex_lock(&power_domains->lock);
- for (slice = DBUF_S1; slice < num_slices; slice++)
+ for_each_dbuf_slice(dev_priv, slice)
gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
dev_priv->dbuf.enabled_slices = req_slices;
@@ -4820,10 +4820,9 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
{
- int num_slices = intel_dbuf_num_slices(dev_priv);
enum dbuf_slice slice;
- for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)
+ for_each_dbuf_slice(dev_priv, slice)
intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
DBUF_TRACKER_STATE_SERVICE_MASK,
DBUF_TRACKER_STATE_SERVICE(8));
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 38e2ba45bfd8..155f41ed9dee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3636,16 +3636,16 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{
- int i;
- int num_slices = intel_dbuf_num_slices(dev_priv);
- u8 enabled_slices_mask = 0;
+ u8 enabled_slices = 0;
+ enum dbuf_slice slice;
- for (i = 0; i < num_slices; i++) {
- if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE)
- enabled_slices_mask |= BIT(i);
+ for_each_dbuf_slice(dev_priv, slice) {
+ if (intel_uncore_read(&dev_priv->uncore,
+ DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
+ enabled_slices |= BIT(slice);
}
- return enabled_slices_mask;
+ return enabled_slices;
}
/*
@@ -4028,20 +4028,10 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
return 0;
}
-static int intel_dbuf_size(struct drm_i915_private *dev_priv)
-{
- return INTEL_INFO(dev_priv)->dbuf.size;
-}
-
-int intel_dbuf_num_slices(struct drm_i915_private *dev_priv)
-{
- return hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
-}
-
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
{
- return intel_dbuf_size(dev_priv) /
- intel_dbuf_num_slices(dev_priv);
+ return INTEL_INFO(dev_priv)->dbuf.size /
+ hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
}
static void
@@ -4060,7 +4050,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
ddb->end = fls(slice_mask) * slice_size;
WARN_ON(ddb->start >= ddb->end);
- WARN_ON(ddb->end > intel_dbuf_size(dev_priv));
+ WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
}
u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
@@ -5820,10 +5810,10 @@ skl_compute_ddb(struct intel_atomic_state *state)
return ret;
drm_dbg_kms(&dev_priv->drm,
- "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
+ "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x)\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- intel_dbuf_num_slices(dev_priv));
+ INTEL_INFO(dev_priv)->dbuf.slice_mask);
}
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
--
2.26.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915: Add enabledisable()
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (5 preceding siblings ...)
2021-04-16 17:10 ` [Intel-gfx] [PATCH 6/8] drm/i915: Polish for_each_dbuf_slice() Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 8/8] drm/i915: Say "enable foo" instead of "set foo to enabled" Ville Syrjala
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
'enable ? "enable" : "disable"' is a fairly common pattern in
out debug prints. Let's introduce a helper for it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
drivers/gpu/drm/i915/i915_utils.h | 5 +++++
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4ef573883412..f4249f087fa7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2334,8 +2334,8 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
drm_dbg_kms(&i915->drm,
- "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
- enable ? "enable" : "disable");
+ "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
+ enabledisable(enable));
}
static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0fb4864a191a..d48dd15a4f6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4766,7 +4766,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
drm_WARN(&dev_priv->drm, enable != state,
"DBuf slice %d power %s timeout!\n",
- slice, enable ? "enable" : "disable");
+ slice, enabledisable(enable));
}
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5ee953aaa00c..44109a4b69aa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1861,7 +1861,7 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
if (ret < 0)
drm_dbg_kms(&i915->drm,
"Failed to %s sink decompression state\n",
- enable ? "enable" : "disable");
+ enabledisable(enable));
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 4f8337c7fd2e..8e9ac9ba1d38 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -291,7 +291,7 @@ static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
reg_val) != 1) {
drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enable ? "enable" : "disable");
+ enabledisable(enable));
}
}
diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h
index abd4dcd9f79c..f02f52ab5070 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -418,6 +418,11 @@ static inline const char *onoff(bool v)
return v ? "on" : "off";
}
+static inline const char *enabledisable(bool v)
+{
+ return v ? "enable" : "disable";
+}
+
static inline const char *enableddisabled(bool v)
{
return v ? "enabled" : "disabled";
--
2.26.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915: Say "enable foo" instead of "set foo to enabled"
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (6 preceding siblings ...)
2021-04-16 17:10 ` [Intel-gfx] [PATCH 7/8] drm/i915: Add enabledisable() Ville Syrjala
@ 2021-04-16 17:10 ` Ville Syrjala
2021-04-16 17:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: dbuf cleanups Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2021-04-16 17:10 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use simpler sentences. Just say "enable foo" instead
of "set foo to enabled" etc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_tc.c | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 44109a4b69aa..52ea09fc5e70 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2293,8 +2293,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
- drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
- enableddisabled(intel_dp->has_hdmi_sink));
+ drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
+ enabledisable(intel_dp->has_hdmi_sink));
tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
@@ -2302,8 +2302,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
drm_dbg_kms(&i915->drm,
- "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
- enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
+ "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
+ enabledisable(intel_dp->dfp.ycbcr_444_to_420));
tmp = 0;
if (intel_dp->dfp.rgb_to_ycbcr) {
@@ -2340,8 +2340,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
drm_dbg_kms(&i915->drm,
- "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
- enableddisabled(tmp ? true : false));
+ "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
+ enabledisable(tmp));
}
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 88085486ee59..59de6ca436db 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -267,8 +267,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
if (val == 0xffffffff) {
drm_dbg_kms(&i915->drm,
- "Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
- dig_port->tc_port_name, enableddisabled(enable));
+ "Port %s: PHY in TCCOLD, can't %s safe-mode\n",
+ dig_port->tc_port_name, enabledisable(enable));
return false;
}
--
2.26.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: dbuf cleanups
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (7 preceding siblings ...)
2021-04-16 17:10 ` [Intel-gfx] [PATCH 8/8] drm/i915: Say "enable foo" instead of "set foo to enabled" Ville Syrjala
@ 2021-04-16 17:25 ` Patchwork
2021-04-16 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-04-16 17:25 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: dbuf cleanups
URL : https://patchwork.freedesktop.org/series/89171/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c4e158b6022a drm/i915: Collect dbuf device info into a sub-struct
3bcf75a562a4 drm/i915: Handle dbuf bypass path allocation earlier
-:33: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#33: FILE: drivers/gpu/drm/i915/i915_pci.c:723:
+ .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ \
-:41: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#41: FILE: drivers/gpu/drm/i915/i915_pci.c:730:
+ .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
total: 0 errors, 2 warnings, 0 checks, 47 lines checked
6182af680aea drm/i915: Store dbuf slice mask in device info
4bec22613175 drm/i915: Use intel_dbuf_slice_size()
407ca0202e11 drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST
bbfbba08f9aa drm/i915: Polish for_each_dbuf_slice()
-:79: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__slice' - possible side-effects?
#79: FILE: drivers/gpu/drm/i915/display/intel_display.h:191:
+#define for_each_dbuf_slice(__dev_priv, __slice) \
for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
+ for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
-:86: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#86: FILE: drivers/gpu/drm/i915/display/intel_display.h:195:
+#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
+ for_each_dbuf_slice((__dev_priv), (__slice)) \
+ for_each_if((__mask) & BIT(__slice))
-:86: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__slice' - possible side-effects?
#86: FILE: drivers/gpu/drm/i915/display/intel_display.h:195:
+#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
+ for_each_dbuf_slice((__dev_priv), (__slice)) \
+ for_each_if((__mask) & BIT(__slice))
total: 1 errors, 0 warnings, 2 checks, 162 lines checked
b571b996abd4 drm/i915: Add enabledisable()
bb42f353dfe4 drm/i915: Say "enable foo" instead of "set foo to enabled"
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: dbuf cleanups
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (8 preceding siblings ...)
2021-04-16 17:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: dbuf cleanups Patchwork
@ 2021-04-16 17:26 ` Patchwork
2021-04-16 17:30 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-04-16 17:26 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: dbuf cleanups
URL : https://patchwork.freedesktop.org/series/89171/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: dbuf cleanups
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (9 preceding siblings ...)
2021-04-16 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-04-16 17:30 ` Patchwork
2021-04-16 17:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-04-16 17:30 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: dbuf cleanups
URL : https://patchwork.freedesktop.org/series/89171/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: dbuf cleanups
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (10 preceding siblings ...)
2021-04-16 17:30 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2021-04-16 17:51 ` Patchwork
2021-04-16 19:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-20 12:57 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-04-16 17:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2696 bytes --]
== Series Details ==
Series: drm/i915: dbuf cleanups
URL : https://patchwork.freedesktop.org/series/89171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9978 -> Patchwork_19944
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/index.html
Known issues
------------
Here are the changes found in Patchwork_19944 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160: [FAIL][1] ([i915#3194]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
* igt@i915_selftest@live@gt_timelines:
- fi-skl-6600u: [DMESG-WARN][3] -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/fi-skl-6600u/igt@i915_selftest@live@gt_timelines.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/fi-skl-6600u/igt@i915_selftest@live@gt_timelines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
Participating hosts (44 -> 41)
------------------------------
Missing (3): fi-icl-y fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9978 -> Patchwork_19944
CI-20190529: 20190529
CI_DRM_9978: 732dea807fffac8bed7696a335973c95f810e4b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6067: 14317b92a672d9a20cd04fc3b0c80e2fb12d51d5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19944: bb42f353dfe4f00c428649ce0ac736b6975bd237 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bb42f353dfe4 drm/i915: Say "enable foo" instead of "set foo to enabled"
b571b996abd4 drm/i915: Add enabledisable()
bbfbba08f9aa drm/i915: Polish for_each_dbuf_slice()
407ca0202e11 drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST
4bec22613175 drm/i915: Use intel_dbuf_slice_size()
6182af680aea drm/i915: Store dbuf slice mask in device info
3bcf75a562a4 drm/i915: Handle dbuf bypass path allocation earlier
c4e158b6022a drm/i915: Collect dbuf device info into a sub-struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/index.html
[-- Attachment #1.2: Type: text/html, Size: 3245 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: dbuf cleanups
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (11 preceding siblings ...)
2021-04-16 17:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-04-16 19:08 ` Patchwork
2021-04-20 12:57 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-04-16 19:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 27257 bytes --]
== Series Details ==
Series: drm/i915: dbuf cleanups
URL : https://patchwork.freedesktop.org/series/89171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9978_full -> Patchwork_19944_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19944_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][1] ([fdo#109271]) +13 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk7/igt@feature_discovery@display-3x.html
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][2] ([i915#3002])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb6/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][4] ([i915#3354])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_mmap_gtt@big-copy:
- shard-skl: [PASS][10] -> [FAIL][11] ([i915#307])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl3/igt@gem_mmap_gtt@big-copy.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl5/igt@gem_mmap_gtt@big-copy.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][12] ([i915#2658])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb6/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][13] ([i915#2658])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl6/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271]) +62 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][15] ([i915#2724])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb6/igt@gem_userptr_blits@vma-merge.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [PASS][16] -> [TIMEOUT][17] ([i915#2795])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-tglb2/igt@gem_vm_create@destroy-race.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-tglb8/igt@gem_vm_create@destroy-race.html
* igt@kms_ccs@pipe-c-bad-rotation-90:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111304])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl4/igt@kms_ccs@pipe-c-bad-rotation-90.html
* igt@kms_chamelium@hdmi-hpd:
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl8/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +5 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl5/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +16 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +10 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb6/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk7/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][26] -> [FAIL][27] ([i915#79])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][28] -> [DMESG-WARN][29] ([i915#180])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#2642])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#2642])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
- shard-snb: NOTRUN -> [SKIP][32] ([fdo#109271]) +216 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271]) +26 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: NOTRUN -> [FAIL][34] ([i915#1188])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#533])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][36] -> [DMESG-WARN][37] ([i915#180]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-glk: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#533])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][39] ([fdo#108145] / [i915#265]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][40] ([fdo#108145] / [i915#265]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][43] ([i915#265]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-glk: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#658])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#658]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#658])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl8/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#658])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][48] -> [SKIP][49] ([fdo#109441]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-iclb2/igt@kms_psr@psr2_basic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-iclb5/igt@kms_psr@psr2_basic.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][50] ([IGT#2])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl2/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271]) +169 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl6/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2437])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#1722])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl8/igt@perf@polling-small-buf.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl6/igt@perf@polling-small-buf.html
* igt@sysfs_clients@busy:
- shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2994])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@sysfs_clients@busy.html
* igt@sysfs_clients@recycle-many:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#2994]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl2/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-apl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][59] ([i915#2842]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][61] ([i915#2842]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [FAIL][63] ([i915#2842]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][65] ([i915#1436] / [i915#716]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-glk2/igt@gen9_exec_parse@allowed-all.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][67] ([i915#1436] / [i915#716]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl2/igt@gen9_exec_parse@allowed-single.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl4/igt@gen9_exec_parse@allowed-single.html
* igt@i915_suspend@forcewake:
- shard-kbl: [DMESG-WARN][69] ([i915#180]) -> [PASS][70] +3 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl6/igt@i915_suspend@forcewake.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl4/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-glk: [FAIL][71] -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-glk5/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk8/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2:
- shard-glk: [FAIL][73] ([i915#79]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][75] ([i915#79]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
- shard-skl: [INCOMPLETE][77] ([i915#198]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][79] ([i915#2122]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][81] ([fdo#108145] / [i915#265]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][83] ([fdo#109441]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-a:
- shard-snb: [SKIP][85] ([fdo#109271]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-snb2/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-snb7/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][87] ([i915#2842]) -> [FAIL][88] ([i915#2852])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-iclb3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][89] ([i915#1226]) -> [SKIP][90] ([fdo#109349])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][91] ([i915#2920]) -> [SKIP][92] ([i915#658]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-iclb3/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][93] ([i915#658]) -> [SKIP][94] ([i915#2920]) +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#602]) -> ([FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl7/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl7/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl7/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl7/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl6/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl6/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl4/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl6/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-kbl2/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl7/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl6/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl6/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl7/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl3/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl4/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl7/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-kbl6/igt@runner@aborted.html
- shard-apl: ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115]) ([i915#1610] / [i915#180] / [i915#2292] / [i915#3002]) -> ([FAIL][116], [FAIL][117], [FAIL][118]) ([i915#180] / [i915#3002])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-apl2/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-apl8/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-apl2/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-apl6/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl2/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-apl1/igt@runner@aborted.html
- shard-skl: ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([i915#1436] / [i915#2029] / [i915#3002]) -> ([FAIL][125], [FAIL][126]) ([i915#3002])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl2/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl2/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl2/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl3/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl3/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9978/shard-skl3/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl3/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/shard-skl5/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3354]: https://gitlab.freedesktop.org/drm/intel/issues/3354
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9978 -> Patchwork_19944
CI-20190529: 20190529
CI_DRM_9978: 732dea807fffac8bed7696a335973c95f810e4b1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6067: 14317b92a672d9a20cd04fc3b0c80e2fb12d51d5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19944: bb42f353dfe4f00c428649ce0ac736b6975bd237 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19944/index.html
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
` (12 preceding siblings ...)
2021-04-16 19:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-04-20 12:57 ` Jani Nikula
2021-04-20 13:22 ` Ville Syrjälä
13 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2021-04-20 12:57 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 16 Apr 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> A bunch of drive-by-cleanup While I was reading through
> the dbuf code.
Good stuff. On the series,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Some thoughts provoked by the series:
* Time to start splitting up dbuf/ddb/wm stuff from intel_pm.[ch] to
separate file(s) under display/?
* Time to start moving more display related struct intel_device_info
fields under the display substruct?
BR,
Jani.
>
> Ville Syrjälä (8):
> drm/i915: Collect dbuf device info into a sub-struct
> drm/i915: Handle dbuf bypass path allocation earlier
> drm/i915: Store dbuf slice mask in device info
> drm/i915: Use intel_dbuf_slice_size()
> drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST
> drm/i915: Polish for_each_dbuf_slice()
> drm/i915: Add enabledisable()
> drm/i915: Say "enable foo" instead of "set foo to enabled"
>
> drivers/gpu/drm/i915/display/intel_bw.c | 11 ++---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.h | 9 ++--
> .../drm/i915/display/intel_display_power.c | 24 ++++------
> drivers/gpu/drm/i915/display/intel_dp.c | 14 +++---
> .../drm/i915/display/intel_dp_aux_backlight.c | 2 +-
> drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
> drivers/gpu/drm/i915/i915_pci.c | 16 +++----
> drivers/gpu/drm/i915/i915_utils.h | 5 +++
> drivers/gpu/drm/i915/intel_device_info.h | 6 ++-
> drivers/gpu/drm/i915/intel_pm.c | 45 +++++++------------
> drivers/gpu/drm/i915/intel_pm.h | 1 +
> 12 files changed, 65 insertions(+), 76 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups
2021-04-20 12:57 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
@ 2021-04-20 13:22 ` Ville Syrjälä
0 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjälä @ 2021-04-20 13:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Apr 20, 2021 at 03:57:45PM +0300, Jani Nikula wrote:
> On Fri, 16 Apr 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > A bunch of drive-by-cleanup While I was reading through
> > the dbuf code.
>
> Good stuff. On the series,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Some thoughts provoked by the series:
>
> * Time to start splitting up dbuf/ddb/wm stuff from intel_pm.[ch] to
> separate file(s) under display/?
I guess we could start shoveling. I've been putting it off due to
having bunch of in-flight stuff (wm latency cleanups, s/intel/ilk/
rename, and some wip skl+ dbuf patches come to mind). But I suppose
those aren't going to make any progress without a reposting anyway.
I could always respin them after the code has settled in its new
home.
>
> * Time to start moving more display related struct intel_device_info
> fields under the display substruct?
Perhaps. I was a bit torn between .dbuf and .display.dbuf for this
series. In the end I decided that .display.dbuf is a bit too long
for my liking. Not sure if s/.display/.de/ might make it more
palatable...
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 16+ messages in thread