* [PATCH v4] drm/doc/rfc: i915 DG1 uAPI
@ 2021-04-19 16:44 ` Matthew Auld
0 siblings, 0 replies; 8+ messages in thread
From: Matthew Auld @ 2021-04-19 16:44 UTC (permalink / raw)
To: intel-gfx
Cc: Lionel Landwerlin, Thomas Hellström, Jordan Justen,
dri-devel, Daniel Vetter, Kenneth Graunke,
Daniele Ceraolo Spurio, Jon Bloomfield, Jason Ekstrand, mesa-dev,
Daniel Vetter
Add an entry for the new uAPI needed for DG1. Also add the overall
upstream plan, including some notes for the TTM conversion.
v2(Daniel):
- include the overall upstreaming plan
- add a note for mmap, there are differences here for TTM vs i915
- bunch of other suggestions from Daniel
v3:
(Daniel)
- add a note for set/get caching stuff
- add some more docs for existing query and extensions stuff
- add an actual code example for regions query
- bunch of other stuff
(Jason)
- uAPI change(!):
- try a simpler design with the placements extension
- rather than have a generic setparam which can cover multiple
use cases, have each extension be responsible for one thing
only
v4:
(Daniel)
- add some more notes for ttm conversion
- bunch of other stuff
(Jason)
- uAPI change(!):
- drop all the extra rsvd members for the region_query and
region_info, just keep the bare minimum needed for padding
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@linux.intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Dave Airlie <airlied@gmail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: mesa-dev@lists.freedesktop.org
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
Documentation/gpu/rfc/i915_gem_lmem.h | 212 ++++++++++++++++++++++++
Documentation/gpu/rfc/i915_gem_lmem.rst | 130 +++++++++++++++
Documentation/gpu/rfc/index.rst | 4 +
3 files changed, 346 insertions(+)
create mode 100644 Documentation/gpu/rfc/i915_gem_lmem.h
create mode 100644 Documentation/gpu/rfc/i915_gem_lmem.rst
diff --git a/Documentation/gpu/rfc/i915_gem_lmem.h b/Documentation/gpu/rfc/i915_gem_lmem.h
new file mode 100644
index 000000000000..7ed59b6202d5
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_gem_lmem.h
@@ -0,0 +1,212 @@
+/**
+ * enum drm_i915_gem_memory_class - Supported memory classes
+ */
+enum drm_i915_gem_memory_class {
+ /** @I915_MEMORY_CLASS_SYSTEM: System memory */
+ I915_MEMORY_CLASS_SYSTEM = 0,
+ /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
+ I915_MEMORY_CLASS_DEVICE,
+};
+
+/**
+ * struct drm_i915_gem_memory_class_instance - Identify particular memory region
+ */
+struct drm_i915_gem_memory_class_instance {
+ /** @memory_class: See enum drm_i915_gem_memory_class */
+ __u16 memory_class;
+
+ /** @memory_instance: Which instance */
+ __u16 memory_instance;
+};
+
+/**
+ * struct drm_i915_memory_region_info - Describes one region as known to the
+ * driver.
+ *
+ * Note that we reserve some stuff here for potential future work. As an example
+ * we might want expose the capabilities(see @caps) for a given region, which
+ * could include things like if the region is CPU mappable/accessible, what are
+ * the supported mapping types etc.
+ *
+ * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
+ * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
+ * at &drm_i915_query_item.query_id.
+ */
+struct drm_i915_memory_region_info {
+ /** @region: The class:instance pair encoding */
+ struct drm_i915_gem_memory_class_instance region;
+
+ /** @pad: MBZ */
+ __u32 pad;
+
+ /** @caps: MBZ */
+ __u64 caps;
+
+ /** @probed_size: Memory probed by the driver (-1 = unknown) */
+ __u64 probed_size;
+
+ /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
+ __u64 unallocated_size;
+};
+
+/**
+ * struct drm_i915_query_memory_regions
+ *
+ * The region info query enumerates all regions known to the driver by filling
+ * in an array of struct drm_i915_memory_region_info structures.
+ *
+ * Example for getting the list of supported regions:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_memory_regions *info;
+ * struct drm_i915_query_item item = {
+ * .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ * };
+ * struct drm_i915_query query = {
+ * .num_items = 1,
+ * .items_ptr = (uintptr_t)&item,
+ * };
+ * int err, i;
+ *
+ * // First query the size of the blob we need, this needs to be large
+ * // enough to hold our array of regions. The kernel will fill out the
+ * // item.length for us, which is the number of bytes we need.
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * info = calloc(1, item.length);
+ * // Now that we allocated the required number of bytes, we call the ioctl
+ * // again, this time with the data_ptr pointing to our newly allocated
+ * // blob, which the kernel can then populate with the all the region info.
+ * item.data_ptr = (uintptr_t)&info,
+ *
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * // We can now access each region in the array
+ * for (i = 0; i < info->num_regions; i++) {
+ * struct drm_i915_memory_region_info mr = info->regions[i];
+ * u16 class = mr.region.class;
+ * u16 instance = mr.region.instance;
+ *
+ * ....
+ * }
+ *
+ * free(info);
+ */
+struct drm_i915_query_memory_regions {
+ /** @num_regions: Number of supported regions */
+ __u32 num_regions;
+
+ /** @pad: MBZ */
+ __u32 pad;
+
+ /** @regions: Info about each supported region */
+ struct drm_i915_memory_region_info regions[];
+};
+
+#define DRM_I915_GEM_CREATE_EXT 0xdeadbeaf
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
+
+/**
+ * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
+ * extension support using struct i915_user_extension.
+ *
+ * Note that in the future we want to have our buffer flags here, at least for
+ * the stuff that is immutable. Previously we would have two ioctls, one to
+ * create the object with gem_create, and another to apply various parameters,
+ * however this creates some ambiguity for the params which are considered
+ * immutable. Also in general we're phasing out the various SET/GET ioctls.
+ */
+struct drm_i915_gem_create_ext {
+ /**
+ * @size: Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ *
+ * Note that for some devices we have might have further minimum
+ * page-size restrictions(larger than 4K), like for device local-memory.
+ * However in general the final size here should always reflect any
+ * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
+ * extension to place the object in device local-memory.
+ */
+ __u64 size;
+ /**
+ * @handle: Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ /** @flags: MBZ */
+ __u32 flags;
+ /**
+ * @extensions: The chain of extensions to apply to this object.
+ *
+ * This will be useful in the future when we need to support several
+ * different extensions, and we need to apply more than one when
+ * creating the object. See struct i915_user_extension.
+ *
+ * If we don't supply any extensions then we get the same old gem_create
+ * behaviour.
+ *
+ * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
+ * struct drm_i915_gem_create_ext_memory_regions.
+ */
+#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+ __u64 extensions;
+};
+
+/**
+ * struct drm_i915_gem_create_ext_memory_regions - The
+ * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
+ *
+ * Set the object with the desired set of placements/regions in priority
+ * order. Each entry must be unique and supported by the device.
+ *
+ * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
+ * an equivalent layout of class:instance pair encodings. See struct
+ * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
+ * query the supported regions for a device.
+ *
+ * As an example, on discrete devices, if we wish to set the placement as
+ * device local-memory we can do something like:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_gem_memory_class_instance region_lmem = {
+ * .memory_class = I915_MEMORY_CLASS_DEVICE,
+ * .memory_instance = 0,
+ * };
+ * struct drm_i915_gem_create_ext_memory_regions regions = {
+ * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ * .regions = (uintptr_t)®ion_lmem,
+ * .num_regions = 1,
+ * };
+ * struct drm_i915_gem_create_ext create_ext = {
+ * .size = 16 * PAGE_SIZE,
+ * .extensions = (uintptr_t)®ions,
+ * };
+ *
+ * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ * if (err) ...
+ *
+ * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
+ * along with the final object size in &drm_i915_gem_create_ext.size, which
+ * should account for any rounding up, if required.
+ */
+struct drm_i915_gem_create_ext_memory_regions {
+ /** @base: Extension link. See struct i915_user_extension. */
+ struct i915_user_extension base;
+
+ /** @pad: MBZ */
+ __u32 pad;
+ /** @num_regions: Number of elements in the @regions array. */
+ __u32 num_regions;
+ /**
+ * @regions: The regions/placements array.
+ *
+ * An array of struct drm_i915_gem_memory_class_instance.
+ */
+ __u64 regions;
+};
diff --git a/Documentation/gpu/rfc/i915_gem_lmem.rst b/Documentation/gpu/rfc/i915_gem_lmem.rst
new file mode 100644
index 000000000000..462f1efd9003
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_gem_lmem.rst
@@ -0,0 +1,130 @@
+=========================
+I915 DG1/LMEM RFC Section
+=========================
+
+Upstream plan
+=============
+For upstream the overall plan for landing all the DG1 stuff and turning it for
+real, with all the uAPI bits is:
+
+* Merge basic HW enabling of DG1(still without pciid)
+* Merge the uAPI bits behind special CONFIG_BROKEN(or so) flag
+ * At this point we can still make changes, but importantly this lets us
+ start running IGTs which can utilize local-memory in CI
+* Convert over to TTM, make sure it all keeps working. Some of the work items:
+ * TTM shrinker for discrete
+ * dma_resv_lockitem for full dma_resv_lock, i.e not just trylock
+ * Use TTM CPU pagefault handler
+ * Route shmem backend over to TTM SYSTEM for discrete
+ * TTM purgeable object support
+ * Move i915 buddy allocator over to TTM
+ * MMAP ioctl mode(see `I915 MMAP`_)
+ * SET/GET ioctl caching(see `I915 SET/GET CACHING`_)
+* Add pciid for DG1 and turn on uAPI for real
+
+New object placement and region query uAPI
+==========================================
+Starting from DG1 we need to give userspace the ability to allocate buffers from
+device local-memory. Currently the driver supports gem_create, which can place
+buffers in system memory via shmem, and the usual assortment of other
+interfaces, like dumb buffers and userptr.
+
+To support this new capability, while also providing a uAPI which will work
+beyond just DG1, we propose to offer three new bits of uAPI:
+
+DRM_I915_QUERY_MEMORY_REGIONS
+-----------------------------
+New query ID which allows userspace to discover the list of supported memory
+regions(like system-memory and local-memory) for a given device. We identify
+each region with a class and instance pair, which should be unique. The class
+here would be DEVICE or SYSTEM, and the instance would be zero, on platforms
+like DG1.
+
+Side note: The class/instance design is borrowed from our existing engine uAPI,
+where we describe every physical engine in terms of its class, and the
+particular instance, since we can have more than one per class.
+
+In the future we also want to expose more information which can further
+describe the capabilities of a region.
+
+.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h
+ :functions: drm_i915_gem_memory_class drm_i915_gem_memory_class_instance drm_i915_memory_region_info drm_i915_query_memory_regions
+
+GEM_CREATE_EXT
+--------------
+New ioctl which is basically just gem_create but now allows userspace to
+provide a chain of possible extensions. Note that if we don't provide any
+extensions then we get the exact same behaviour as gem_create.
+
+Side note: We also need to support PXP[1] in the near future, which is also
+applicable to integrated platforms, and adds its own gem_create_ext extension,
+which basically lets userspace mark a buffer as "protected".
+
+.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h
+ :functions: drm_i915_gem_create_ext
+
+I915_GEM_CREATE_EXT_MEMORY_REGIONS
+----------------------------------
+Implemented as an extension for gem_create_ext, we would now allow userspace to
+optionally provide an immutable list of preferred placements at creation time,
+in priority order, for a given buffer object. For the placements we expect
+them each to use the class/instance encoding, as per the output of the regions
+query. Having the list in priority order will be useful in the future when
+placing an object, say during eviction.
+
+.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h
+ :functions: drm_i915_gem_create_ext_memory_regions
+
+One fair criticism here is that this seems a little over-engineered[2]. If we
+just consider DG1 then yes, a simple gem_create.flags or something is totally
+all that's needed to tell the kernel to allocate the buffer in local-memory or
+whatever. However looking to the future we need uAPI which can also support
+upcoming Xe HP multi-tile architecture in a sane way, where there can be
+multiple local-memory instances for a given device, and so using both class and
+instance in our uAPI to describe regions is desirable, although specifically
+for DG1 it's uninteresting, since we only have a single local-memory instance.
+
+Existing uAPI issues
+====================
+Some potential issues we still need to resolve.
+
+I915 MMAP
+---------
+In i915 there are multiple ways to MMAP GEM object, including mapping the same
+object using different mapping types(WC vs WB), i.e multiple active mmaps per
+object. TTM expects one MMAP at most for the lifetime of the object. If it
+turns out that we have to backpedal here, there might be some potential
+userspace fallout.
+
+I915 SET/GET CACHING
+--------------------
+In i915 we have set/get_caching ioctl. TTM doesn't let us to change this, but
+DG1 doesn't support non-snooped pcie transactions, so we can just always
+allocate as WB for smem-only buffers. If/when our hw gains support for
+non-snooped pcie transactions then we must fix this mode at allocation time as
+a new GEM extension.
+
+This is related to the mmap problem, because in general (meaning, when we're
+not running on intel cpus) the cpu mmap must not, ever, be inconsistent with
+allocation mode.
+
+Possible idea is to let the kernel picks the mmap mode for userspace from the
+following table:
+
+smem-only: WB. Userspace does not need to call clflush.
+
+smem+lmem: We allocate uncached memory, and give userspace a WC mapping
+for when the buffer is in smem, and WC when it's in lmem. GPU does snooped
+access, which is a bit inefficient.
+
+lmem only: always WC
+
+This means on discrete you only get a single mmap mode, all others must be
+rejected. That's probably going to be a new default mode or something like
+that.
+
+Links
+=====
+[1] https://patchwork.freedesktop.org/series/86798/
+
+[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599#note_553791
diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst
index a8621f7dab8b..05670442ca1b 100644
--- a/Documentation/gpu/rfc/index.rst
+++ b/Documentation/gpu/rfc/index.rst
@@ -15,3 +15,7 @@ host such documentation:
* Once the code has landed move all the documentation to the right places in
the main core, helper or driver sections.
+
+.. toctree::
+
+ i915_gem_lmem.rst
--
2.26.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH v4] drm/doc/rfc: i915 DG1 uAPI
@ 2021-04-19 16:44 ` Matthew Auld
0 siblings, 0 replies; 8+ messages in thread
From: Matthew Auld @ 2021-04-19 16:44 UTC (permalink / raw)
To: intel-gfx
Cc: Lionel Landwerlin, Thomas Hellström, dri-devel,
Daniel Vetter, Kenneth Graunke, mesa-dev, Daniel Vetter
Add an entry for the new uAPI needed for DG1. Also add the overall
upstream plan, including some notes for the TTM conversion.
v2(Daniel):
- include the overall upstreaming plan
- add a note for mmap, there are differences here for TTM vs i915
- bunch of other suggestions from Daniel
v3:
(Daniel)
- add a note for set/get caching stuff
- add some more docs for existing query and extensions stuff
- add an actual code example for regions query
- bunch of other stuff
(Jason)
- uAPI change(!):
- try a simpler design with the placements extension
- rather than have a generic setparam which can cover multiple
use cases, have each extension be responsible for one thing
only
v4:
(Daniel)
- add some more notes for ttm conversion
- bunch of other stuff
(Jason)
- uAPI change(!):
- drop all the extra rsvd members for the region_query and
region_info, just keep the bare minimum needed for padding
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@linux.intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Dave Airlie <airlied@gmail.com>
Cc: dri-devel@lists.freedesktop.org
Cc: mesa-dev@lists.freedesktop.org
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
Documentation/gpu/rfc/i915_gem_lmem.h | 212 ++++++++++++++++++++++++
Documentation/gpu/rfc/i915_gem_lmem.rst | 130 +++++++++++++++
Documentation/gpu/rfc/index.rst | 4 +
3 files changed, 346 insertions(+)
create mode 100644 Documentation/gpu/rfc/i915_gem_lmem.h
create mode 100644 Documentation/gpu/rfc/i915_gem_lmem.rst
diff --git a/Documentation/gpu/rfc/i915_gem_lmem.h b/Documentation/gpu/rfc/i915_gem_lmem.h
new file mode 100644
index 000000000000..7ed59b6202d5
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_gem_lmem.h
@@ -0,0 +1,212 @@
+/**
+ * enum drm_i915_gem_memory_class - Supported memory classes
+ */
+enum drm_i915_gem_memory_class {
+ /** @I915_MEMORY_CLASS_SYSTEM: System memory */
+ I915_MEMORY_CLASS_SYSTEM = 0,
+ /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
+ I915_MEMORY_CLASS_DEVICE,
+};
+
+/**
+ * struct drm_i915_gem_memory_class_instance - Identify particular memory region
+ */
+struct drm_i915_gem_memory_class_instance {
+ /** @memory_class: See enum drm_i915_gem_memory_class */
+ __u16 memory_class;
+
+ /** @memory_instance: Which instance */
+ __u16 memory_instance;
+};
+
+/**
+ * struct drm_i915_memory_region_info - Describes one region as known to the
+ * driver.
+ *
+ * Note that we reserve some stuff here for potential future work. As an example
+ * we might want expose the capabilities(see @caps) for a given region, which
+ * could include things like if the region is CPU mappable/accessible, what are
+ * the supported mapping types etc.
+ *
+ * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
+ * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
+ * at &drm_i915_query_item.query_id.
+ */
+struct drm_i915_memory_region_info {
+ /** @region: The class:instance pair encoding */
+ struct drm_i915_gem_memory_class_instance region;
+
+ /** @pad: MBZ */
+ __u32 pad;
+
+ /** @caps: MBZ */
+ __u64 caps;
+
+ /** @probed_size: Memory probed by the driver (-1 = unknown) */
+ __u64 probed_size;
+
+ /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
+ __u64 unallocated_size;
+};
+
+/**
+ * struct drm_i915_query_memory_regions
+ *
+ * The region info query enumerates all regions known to the driver by filling
+ * in an array of struct drm_i915_memory_region_info structures.
+ *
+ * Example for getting the list of supported regions:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_memory_regions *info;
+ * struct drm_i915_query_item item = {
+ * .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ * };
+ * struct drm_i915_query query = {
+ * .num_items = 1,
+ * .items_ptr = (uintptr_t)&item,
+ * };
+ * int err, i;
+ *
+ * // First query the size of the blob we need, this needs to be large
+ * // enough to hold our array of regions. The kernel will fill out the
+ * // item.length for us, which is the number of bytes we need.
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * info = calloc(1, item.length);
+ * // Now that we allocated the required number of bytes, we call the ioctl
+ * // again, this time with the data_ptr pointing to our newly allocated
+ * // blob, which the kernel can then populate with the all the region info.
+ * item.data_ptr = (uintptr_t)&info,
+ *
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * // We can now access each region in the array
+ * for (i = 0; i < info->num_regions; i++) {
+ * struct drm_i915_memory_region_info mr = info->regions[i];
+ * u16 class = mr.region.class;
+ * u16 instance = mr.region.instance;
+ *
+ * ....
+ * }
+ *
+ * free(info);
+ */
+struct drm_i915_query_memory_regions {
+ /** @num_regions: Number of supported regions */
+ __u32 num_regions;
+
+ /** @pad: MBZ */
+ __u32 pad;
+
+ /** @regions: Info about each supported region */
+ struct drm_i915_memory_region_info regions[];
+};
+
+#define DRM_I915_GEM_CREATE_EXT 0xdeadbeaf
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
+
+/**
+ * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
+ * extension support using struct i915_user_extension.
+ *
+ * Note that in the future we want to have our buffer flags here, at least for
+ * the stuff that is immutable. Previously we would have two ioctls, one to
+ * create the object with gem_create, and another to apply various parameters,
+ * however this creates some ambiguity for the params which are considered
+ * immutable. Also in general we're phasing out the various SET/GET ioctls.
+ */
+struct drm_i915_gem_create_ext {
+ /**
+ * @size: Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ *
+ * Note that for some devices we have might have further minimum
+ * page-size restrictions(larger than 4K), like for device local-memory.
+ * However in general the final size here should always reflect any
+ * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
+ * extension to place the object in device local-memory.
+ */
+ __u64 size;
+ /**
+ * @handle: Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ /** @flags: MBZ */
+ __u32 flags;
+ /**
+ * @extensions: The chain of extensions to apply to this object.
+ *
+ * This will be useful in the future when we need to support several
+ * different extensions, and we need to apply more than one when
+ * creating the object. See struct i915_user_extension.
+ *
+ * If we don't supply any extensions then we get the same old gem_create
+ * behaviour.
+ *
+ * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
+ * struct drm_i915_gem_create_ext_memory_regions.
+ */
+#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+ __u64 extensions;
+};
+
+/**
+ * struct drm_i915_gem_create_ext_memory_regions - The
+ * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
+ *
+ * Set the object with the desired set of placements/regions in priority
+ * order. Each entry must be unique and supported by the device.
+ *
+ * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
+ * an equivalent layout of class:instance pair encodings. See struct
+ * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
+ * query the supported regions for a device.
+ *
+ * As an example, on discrete devices, if we wish to set the placement as
+ * device local-memory we can do something like:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_gem_memory_class_instance region_lmem = {
+ * .memory_class = I915_MEMORY_CLASS_DEVICE,
+ * .memory_instance = 0,
+ * };
+ * struct drm_i915_gem_create_ext_memory_regions regions = {
+ * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ * .regions = (uintptr_t)®ion_lmem,
+ * .num_regions = 1,
+ * };
+ * struct drm_i915_gem_create_ext create_ext = {
+ * .size = 16 * PAGE_SIZE,
+ * .extensions = (uintptr_t)®ions,
+ * };
+ *
+ * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ * if (err) ...
+ *
+ * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
+ * along with the final object size in &drm_i915_gem_create_ext.size, which
+ * should account for any rounding up, if required.
+ */
+struct drm_i915_gem_create_ext_memory_regions {
+ /** @base: Extension link. See struct i915_user_extension. */
+ struct i915_user_extension base;
+
+ /** @pad: MBZ */
+ __u32 pad;
+ /** @num_regions: Number of elements in the @regions array. */
+ __u32 num_regions;
+ /**
+ * @regions: The regions/placements array.
+ *
+ * An array of struct drm_i915_gem_memory_class_instance.
+ */
+ __u64 regions;
+};
diff --git a/Documentation/gpu/rfc/i915_gem_lmem.rst b/Documentation/gpu/rfc/i915_gem_lmem.rst
new file mode 100644
index 000000000000..462f1efd9003
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_gem_lmem.rst
@@ -0,0 +1,130 @@
+=========================
+I915 DG1/LMEM RFC Section
+=========================
+
+Upstream plan
+=============
+For upstream the overall plan for landing all the DG1 stuff and turning it for
+real, with all the uAPI bits is:
+
+* Merge basic HW enabling of DG1(still without pciid)
+* Merge the uAPI bits behind special CONFIG_BROKEN(or so) flag
+ * At this point we can still make changes, but importantly this lets us
+ start running IGTs which can utilize local-memory in CI
+* Convert over to TTM, make sure it all keeps working. Some of the work items:
+ * TTM shrinker for discrete
+ * dma_resv_lockitem for full dma_resv_lock, i.e not just trylock
+ * Use TTM CPU pagefault handler
+ * Route shmem backend over to TTM SYSTEM for discrete
+ * TTM purgeable object support
+ * Move i915 buddy allocator over to TTM
+ * MMAP ioctl mode(see `I915 MMAP`_)
+ * SET/GET ioctl caching(see `I915 SET/GET CACHING`_)
+* Add pciid for DG1 and turn on uAPI for real
+
+New object placement and region query uAPI
+==========================================
+Starting from DG1 we need to give userspace the ability to allocate buffers from
+device local-memory. Currently the driver supports gem_create, which can place
+buffers in system memory via shmem, and the usual assortment of other
+interfaces, like dumb buffers and userptr.
+
+To support this new capability, while also providing a uAPI which will work
+beyond just DG1, we propose to offer three new bits of uAPI:
+
+DRM_I915_QUERY_MEMORY_REGIONS
+-----------------------------
+New query ID which allows userspace to discover the list of supported memory
+regions(like system-memory and local-memory) for a given device. We identify
+each region with a class and instance pair, which should be unique. The class
+here would be DEVICE or SYSTEM, and the instance would be zero, on platforms
+like DG1.
+
+Side note: The class/instance design is borrowed from our existing engine uAPI,
+where we describe every physical engine in terms of its class, and the
+particular instance, since we can have more than one per class.
+
+In the future we also want to expose more information which can further
+describe the capabilities of a region.
+
+.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h
+ :functions: drm_i915_gem_memory_class drm_i915_gem_memory_class_instance drm_i915_memory_region_info drm_i915_query_memory_regions
+
+GEM_CREATE_EXT
+--------------
+New ioctl which is basically just gem_create but now allows userspace to
+provide a chain of possible extensions. Note that if we don't provide any
+extensions then we get the exact same behaviour as gem_create.
+
+Side note: We also need to support PXP[1] in the near future, which is also
+applicable to integrated platforms, and adds its own gem_create_ext extension,
+which basically lets userspace mark a buffer as "protected".
+
+.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h
+ :functions: drm_i915_gem_create_ext
+
+I915_GEM_CREATE_EXT_MEMORY_REGIONS
+----------------------------------
+Implemented as an extension for gem_create_ext, we would now allow userspace to
+optionally provide an immutable list of preferred placements at creation time,
+in priority order, for a given buffer object. For the placements we expect
+them each to use the class/instance encoding, as per the output of the regions
+query. Having the list in priority order will be useful in the future when
+placing an object, say during eviction.
+
+.. kernel-doc:: Documentation/gpu/rfc/i915_gem_lmem.h
+ :functions: drm_i915_gem_create_ext_memory_regions
+
+One fair criticism here is that this seems a little over-engineered[2]. If we
+just consider DG1 then yes, a simple gem_create.flags or something is totally
+all that's needed to tell the kernel to allocate the buffer in local-memory or
+whatever. However looking to the future we need uAPI which can also support
+upcoming Xe HP multi-tile architecture in a sane way, where there can be
+multiple local-memory instances for a given device, and so using both class and
+instance in our uAPI to describe regions is desirable, although specifically
+for DG1 it's uninteresting, since we only have a single local-memory instance.
+
+Existing uAPI issues
+====================
+Some potential issues we still need to resolve.
+
+I915 MMAP
+---------
+In i915 there are multiple ways to MMAP GEM object, including mapping the same
+object using different mapping types(WC vs WB), i.e multiple active mmaps per
+object. TTM expects one MMAP at most for the lifetime of the object. If it
+turns out that we have to backpedal here, there might be some potential
+userspace fallout.
+
+I915 SET/GET CACHING
+--------------------
+In i915 we have set/get_caching ioctl. TTM doesn't let us to change this, but
+DG1 doesn't support non-snooped pcie transactions, so we can just always
+allocate as WB for smem-only buffers. If/when our hw gains support for
+non-snooped pcie transactions then we must fix this mode at allocation time as
+a new GEM extension.
+
+This is related to the mmap problem, because in general (meaning, when we're
+not running on intel cpus) the cpu mmap must not, ever, be inconsistent with
+allocation mode.
+
+Possible idea is to let the kernel picks the mmap mode for userspace from the
+following table:
+
+smem-only: WB. Userspace does not need to call clflush.
+
+smem+lmem: We allocate uncached memory, and give userspace a WC mapping
+for when the buffer is in smem, and WC when it's in lmem. GPU does snooped
+access, which is a bit inefficient.
+
+lmem only: always WC
+
+This means on discrete you only get a single mmap mode, all others must be
+rejected. That's probably going to be a new default mode or something like
+that.
+
+Links
+=====
+[1] https://patchwork.freedesktop.org/series/86798/
+
+[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599#note_553791
diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst
index a8621f7dab8b..05670442ca1b 100644
--- a/Documentation/gpu/rfc/index.rst
+++ b/Documentation/gpu/rfc/index.rst
@@ -15,3 +15,7 @@ host such documentation:
* Once the code has landed move all the documentation to the right places in
the main core, helper or driver sections.
+
+.. toctree::
+
+ i915_gem_lmem.rst
--
2.26.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/doc/rfc: i915 DG1 uAPI (rev3)
2021-04-19 16:44 ` [Intel-gfx] " Matthew Auld
(?)
@ 2021-04-19 17:17 ` Patchwork
-1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-04-19 17:17 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: drm/doc/rfc: i915 DG1 uAPI (rev3)
URL : https://patchwork.freedesktop.org/series/88958/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4a27b6a842d8 drm/doc/rfc: i915 DG1 uAPI
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#53:
new file mode 100644
-:58: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#58: FILE: Documentation/gpu/rfc/i915_gem_lmem.h:1:
+/**
-:167: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#167: FILE: Documentation/gpu/rfc/i915_gem_lmem.h:110:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
-:276: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#276: FILE: Documentation/gpu/rfc/i915_gem_lmem.rst:1:
+=========================
total: 0 errors, 4 warnings, 0 checks, 349 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/doc/rfc: i915 DG1 uAPI (rev3)
2021-04-19 16:44 ` [Intel-gfx] " Matthew Auld
(?)
(?)
@ 2021-04-19 17:21 ` Patchwork
-1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-04-19 17:21 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: drm/doc/rfc: i915 DG1 uAPI (rev3)
URL : https://patchwork.freedesktop.org/series/88958/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/doc/rfc: i915 DG1 uAPI (rev3)
2021-04-19 16:44 ` [Intel-gfx] " Matthew Auld
` (2 preceding siblings ...)
(?)
@ 2021-04-19 17:45 ` Patchwork
-1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-04-19 17:45 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5555 bytes --]
== Series Details ==
Series: drm/doc/rfc: i915 DG1 uAPI (rev3)
URL : https://patchwork.freedesktop.org/series/88958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9982 -> Patchwork_19952
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/index.html
Known issues
------------
Here are the changes found in Patchwork_19952 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-y/igt@amdgpu/amd_basic@semaphore.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-y: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-y/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [PASS][3] -> [INCOMPLETE][4] ([i915#2782] / [i915#2940])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#1372])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
- fi-icl-y: NOTRUN -> [SKIP][7] ([fdo#109284] / [fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-y/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-y: NOTRUN -> [SKIP][8] ([fdo#109285])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-y/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-y: NOTRUN -> [SKIP][9] ([fdo#109278])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-icl-y: NOTRUN -> [SKIP][10] ([fdo#110189]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-icl-y: NOTRUN -> [SKIP][11] ([i915#3301])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-y/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bsw-nick: NOTRUN -> [FAIL][12] ([i915#1436])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-bsw-nick/igt@runner@aborted.html
#### Possible fixes ####
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][13] ([i915#1161] / [i915#262]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [FAIL][15] ([i915#1161]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 40)
------------------------------
Additional (1): fi-icl-y
Missing (3): fi-bsw-cyan fi-bdw-5557u fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9982 -> Patchwork_19952
CI-20190529: 20190529
CI_DRM_9982: a3a8aa7a45870eaf218a337dd312abdbd81a8faa @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6070: 907705f0c3f6b5ae6358a4822434dd6d7a070cff @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19952: 4a27b6a842d87c95462a34f877e90c830a5c702e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4a27b6a842d8 drm/doc/rfc: i915 DG1 uAPI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/index.html
[-- Attachment #1.2: Type: text/html, Size: 6455 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/doc/rfc: i915 DG1 uAPI (rev3)
2021-04-19 16:44 ` [Intel-gfx] " Matthew Auld
` (3 preceding siblings ...)
(?)
@ 2021-04-19 22:05 ` Patchwork
-1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-04-19 22:05 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30256 bytes --]
== Series Details ==
Series: drm/doc/rfc: i915 DG1 uAPI (rev3)
URL : https://patchwork.freedesktop.org/series/88958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9982_full -> Patchwork_19952_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19952_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_mm@all@replace:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#2485])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl2/igt@drm_mm@all@replace.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl10/igt@drm_mm@all@replace.html
* igt@gem_ctx_persistence@engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-snb2/igt@gem_ctx_persistence@engines-mixed-process.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#2481] / [i915#3070])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb6/igt@gem_eio@unwedge-stress.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_create@forked:
- shard-glk: [PASS][6] -> [DMESG-WARN][7] ([i915#118] / [i915#95]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-glk9/igt@gem_exec_create@forked.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-glk9/igt@gem_exec_create@forked.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +268 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-snb5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2389])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb1/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_media_vme:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#284])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@gem_media_vme.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#307])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb7/igt@gem_mmap_gtt@cpuset-medium-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb7/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl2/igt@gem_pread@exhaustion.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271]) +19 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl1/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][21] ([i915#3002])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl6/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@set-cache-level:
- shard-snb: NOTRUN -> [FAIL][22] ([i915#3324])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-snb6/igt@gem_userptr_blits@set-cache-level.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#3297])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [PASS][24] -> [FAIL][25] ([i915#2822])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-tglb1/igt@gem_vm_create@destroy-race.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb3/igt@gem_vm_create@destroy-race.html
* igt@gen7_exec_parse@chained-batch:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#109289])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@gen7_exec_parse@chained-batch.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#1436] / [i915#716])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl10/igt@gen9_exec_parse@allowed-single.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-large:
- shard-skl: NOTRUN -> [FAIL][29] ([i915#3296])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@gen9_exec_parse@bb-large.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][30] -> [FAIL][31] ([i915#2521])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#111615]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_ccs@pipe-c-bad-pixel-format:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111304])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@kms_ccs@pipe-c-bad-pixel-format.html
* igt@kms_chamelium@dp-hpd-fast:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +12 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-snb6/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_color_chamelium@pipe-a-ctm-0-5:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +17 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl2/igt@kms_color_chamelium@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-tglb: NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][38] ([i915#1319])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][39] ([i915#2105])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl2/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3319])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-random:
- shard-tglb: NOTRUN -> [SKIP][41] ([i915#3359])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-32x10-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#2346] / [i915#533])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][44] -> [INCOMPLETE][45] ([i915#155] / [i915#180] / [i915#636])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][46] -> [FAIL][47] ([i915#79])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-apl: NOTRUN -> [FAIL][48] ([i915#2641])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#111825]) +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +4 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl1/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][55] ([fdo#108145] / [i915#265])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#2733])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][59] -> [SKIP][60] ([fdo#109441])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][61] ([IGT#2])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl7/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271]) +46 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2437])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl8/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271]) +195 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl7/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#2530])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][66] -> [FAIL][67] ([i915#1542])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl8/igt@perf@polling-parameterized.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl1/igt@perf@polling-parameterized.html
* igt@prime_nv_pcopy@test_semaphore:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109291])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb5/igt@prime_nv_pcopy@test_semaphore.html
* igt@prime_vgem@sync@rcs0:
- shard-iclb: [PASS][69] -> [INCOMPLETE][70] ([i915#409])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb7/igt@prime_vgem@sync@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb7/igt@prime_vgem@sync@rcs0.html
* igt@sysfs_clients@pidname:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2994]) +4 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl2/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@split-10:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2994])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl4/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_exec_endless@dispatch@vcs1:
- shard-tglb: [INCOMPLETE][73] -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-tglb6/igt@gem_exec_endless@dispatch@vcs1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb2/igt@gem_exec_endless@dispatch@vcs1.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][75] ([i915#2842]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [FAIL][77] ([i915#2842]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-apl6/igt@gem_workarounds@suspend-resume.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl7/igt@gem_workarounds@suspend-resume.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [DMESG-WARN][81] ([i915#180]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_flip@blocking-wf_vblank@c-hdmi-a2:
- shard-glk: [FAIL][83] ([i915#2122]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-glk3/igt@kms_flip@blocking-wf_vblank@c-hdmi-a2.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-glk3/igt@kms_flip@blocking-wf_vblank@c-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][85] ([i915#79]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][87] ([i915#2122]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-skl: [FAIL][89] ([i915#49]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][91] ([i915#1188]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl4/igt@kms_hdr@bpc-switch.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl9/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][93] ([fdo#108145] / [i915#265]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][95] ([fdo#109441]) -> [PASS][96] +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb5/igt@kms_psr@psr2_suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][97] ([i915#180] / [i915#295]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-wait-busy:
- shard-skl: [DMESG-WARN][99] ([i915#1982]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl3/igt@kms_vblank@pipe-c-wait-busy.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl4/igt@kms_vblank@pipe-c-wait-busy.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][101] ([i915#1542]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-glk6/igt@perf@polling-parameterized.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-glk8/igt@perf@polling-parameterized.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][103] ([i915#1722]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl6/igt@perf@polling-small-buf.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl9/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][105] ([i915#2684]) -> [FAIL][106] ([i915#2680])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][107] ([i915#2920]) -> [SKIP][108] ([i915#658]) +2 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][109] ([i915#658]) -> [SKIP][110] ([i915#2920])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#602]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#92])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl2/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl2/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl6/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl1/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl7/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl7/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-kbl4/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl2/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl2/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl6/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-kbl7/igt@runner@aborted.html
- shard-iclb: ([FAIL][128], [FAIL][129]) ([i915#3002]) -> ([FAIL][130], [FAIL][131], [FAIL][132]) ([i915#2426] / [i915#3002] / [i915#409])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-iclb4/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb8/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb7/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-iclb8/igt@runner@aborted.html
- shard-apl: ([FAIL][133], [FAIL][134], [FAIL][135]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002]) -> ([FAIL][136], [FAIL][137]) ([i915#3002])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-apl6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-apl6/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-apl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl6/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-apl2/igt@runner@aborted.html
- shard-skl: ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141]) ([i915#1814] / [i915#2029] / [i915#3002]) -> ([FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([i915#1436] / [i915#2029] / [i915#3002])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl3/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl4/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl4/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9982/shard-skl3/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl2/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl2/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl8/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl3/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/shard-skl6/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#2485]: https://gitlab.freedesktop.org/drm/intel/issues/2485
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2641]: https://gitlab.freedesktop.org/drm/intel/issues/2641
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2684]: https:/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19952/index.html
[-- Attachment #1.2: Type: text/html, Size: 36021 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4] drm/doc/rfc: i915 DG1 uAPI
2021-04-19 16:44 ` [Intel-gfx] " Matthew Auld
@ 2021-04-23 6:25 ` Dave Airlie
-1 siblings, 0 replies; 8+ messages in thread
From: Dave Airlie @ 2021-04-23 6:25 UTC (permalink / raw)
To: Matthew Auld
Cc: Lionel Landwerlin, Thomas Hellström, Jordan Justen,
Intel Graphics Development, dri-devel, Daniel Vetter,
Kenneth Graunke, Daniele Ceraolo Spurio, Jon Bloomfield,
Jason Ekstrand, mesa-dev, Daniel Vetter
On Tue, 20 Apr 2021 at 02:45, Matthew Auld <matthew.auld@intel.com> wrote:
>
> Add an entry for the new uAPI needed for DG1. Also add the overall
> upstream plan, including some notes for the TTM conversion.
>
> v2(Daniel):
> - include the overall upstreaming plan
> - add a note for mmap, there are differences here for TTM vs i915
> - bunch of other suggestions from Daniel
> v3:
> (Daniel)
> - add a note for set/get caching stuff
> - add some more docs for existing query and extensions stuff
> - add an actual code example for regions query
> - bunch of other stuff
> (Jason)
> - uAPI change(!):
> - try a simpler design with the placements extension
> - rather than have a generic setparam which can cover multiple
> use cases, have each extension be responsible for one thing
> only
> v4:
> (Daniel)
> - add some more notes for ttm conversion
> - bunch of other stuff
> (Jason)
> - uAPI change(!):
> - drop all the extra rsvd members for the region_query and
> region_info, just keep the bare minimum needed for padding
Staying out of the ioctl's being over engineering, I hope they have a
good future use case.
The plan seems like a good plan.
Acked-by: Dave Airlie <airlied@redhat.com>
Dave.
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/doc/rfc: i915 DG1 uAPI
@ 2021-04-23 6:25 ` Dave Airlie
0 siblings, 0 replies; 8+ messages in thread
From: Dave Airlie @ 2021-04-23 6:25 UTC (permalink / raw)
To: Matthew Auld
Cc: Lionel Landwerlin, Thomas Hellström,
Intel Graphics Development, dri-devel, Daniel Vetter,
Kenneth Graunke, mesa-dev, Daniel Vetter
On Tue, 20 Apr 2021 at 02:45, Matthew Auld <matthew.auld@intel.com> wrote:
>
> Add an entry for the new uAPI needed for DG1. Also add the overall
> upstream plan, including some notes for the TTM conversion.
>
> v2(Daniel):
> - include the overall upstreaming plan
> - add a note for mmap, there are differences here for TTM vs i915
> - bunch of other suggestions from Daniel
> v3:
> (Daniel)
> - add a note for set/get caching stuff
> - add some more docs for existing query and extensions stuff
> - add an actual code example for regions query
> - bunch of other stuff
> (Jason)
> - uAPI change(!):
> - try a simpler design with the placements extension
> - rather than have a generic setparam which can cover multiple
> use cases, have each extension be responsible for one thing
> only
> v4:
> (Daniel)
> - add some more notes for ttm conversion
> - bunch of other stuff
> (Jason)
> - uAPI change(!):
> - drop all the extra rsvd members for the region_query and
> region_info, just keep the bare minimum needed for padding
Staying out of the ioctl's being over engineering, I hope they have a
good future use case.
The plan seems like a good plan.
Acked-by: Dave Airlie <airlied@redhat.com>
Dave.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-04-23 6:25 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-19 16:44 [PATCH v4] drm/doc/rfc: i915 DG1 uAPI Matthew Auld
2021-04-19 16:44 ` [Intel-gfx] " Matthew Auld
2021-04-19 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/doc/rfc: i915 DG1 uAPI (rev3) Patchwork
2021-04-19 17:21 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-19 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-19 22:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-23 6:25 ` [PATCH v4] drm/doc/rfc: i915 DG1 uAPI Dave Airlie
2021-04-23 6:25 ` [Intel-gfx] " Dave Airlie
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