* [xlnx:master 11872/12154] arch/arm/mach-zynq/suspend.S:58: Error: selected processor does not support `movweq r3, #0xff00' in ARM mode
@ 2021-04-22 22:34 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2021-04-22 22:34 UTC (permalink / raw)
To: kbuild-all
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Hi Quanyang,
First bad commit (maybe != root cause):
tree: https://github.com/Xilinx/linux-xlnx master
head: bcd80b4c331c5d55de978ab0b2f6181a8aea3434
commit: dc5ecd46b5133ffcaa12eae5fb4414e9e95ff0e6 [11872/12154] arm: zynq: delete AFLAGS_suspend.o to fix compile warning
config: arm-allyesconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/Xilinx/linux-xlnx/commit/dc5ecd46b5133ffcaa12eae5fb4414e9e95ff0e6
git remote add xlnx https://github.com/Xilinx/linux-xlnx
git fetch --no-tags xlnx master
git checkout dc5ecd46b5133ffcaa12eae5fb4414e9e95ff0e6
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
arch/arm/mach-zynq/suspend.S: Assembler messages:
>> arch/arm/mach-zynq/suspend.S:58: Error: selected processor does not support `movweq r3,#0xff00' in ARM mode
>> arch/arm/mach-zynq/suspend.S:62: Error: selected processor does not support `movw r4,#0xfff0' in ARM mode
>> arch/arm/mach-zynq/suspend.S:63: Error: selected processor does not support `movt r4,#0x1f' in ARM mode
arch/arm/mach-zynq/suspend.S:66: Error: selected processor does not support `movweq r3,#0xff00' in ARM mode
>> arch/arm/mach-zynq/suspend.S:68: Error: selected processor does not support `dsb sy' in ARM mode
arch/arm/mach-zynq/suspend.S:73: Error: selected processor does not support `dsb sy' in ARM mode
arch/arm/mach-zynq/suspend.S:86: Error: selected processor does not support `dsb sy' in ARM mode
>> arch/arm/mach-zynq/suspend.S:91: Error: selected processor does not support `movwne r3,#0xff00' in ARM mode
>> arch/arm/mach-zynq/suspend.S:99: Error: selected processor does not support `dmb st' in ARM mode
arch/arm/mach-zynq/suspend.S:105: Error: selected processor does not support `dmb st' in ARM mode
arch/arm/mach-zynq/suspend.S:122: Error: selected processor does not support `dsb sy' in ARM mode
>> arch/arm/mach-zynq/suspend.S:123: Error: selected processor does not support `wfi' in ARM mode
arch/arm/mach-zynq/suspend.S:124: Error: selected processor does not support `dsb sy' in ARM mode
arch/arm/mach-zynq/suspend.S:138: Error: selected processor does not support `dsb sy' in ARM mode
arch/arm/mach-zynq/suspend.S:145: Error: selected processor does not support `dmb st' in ARM mode
arch/arm/mach-zynq/suspend.S:156: Error: selected processor does not support `dsb sy' in ARM mode
arch/arm/mach-zynq/suspend.S:163: Error: selected processor does not support `dmb st' in ARM mode
arch/arm/mach-zynq/suspend.S:170: Error: selected processor does not support `dmb st' in ARM mode
arch/arm/mach-zynq/suspend.S:176: Error: selected processor does not support `dsb sy' in ARM mode
vim +58 arch/arm/mach-zynq/suspend.S
a32e73f42fc702 Michal Simek 2017-08-07 38
a32e73f42fc702 Michal Simek 2017-08-07 39 .text
a32e73f42fc702 Michal Simek 2017-08-07 40 .align 3
a32e73f42fc702 Michal Simek 2017-08-07 41
a32e73f42fc702 Michal Simek 2017-08-07 42 /**
a32e73f42fc702 Michal Simek 2017-08-07 43 * zynq_sys_suspend - Enter suspend
a32e73f42fc702 Michal Simek 2017-08-07 44 * @ddrc_base: Base address of the DDRC
a32e73f42fc702 Michal Simek 2017-08-07 45 * @slcr_base: Base address of the SLCR
a32e73f42fc702 Michal Simek 2017-08-07 46 * Returns -1 if DRAM subsystem is not gated off, 0 otherwise.
a32e73f42fc702 Michal Simek 2017-08-07 47 *
a32e73f42fc702 Michal Simek 2017-08-07 48 * This function is moved into OCM and finishes the suspend operation. I.e. DDR
a32e73f42fc702 Michal Simek 2017-08-07 49 * related clocks are gated off and the DDR PLL is bypassed.
a32e73f42fc702 Michal Simek 2017-08-07 50 */
a32e73f42fc702 Michal Simek 2017-08-07 51 ENTRY(zynq_sys_suspend)
a32e73f42fc702 Michal Simek 2017-08-07 52 push {r4 - r7}
a32e73f42fc702 Michal Simek 2017-08-07 53
a32e73f42fc702 Michal Simek 2017-08-07 54 /* Check DDRC is in self-refresh mode */
a32e73f42fc702 Michal Simek 2017-08-07 55 ldr r2, [r0, #MODE_STS_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 56 and r2, #DDRC_STATUS_MASK
a32e73f42fc702 Michal Simek 2017-08-07 57 cmp r2, #DDRC_OPMODE_SR
a32e73f42fc702 Michal Simek 2017-08-07 @58 movweq r3, #0xff00
a32e73f42fc702 Michal Simek 2017-08-07 59 bne suspend
a32e73f42fc702 Michal Simek 2017-08-07 60
a32e73f42fc702 Michal Simek 2017-08-07 61 mov r3, #MAXTRIES
a32e73f42fc702 Michal Simek 2017-08-07 @62 movw r4, #0xfff0
a32e73f42fc702 Michal Simek 2017-08-07 @63 movt r4, #0x1f
a32e73f42fc702 Michal Simek 2017-08-07 64 /* Wait for command queue empty */
a32e73f42fc702 Michal Simek 2017-08-07 65 1: subs r3, #1
a32e73f42fc702 Michal Simek 2017-08-07 66 movweq r3, #0xff00
a32e73f42fc702 Michal Simek 2017-08-07 67 beq suspend
a32e73f42fc702 Michal Simek 2017-08-07 @68 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 69 ldr r2, [r0, #MODE_STS_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 70 ands r2, r4
a32e73f42fc702 Michal Simek 2017-08-07 71 bne 1b
a32e73f42fc702 Michal Simek 2017-08-07 72
a32e73f42fc702 Michal Simek 2017-08-07 73 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 74
a32e73f42fc702 Michal Simek 2017-08-07 75 /*
a32e73f42fc702 Michal Simek 2017-08-07 76 * Wait for DDRC pipeline/queues to drain.
a32e73f42fc702 Michal Simek 2017-08-07 77 * We should wait ~40 DDR cycles. DDR is still at full speed while the
a32e73f42fc702 Michal Simek 2017-08-07 78 * CPU might already run in PLL bypass mode. The fastest speed the CPU
a32e73f42fc702 Michal Simek 2017-08-07 79 * runs at is ~1 GHz ~ 2 * DDR speed.
a32e73f42fc702 Michal Simek 2017-08-07 80 */
a32e73f42fc702 Michal Simek 2017-08-07 81 mov r3, #160
a32e73f42fc702 Michal Simek 2017-08-07 82 1: nop
a32e73f42fc702 Michal Simek 2017-08-07 83 subs r3, #1
a32e73f42fc702 Michal Simek 2017-08-07 84 bne 1b
a32e73f42fc702 Michal Simek 2017-08-07 85
a32e73f42fc702 Michal Simek 2017-08-07 86 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 87
a32e73f42fc702 Michal Simek 2017-08-07 88 /* read back CAM status once more */
a32e73f42fc702 Michal Simek 2017-08-07 89 ldr r2, [r0, #MODE_STS_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 90 ands r2, r4
a32e73f42fc702 Michal Simek 2017-08-07 @91 movwne r3, #0xff00
a32e73f42fc702 Michal Simek 2017-08-07 92 bne suspend
a32e73f42fc702 Michal Simek 2017-08-07 93
a32e73f42fc702 Michal Simek 2017-08-07 94 /* Stop DDR clocks */
a32e73f42fc702 Michal Simek 2017-08-07 95 ldr r2, [r1, #DDR_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 96 bic r2, #DDRCLK_ENABLE_MASK
a32e73f42fc702 Michal Simek 2017-08-07 97 str r2, [r1, #DDR_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 98
a32e73f42fc702 Michal Simek 2017-08-07 @99 dmb st
a32e73f42fc702 Michal Simek 2017-08-07 100
a32e73f42fc702 Michal Simek 2017-08-07 101 ldr r2, [r1, #DCI_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 102 bic r2, #DCICLK_ENABLE_MASK
a32e73f42fc702 Michal Simek 2017-08-07 103 str r2, [r1, #DCI_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 104
a32e73f42fc702 Michal Simek 2017-08-07 105 dmb st
a32e73f42fc702 Michal Simek 2017-08-07 106
a32e73f42fc702 Michal Simek 2017-08-07 107 /* Bypass and powerdown DDR PLL */
a32e73f42fc702 Michal Simek 2017-08-07 108 ldr r2, [r1, #DDRPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 109 orr r2, #PLL_BYPASS_MASK
a32e73f42fc702 Michal Simek 2017-08-07 110 str r2, [r1, #DDRPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 111 orr r2, #(PLL_PWRDWN_MASK | PLL_RESET_MASK)
a32e73f42fc702 Michal Simek 2017-08-07 112 str r2, [r1, #DDRPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 113
a32e73f42fc702 Michal Simek 2017-08-07 114 /* Bypass and powerdown ARM PLL */
a32e73f42fc702 Michal Simek 2017-08-07 115 ldr r2, [r1, #ARMPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 116 orr r2, #PLL_BYPASS_MASK
a32e73f42fc702 Michal Simek 2017-08-07 117 str r2, [r1, #ARMPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 118 orr r2, #(PLL_PWRDWN_MASK | PLL_RESET_MASK)
a32e73f42fc702 Michal Simek 2017-08-07 119 str r2, [r1, #ARMPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 120
a32e73f42fc702 Michal Simek 2017-08-07 121 suspend:
a32e73f42fc702 Michal Simek 2017-08-07 122 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 @123 wfi
a32e73f42fc702 Michal Simek 2017-08-07 124 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 125 cmp r3, #0xff00
a32e73f42fc702 Michal Simek 2017-08-07 126 moveq r0, #-1
a32e73f42fc702 Michal Simek 2017-08-07 127 beq exit
a32e73f42fc702 Michal Simek 2017-08-07 128
a32e73f42fc702 Michal Simek 2017-08-07 129 /* Power up ARM PLL */
a32e73f42fc702 Michal Simek 2017-08-07 130 ldr r2, [r1, #ARMPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 131 bic r2, #(PLL_PWRDWN_MASK | PLL_RESET_MASK)
a32e73f42fc702 Michal Simek 2017-08-07 132 str r2, [r1, #ARMPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 133 /* wait for lock */
a32e73f42fc702 Michal Simek 2017-08-07 134 1: ldr r2, [r1, #PLLSTATUS_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 135 ands r2, #ARM_LOCK_MASK
a32e73f42fc702 Michal Simek 2017-08-07 136 beq 1b
a32e73f42fc702 Michal Simek 2017-08-07 137
a32e73f42fc702 Michal Simek 2017-08-07 138 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 139
a32e73f42fc702 Michal Simek 2017-08-07 140 /* Disable ARM PLL bypass */
a32e73f42fc702 Michal Simek 2017-08-07 141 ldr r2, [r1, #ARMPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 142 bic r2, #PLL_BYPASS_MASK
a32e73f42fc702 Michal Simek 2017-08-07 143 str r2, [r1, #ARMPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 144
a32e73f42fc702 Michal Simek 2017-08-07 145 dmb st
a32e73f42fc702 Michal Simek 2017-08-07 146
a32e73f42fc702 Michal Simek 2017-08-07 147 /* Power up DDR PLL */
a32e73f42fc702 Michal Simek 2017-08-07 148 ldr r2, [r1, #DDRPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 149 bic r2, #(PLL_PWRDWN_MASK | PLL_RESET_MASK)
a32e73f42fc702 Michal Simek 2017-08-07 150 str r2, [r1, #DDRPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 151 /* wait for lock */
a32e73f42fc702 Michal Simek 2017-08-07 152 1: ldr r2, [r1, #PLLSTATUS_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 153 ands r2, #DDR_LOCK_MASK
a32e73f42fc702 Michal Simek 2017-08-07 154 beq 1b
a32e73f42fc702 Michal Simek 2017-08-07 155
a32e73f42fc702 Michal Simek 2017-08-07 156 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 157
a32e73f42fc702 Michal Simek 2017-08-07 158 /* Disable DDR PLL bypass */
a32e73f42fc702 Michal Simek 2017-08-07 159 ldr r2, [r1, #DDRPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 160 bic r2, #PLL_BYPASS_MASK
a32e73f42fc702 Michal Simek 2017-08-07 161 str r2, [r1, #DDRPLL_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 162
a32e73f42fc702 Michal Simek 2017-08-07 163 dmb st
a32e73f42fc702 Michal Simek 2017-08-07 164
a32e73f42fc702 Michal Simek 2017-08-07 165 /* Start DDR clocks */
a32e73f42fc702 Michal Simek 2017-08-07 166 ldr r2, [r1, #DCI_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 167 orr r2, #DCICLK_ENABLE_MASK
a32e73f42fc702 Michal Simek 2017-08-07 168 str r2, [r1, #DCI_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 169
a32e73f42fc702 Michal Simek 2017-08-07 170 dmb st
a32e73f42fc702 Michal Simek 2017-08-07 171
a32e73f42fc702 Michal Simek 2017-08-07 172 ldr r2, [r1, #DDR_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 173 orr r2, #DDRCLK_ENABLE_MASK
a32e73f42fc702 Michal Simek 2017-08-07 174 str r2, [r1, #DDR_CLK_CTRL_OFFS]
a32e73f42fc702 Michal Simek 2017-08-07 175
a32e73f42fc702 Michal Simek 2017-08-07 176 dsb sy
a32e73f42fc702 Michal Simek 2017-08-07 177
a32e73f42fc702 Michal Simek 2017-08-07 178 mov r0, #0
a32e73f42fc702 Michal Simek 2017-08-07 179 exit: pop {r4 - r7}
a32e73f42fc702 Michal Simek 2017-08-07 180 bx lr
a32e73f42fc702 Michal Simek 2017-08-07 181
:::::: The code at line 58 was first introduced by commit
:::::: a32e73f42fc702335fee6a5e2a499ea696f5f9b8 arm: zynq: Suspend support
:::::: TO: Michal Simek <michal.simek@xilinx.com>
:::::: CC: Michal Simek <michal.simek@xilinx.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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2021-04-22 22:34 [xlnx:master 11872/12154] arch/arm/mach-zynq/suspend.S:58: Error: selected processor does not support `movweq r3, #0xff00' in ARM mode kernel test robot
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