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* [linux-next:master 14734/14867] drivers/i2c/busses/i2c-hisi.c:366:14: error: couldn't allocate output register for constraint 'x'
@ 2021-04-26  3:49 ` kernel test robot
  0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-04-26  3:49 UTC (permalink / raw)
  To: Wolfram Sang; +Cc: kbuild-all, clang-built-linux, Linux Memory Management List

[-- Attachment #1: Type: text/plain, Size: 6299 bytes --]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   e3d35712f85ac84fb06234848f6c043ab418cf8b
commit: 221cb2bcf451636463efeca4a7911005ebd1d8ac [14734/14867] Merge remote-tracking branch 'i2c/i2c/for-next'
config: mips-randconfig-r024-20210426 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 6fca189532511da1b48e8c0d9aad8ff2edca382d)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install mips cross compiling tool for clang build
        # apt-get install binutils-mips-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=221cb2bcf451636463efeca4a7911005ebd1d8ac
        git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
        git fetch --no-tags linux-next master
        git checkout 221cb2bcf451636463efeca4a7911005ebd1d8ac
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=mips 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/i2c/busses/i2c-hisi.c:366:14: error: couldn't allocate output register for constraint 'x'
           total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);
                       ^
   include/linux/math.h:42:2: note: expanded from macro 'DIV_ROUND_UP_ULL'
           DIV_ROUND_DOWN_ULL((unsigned long long)(ll) + (d) - 1, (d))
           ^
   include/linux/math.h:39:37: note: expanded from macro 'DIV_ROUND_DOWN_ULL'
           ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
                                              ^
   include/asm-generic/div64.h:245:11: note: expanded from macro 'do_div'
                   __rem = __div64_32(&(n), __base);       \
                           ^
   arch/mips/include/asm/div64.h:76:11: note: expanded from macro '__div64_32'
                   __asm__("divu   $0, %z1, %z2"                           \
                           ^
   drivers/i2c/busses/i2c-hisi.c:368:15: error: couldn't allocate output register for constraint 'x'
           t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor);
                        ^
   include/linux/math.h:42:2: note: expanded from macro 'DIV_ROUND_UP_ULL'
           DIV_ROUND_DOWN_ULL((unsigned long long)(ll) + (d) - 1, (d))
           ^
   include/linux/math.h:39:37: note: expanded from macro 'DIV_ROUND_DOWN_ULL'
           ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
                                              ^
   include/asm-generic/div64.h:245:11: note: expanded from macro 'do_div'
                   __rem = __div64_32(&(n), __base);       \
                           ^
   arch/mips/include/asm/div64.h:76:11: note: expanded from macro '__div64_32'
                   __asm__("divu   $0, %z1, %z2"                           \
                           ^
   2 errors generated.


vim +366 drivers/i2c/busses/i2c-hisi.c

d62fbdb99a8573 Yicong Yang 2021-04-08  351  
d62fbdb99a8573 Yicong Yang 2021-04-08  352  /*
d62fbdb99a8573 Yicong Yang 2021-04-08  353   * Helper function for calculating and configuring the HIGH and LOW
d62fbdb99a8573 Yicong Yang 2021-04-08  354   * periods of SCL clock. The caller will pass the ratio of the
d62fbdb99a8573 Yicong Yang 2021-04-08  355   * counts (divide / divisor) according to the target speed mode,
d62fbdb99a8573 Yicong Yang 2021-04-08  356   * and the target registers.
d62fbdb99a8573 Yicong Yang 2021-04-08  357   */
d62fbdb99a8573 Yicong Yang 2021-04-08  358  static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr,
d62fbdb99a8573 Yicong Yang 2021-04-08  359  			     u32 divide, u32 divisor,
d62fbdb99a8573 Yicong Yang 2021-04-08  360  			     u32 reg_hcnt, u32 reg_lcnt)
d62fbdb99a8573 Yicong Yang 2021-04-08  361  {
d62fbdb99a8573 Yicong Yang 2021-04-08  362  	u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  363  	u32 scl_hcnt, scl_lcnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  364  
d62fbdb99a8573 Yicong Yang 2021-04-08  365  	/* Total SCL clock cycles per speed period */
d62fbdb99a8573 Yicong Yang 2021-04-08 @366  	total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);
d62fbdb99a8573 Yicong Yang 2021-04-08  367  	/* Total HIGH level SCL clock cycles including edges */
d62fbdb99a8573 Yicong Yang 2021-04-08  368  	t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor);
d62fbdb99a8573 Yicong Yang 2021-04-08  369  	/* Total LOW level SCL clock cycles including edges */
d62fbdb99a8573 Yicong Yang 2021-04-08  370  	t_scl_lcnt = total_cnt - t_scl_hcnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  371  	/* Fall edge SCL clock cycles */
d62fbdb99a8573 Yicong Yang 2021-04-08  372  	scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz);
d62fbdb99a8573 Yicong Yang 2021-04-08  373  	/* Rise edge SCL clock cycles */
d62fbdb99a8573 Yicong Yang 2021-04-08  374  	scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz);
d62fbdb99a8573 Yicong Yang 2021-04-08  375  
d62fbdb99a8573 Yicong Yang 2021-04-08  376  	/* Calculated HIGH and LOW periods of SCL clock */
d62fbdb99a8573 Yicong Yang 2021-04-08  377  	scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  378  	scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  379  
d62fbdb99a8573 Yicong Yang 2021-04-08  380  	writel(scl_hcnt, ctlr->iobase + reg_hcnt);
d62fbdb99a8573 Yicong Yang 2021-04-08  381  	writel(scl_lcnt, ctlr->iobase + reg_lcnt);
d62fbdb99a8573 Yicong Yang 2021-04-08  382  }
d62fbdb99a8573 Yicong Yang 2021-04-08  383  

:::::: The code at line 366 was first introduced by commit
:::::: d62fbdb99a85730af408399bfae9fa2aa708c6f1 i2c: add support for HiSilicon I2C controller

:::::: TO: Yicong Yang <yangyicong@hisilicon.com>
:::::: CC: Wolfram Sang <wsa@kernel.org>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 27110 bytes --]

^ permalink raw reply	[flat|nested] 2+ messages in thread
* [linux-next:master 14734/14867] drivers/i2c/busses/i2c-hisi.c:366:14: error: couldn't allocate output register for constraint 'x'
@ 2021-04-26  3:49 ` kernel test robot
  0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2021-04-26  3:49 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 6401 bytes --]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   e3d35712f85ac84fb06234848f6c043ab418cf8b
commit: 221cb2bcf451636463efeca4a7911005ebd1d8ac [14734/14867] Merge remote-tracking branch 'i2c/i2c/for-next'
config: mips-randconfig-r024-20210426 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 6fca189532511da1b48e8c0d9aad8ff2edca382d)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install mips cross compiling tool for clang build
        # apt-get install binutils-mips-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=221cb2bcf451636463efeca4a7911005ebd1d8ac
        git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
        git fetch --no-tags linux-next master
        git checkout 221cb2bcf451636463efeca4a7911005ebd1d8ac
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=mips 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/i2c/busses/i2c-hisi.c:366:14: error: couldn't allocate output register for constraint 'x'
           total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);
                       ^
   include/linux/math.h:42:2: note: expanded from macro 'DIV_ROUND_UP_ULL'
           DIV_ROUND_DOWN_ULL((unsigned long long)(ll) + (d) - 1, (d))
           ^
   include/linux/math.h:39:37: note: expanded from macro 'DIV_ROUND_DOWN_ULL'
           ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
                                              ^
   include/asm-generic/div64.h:245:11: note: expanded from macro 'do_div'
                   __rem = __div64_32(&(n), __base);       \
                           ^
   arch/mips/include/asm/div64.h:76:11: note: expanded from macro '__div64_32'
                   __asm__("divu   $0, %z1, %z2"                           \
                           ^
   drivers/i2c/busses/i2c-hisi.c:368:15: error: couldn't allocate output register for constraint 'x'
           t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor);
                        ^
   include/linux/math.h:42:2: note: expanded from macro 'DIV_ROUND_UP_ULL'
           DIV_ROUND_DOWN_ULL((unsigned long long)(ll) + (d) - 1, (d))
           ^
   include/linux/math.h:39:37: note: expanded from macro 'DIV_ROUND_DOWN_ULL'
           ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
                                              ^
   include/asm-generic/div64.h:245:11: note: expanded from macro 'do_div'
                   __rem = __div64_32(&(n), __base);       \
                           ^
   arch/mips/include/asm/div64.h:76:11: note: expanded from macro '__div64_32'
                   __asm__("divu   $0, %z1, %z2"                           \
                           ^
   2 errors generated.


vim +366 drivers/i2c/busses/i2c-hisi.c

d62fbdb99a8573 Yicong Yang 2021-04-08  351  
d62fbdb99a8573 Yicong Yang 2021-04-08  352  /*
d62fbdb99a8573 Yicong Yang 2021-04-08  353   * Helper function for calculating and configuring the HIGH and LOW
d62fbdb99a8573 Yicong Yang 2021-04-08  354   * periods of SCL clock. The caller will pass the ratio of the
d62fbdb99a8573 Yicong Yang 2021-04-08  355   * counts (divide / divisor) according to the target speed mode,
d62fbdb99a8573 Yicong Yang 2021-04-08  356   * and the target registers.
d62fbdb99a8573 Yicong Yang 2021-04-08  357   */
d62fbdb99a8573 Yicong Yang 2021-04-08  358  static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr,
d62fbdb99a8573 Yicong Yang 2021-04-08  359  			     u32 divide, u32 divisor,
d62fbdb99a8573 Yicong Yang 2021-04-08  360  			     u32 reg_hcnt, u32 reg_lcnt)
d62fbdb99a8573 Yicong Yang 2021-04-08  361  {
d62fbdb99a8573 Yicong Yang 2021-04-08  362  	u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  363  	u32 scl_hcnt, scl_lcnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  364  
d62fbdb99a8573 Yicong Yang 2021-04-08  365  	/* Total SCL clock cycles per speed period */
d62fbdb99a8573 Yicong Yang 2021-04-08 @366  	total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);
d62fbdb99a8573 Yicong Yang 2021-04-08  367  	/* Total HIGH level SCL clock cycles including edges */
d62fbdb99a8573 Yicong Yang 2021-04-08  368  	t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor);
d62fbdb99a8573 Yicong Yang 2021-04-08  369  	/* Total LOW level SCL clock cycles including edges */
d62fbdb99a8573 Yicong Yang 2021-04-08  370  	t_scl_lcnt = total_cnt - t_scl_hcnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  371  	/* Fall edge SCL clock cycles */
d62fbdb99a8573 Yicong Yang 2021-04-08  372  	scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz);
d62fbdb99a8573 Yicong Yang 2021-04-08  373  	/* Rise edge SCL clock cycles */
d62fbdb99a8573 Yicong Yang 2021-04-08  374  	scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz);
d62fbdb99a8573 Yicong Yang 2021-04-08  375  
d62fbdb99a8573 Yicong Yang 2021-04-08  376  	/* Calculated HIGH and LOW periods of SCL clock */
d62fbdb99a8573 Yicong Yang 2021-04-08  377  	scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  378  	scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt;
d62fbdb99a8573 Yicong Yang 2021-04-08  379  
d62fbdb99a8573 Yicong Yang 2021-04-08  380  	writel(scl_hcnt, ctlr->iobase + reg_hcnt);
d62fbdb99a8573 Yicong Yang 2021-04-08  381  	writel(scl_lcnt, ctlr->iobase + reg_lcnt);
d62fbdb99a8573 Yicong Yang 2021-04-08  382  }
d62fbdb99a8573 Yicong Yang 2021-04-08  383  

:::::: The code at line 366 was first introduced by commit
:::::: d62fbdb99a85730af408399bfae9fa2aa708c6f1 i2c: add support for HiSilicon I2C controller

:::::: TO: Yicong Yang <yangyicong@hisilicon.com>
:::::: CC: Wolfram Sang <wsa@kernel.org>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 27110 bytes --]

^ permalink raw reply	[flat|nested] 2+ messages in thread
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2021-04-26  3:49 [linux-next:master 14734/14867] drivers/i2c/busses/i2c-hisi.c:366:14: error: couldn't allocate output register for constraint 'x' kernel test robot
2021-04-26  3:49 ` kernel test robot

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