From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair Francis <alistair.francis@wdc.com>, kupokupokupopo@gmail.com, palmer@dabbelt.com Subject: [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Date: Wed, 28 Apr 2021 07:18:45 +0300 [thread overview] Message-ID: <20210428041848.12982-4-space.monkey.delivers@gmail.com> (raw) In-Reply-To: <20210428041848.12982-1-space.monkey.delivers@gmail.com> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c04911ec05..0682410f5d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + if (riscv_has_ext(env, RVJ)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte); + switch (env->priv) { + case PRV_U: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", + env->upmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", + env->upmmask); + break; + case PRV_S: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", + env->spmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", + env->spmmask); + break; + case PRV_M: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", + env->mpmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", + env->mpmmask); + break; + default: + g_assert_not_reached(); + } + } #endif for (i = 0; i < 32; i++) { -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com> Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com> Subject: [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Date: Wed, 28 Apr 2021 07:18:45 +0300 [thread overview] Message-ID: <20210428041848.12982-4-space.monkey.delivers@gmail.com> (raw) In-Reply-To: <20210428041848.12982-1-space.monkey.delivers@gmail.com> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c04911ec05..0682410f5d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + if (riscv_has_ext(env, RVJ)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte); + switch (env->priv) { + case PRV_U: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", + env->upmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", + env->upmmask); + break; + case PRV_S: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", + env->spmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", + env->spmmask); + break; + case PRV_M: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", + env->mpmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", + env->mpmmask); + break; + default: + g_assert_not_reached(); + } + } #endif for (i = 0; i < 32; i++) { -- 2.20.1
next prev parent reply other threads:[~2021-04-28 4:22 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-28 4:18 [PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation Alexey Baturo 2021-04-28 4:18 ` Alexey Baturo 2021-04-28 4:18 ` [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo 2021-04-28 4:18 ` Alexey Baturo 2021-04-28 4:18 ` [PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo 2021-04-28 4:18 ` Alexey Baturo 2021-05-12 5:54 ` Alistair Francis 2021-04-28 4:18 ` Alexey Baturo [this message] 2021-04-28 4:18 ` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo 2021-04-28 4:18 ` [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo 2021-04-28 4:18 ` Alexey Baturo 2021-04-28 4:18 ` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo 2021-04-28 4:18 ` Alexey Baturo 2021-05-12 5:59 ` Alistair Francis 2021-04-28 4:18 ` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo 2021-04-28 4:18 ` Alexey Baturo -- strict thread matches above, loose matches on Subject: below -- 2021-04-27 22:06 [PATCH v8 0/6] RISC-V Pointer Masking implementation Alexey Baturo 2021-04-27 22:06 ` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo 2021-04-27 22:06 ` Alexey Baturo
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