* [PATCH 2/5] habanalabs: dynamic fw load reset protocol
2021-04-28 11:33 [PATCH 1/5] habanalabs: use common fw_version read Oded Gabbay
@ 2021-04-28 11:33 ` Oded Gabbay
2021-04-28 11:33 ` [PATCH 3/5] habanalabs: expose ASIC specific PCI info to common code Oded Gabbay
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Oded Gabbay @ 2021-04-28 11:33 UTC (permalink / raw)
To: linux-kernel; +Cc: Ohad Sharabi
From: Ohad Sharabi <osharabi@habana.ai>
First stage of the dynamic FW load protocol is to reset the protocol to
avoid residues from former load cycles.
Signed-off-by: Ohad Sharabi <osharabi@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
---
drivers/misc/habanalabs/common/firmware_if.c | 287 ++++++++++++++++++-
drivers/misc/habanalabs/common/habanalabs.h | 41 ++-
drivers/misc/habanalabs/gaudi/gaudi.c | 36 ++-
drivers/misc/habanalabs/goya/goya.c | 36 ++-
4 files changed, 360 insertions(+), 40 deletions(-)
diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c
index 29d15a051ab9..2a22ff9d4425 100644
--- a/drivers/misc/habanalabs/common/firmware_if.c
+++ b/drivers/misc/habanalabs/common/firmware_if.c
@@ -891,30 +891,32 @@ static int hl_read_device_fw_version(struct hl_device *hdev,
enum hl_fw_component fwc)
{
struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+ struct static_fw_load_mgr *static_loader;
const char *name;
u32 ver_off, limit;
char *dest;
+ static_loader = &hdev->fw_loader.static_loader;
+
switch (fwc) {
case FW_COMP_BOOT_FIT:
- ver_off = RREG32(fw_loader->boot_fit_version_offset_reg);
+ ver_off = RREG32(static_loader->boot_fit_version_offset_reg);
dest = hdev->asic_prop.uboot_ver;
name = "Boot-fit";
- limit = fw_loader->boot_fit_version_max_off;
+ limit = static_loader->boot_fit_version_max_off;
break;
case FW_COMP_PREBOOT:
- ver_off = RREG32(
- fw_loader->preboot_version_offset_reg);
+ ver_off = RREG32(static_loader->preboot_version_offset_reg);
dest = hdev->asic_prop.preboot_ver;
name = "Preboot";
- limit = fw_loader->preboot_version_max_off;
+ limit = static_loader->preboot_version_max_off;
break;
default:
dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
return -EIO;
}
- ver_off &= fw_loader->sram_offset_mask;
+ ver_off &= static_loader->sram_offset_mask;
if (ver_off < limit) {
memcpy_fromio(dest,
@@ -1018,25 +1020,262 @@ int hl_fw_read_preboot_status(struct hl_device *hdev, u32 cpu_boot_status_reg,
return -EINVAL;
}
-int hl_fw_init_cpu(struct hl_device *hdev)
+/* associate string with COMM status */
+static char *hl_dynamic_fw_status_str[COMMS_STS_INVLD_LAST] = {
+ [COMMS_STS_NOOP] = "NOOP",
+ [COMMS_STS_ACK] = "ACK",
+ [COMMS_STS_OK] = "OK",
+ [COMMS_STS_ERR] = "ERR",
+ [COMMS_STS_VALID_ERR] = "VALID_ERR",
+ [COMMS_STS_TIMEOUT_ERR] = "TIMEOUT_ERR",
+};
+
+/**
+ * hl_fw_dynamic_report_error_status - report error status
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @status: value of FW status register
+ * @expected_status: the expected status
+ */
+static void hl_fw_dynamic_report_error_status(struct hl_device *hdev,
+ u32 status,
+ enum comms_sts expected_status)
+{
+ enum comms_sts comm_status =
+ FIELD_GET(COMMS_STATUS_STATUS_MASK, status);
+
+ if (comm_status < COMMS_STS_INVLD_LAST)
+ dev_err(hdev->dev, "Device status %s, expected status: %s\n",
+ hl_dynamic_fw_status_str[comm_status],
+ hl_dynamic_fw_status_str[expected_status]);
+ else
+ dev_err(hdev->dev, "Device status unknown %d, expected status: %s\n",
+ comm_status,
+ hl_dynamic_fw_status_str[expected_status]);
+}
+
+/**
+ * hl_fw_dynamic_send_cmd - send LKD to FW cmd
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @lkd_cmd: LKD to FW cmd code
+ * @size: size of next FW component to be loaded (0 if not necessary)
+ *
+ * LDK to FW exact command layout is defined at struct comms_command.
+ * note: the size argument is used only when the next FW component should be
+ * loaded, otherwise it shall be 0. the size is used by the FW in later
+ * protocol stages and when sending only indicating the amount of memory
+ * to be allocated by the FW to receive the next boot component.
+ */
+static void hl_fw_dynamic_send_cmd(struct hl_device *hdev,
+ struct fw_load_mgr *fw_loader,
+ enum comms_cmd cmd, unsigned int size)
+{
+ struct comms_command lkd_cmd;
+
+ lkd_cmd.val = FIELD_PREP(COMMS_COMMAND_CMD_MASK, cmd);
+ lkd_cmd.val |= FIELD_PREP(COMMS_COMMAND_SIZE_MASK, size);
+
+ WREG32(fw_loader->kmd_msg_to_cpu_reg, lkd_cmd.val);
+}
+
+/**
+ * hl_fw_dynamic_wait_for_status - wait for status in dynamic FW load
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @expected_status: expected status to wait for
+ * @timeout: timeout for status wait
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * waiting for status from FW include polling the FW status register until
+ * expected status is received or timeout occurs (whatever occurs first).
+ */
+static int hl_fw_dynamic_wait_for_status(struct hl_device *hdev,
+ struct fw_load_mgr *fw_loader,
+ enum comms_sts expected_status,
+ u32 timeout)
+{
+ u32 status;
+ int rc;
+
+ /* Wait for expected status */
+ rc = hl_poll_timeout(
+ hdev,
+ fw_loader->cpu_cmd_status_to_host_reg,
+ status,
+ FIELD_GET(COMMS_STATUS_STATUS_MASK, status) == expected_status,
+ 10000,
+ timeout);
+
+ if (rc) {
+ hl_fw_dynamic_report_error_status(hdev, status,
+ expected_status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * hl_fw_dynamic_send_clear_cmd - send clear command to FW
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * after command cycle between LKD to FW CPU (i.e. LKD got an expected status
+ * from FW) we need to clear the CPU status register in order to avoid garbage
+ * between command cycles.
+ * This is done by sending clear command and polling the CPU to LKD status
+ * register to hold the status NOOP
+ */
+static int hl_fw_dynamic_send_clear_cmd(struct hl_device *hdev,
+ struct fw_load_mgr *fw_loader)
+{
+ hl_fw_dynamic_send_cmd(hdev, fw_loader, COMMS_CLR_STS, 0);
+
+ return hl_fw_dynamic_wait_for_status(hdev, fw_loader, COMMS_STS_NOOP,
+ fw_loader->cpu_timeout);
+}
+
+/**
+ * hl_fw_dynamic_send_protocol_cmd - send LKD to FW cmd and wait for ACK
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ * @lkd_cmd: LKD to FW cmd code
+ * @size: size of next FW component to be loaded (0 if not necessary)
+ * @wait_ok: if true also wait for OK response from FW
+ * @timeout: timeout for status wait
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * brief:
+ * when sending protocol command we have the following steps:
+ * - send clear (clear command and verify clear status register)
+ * - send the actual protocol command
+ * - wait for ACK on the protocol command
+ * - send clear
+ * - send NOOP
+ * if, in addition, the specific protocol command should wait for OK then:
+ * - wait for OK
+ * - send clear
+ * - send NOOP
+ *
+ * NOTES:
+ * send clear: this is necessary in order to clear the status register to avoid
+ * leftovers between command
+ * NOOP command: necessary to avoid loop on the clear command by the FW
+ */
+static int hl_fw_dynamic_send_protocol_cmd(struct hl_device *hdev,
+ struct fw_load_mgr *fw_loader,
+ enum comms_cmd cmd, unsigned int size,
+ bool wait_ok, u32 timeout)
+{
+ int rc;
+
+ /* first send clear command to clean former commands */
+ rc = hl_fw_dynamic_send_clear_cmd(hdev, fw_loader);
+
+ /* send the actual command */
+ hl_fw_dynamic_send_cmd(hdev, fw_loader, cmd, size);
+
+ /* wait for ACK for the command */
+ rc = hl_fw_dynamic_wait_for_status(hdev, fw_loader, COMMS_STS_ACK,
+ timeout);
+ if (rc)
+ return rc;
+
+ /* clear command to prepare for NOOP command */
+ rc = hl_fw_dynamic_send_clear_cmd(hdev, fw_loader);
+ if (rc)
+ return rc;
+
+ /* send the actual NOOP command */
+ hl_fw_dynamic_send_cmd(hdev, fw_loader, COMMS_NOOP, 0);
+
+ if (!wait_ok)
+ return 0;
+
+ rc = hl_fw_dynamic_wait_for_status(hdev, fw_loader, COMMS_STS_OK,
+ timeout);
+ if (rc)
+ return rc;
+
+ /* clear command to prepare for NOOP command */
+ rc = hl_fw_dynamic_send_clear_cmd(hdev, fw_loader);
+ if (rc)
+ return rc;
+
+ /* send the actual NOOP command */
+ hl_fw_dynamic_send_cmd(hdev, fw_loader, COMMS_NOOP, 0);
+
+ return 0;
+}
+
+/**
+ * hl_fw_dynamic_init_cpu - initialize the device CPU using dynamic protocol
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * brief: the dynamic protocol is master (LKD) slave (FW CPU) protocol.
+ * the communication is done using registers:
+ * - LKD command register
+ * - FW status register
+ * the protocol is race free. this goal is achieved by splitting the requests
+ * and response to known synchronization points between the LKD and the FW.
+ * each response to LKD request is known and bound to a predefined timeout.
+ * in case of timeout expiration without the desired status from FW- the
+ * protocol (and hence the boot) will fail.
+ */
+static int hl_fw_dynamic_init_cpu(struct hl_device *hdev,
+ struct fw_load_mgr *fw_loader)
+{
+ int rc;
+
+ rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_RST_STATE,
+ 0, true,
+ fw_loader->cpu_timeout);
+ return rc;
+}
+
+/**
+ * hl_fw_static_init_cpu - initialize the device CPU using static protocol
+ *
+ * @hdev: pointer to the habanalabs device structure
+ * @fw_loader: managing structure for loading device's FW
+ *
+ * @return 0 on success, otherwise non-zero error code
+ */
+static int hl_fw_static_init_cpu(struct hl_device *hdev,
+ struct fw_load_mgr *fw_loader)
{
u32 cpu_msg_status_reg, cpu_timeout, msg_to_cpu_reg, status;
u32 cpu_boot_status_reg, cpu_security_boot_status_reg;
struct asic_fixed_properties *prop = &hdev->asic_prop;
- struct fw_load_mgr *fw_loader;
+ struct static_fw_load_mgr *static_loader;
int rc;
if (!(hdev->fw_components & FW_TYPE_BOOT_CPU))
return 0;
- /* init loader parameters */
- fw_loader = &hdev->fw_loader;
- cpu_security_boot_status_reg = fw_loader->cpu_boot_status_reg;
+ /* init common loader parameters */
+ static_loader = &fw_loader->static_loader;
cpu_msg_status_reg = fw_loader->cpu_cmd_status_to_host_reg;
- cpu_boot_status_reg = fw_loader->cpu_boot_status_reg;
msg_to_cpu_reg = fw_loader->kmd_msg_to_cpu_reg;
cpu_timeout = fw_loader->cpu_timeout;
+ /* init static loader parameters */
+ cpu_security_boot_status_reg = static_loader->cpu_boot_status_reg;
+ cpu_boot_status_reg = static_loader->cpu_boot_status_reg;
+
dev_info(hdev->dev, "Going to wait for device boot (up to %lds)\n",
cpu_timeout / USEC_PER_SEC);
@@ -1187,7 +1426,7 @@ int hl_fw_init_cpu(struct hl_device *hdev)
goto out;
}
- rc = fw_read_errors(hdev, fw_loader->boot_err0_reg,
+ rc = fw_read_errors(hdev, fw_loader->static_loader.boot_err0_reg,
cpu_security_boot_status_reg);
if (rc)
return rc;
@@ -1217,8 +1456,28 @@ int hl_fw_init_cpu(struct hl_device *hdev)
return 0;
out:
- fw_read_errors(hdev, fw_loader->boot_err0_reg,
+ fw_read_errors(hdev, fw_loader->static_loader.boot_err0_reg,
cpu_security_boot_status_reg);
return rc;
}
+
+/**
+ * hl_fw_init_cpu - initialize the device CPU
+ *
+ * @hdev: pointer to the habanalabs device structure
+ *
+ * @return 0 on success, otherwise non-zero error code
+ *
+ * perform necessary initializations for device's CPU. takes into account if
+ * init protocol is static or dynamic.
+ */
+int hl_fw_init_cpu(struct hl_device *hdev)
+{
+ struct asic_fixed_properties *prop = &hdev->asic_prop;
+ struct fw_load_mgr *fw_loader = &hdev->fw_loader;
+
+ return prop->dynamic_fw_load ?
+ hl_fw_dynamic_init_cpu(hdev, fw_loader) :
+ hl_fw_static_init_cpu(hdev, fw_loader);
+}
diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h
index 1a822fd741d1..5df971e5c108 100644
--- a/drivers/misc/habanalabs/common/habanalabs.h
+++ b/drivers/misc/habanalabs/common/habanalabs.h
@@ -819,37 +819,58 @@ enum div_select_defs {
};
/**
- * struct fw_load_mgr - manager FW loading process
+ * struct static_fw_load_mgr - static FW load manager
* @preboot_version_max_off: max offset to preboot version
* @boot_fit_version_max_off: max offset to boot fit version
- * @kmd_msg_to_cpu_reg: register address for KDM->CPU messages
- * @cpu_cmd_status_to_host_reg: register address for CPU command status response
* @cpu_boot_status_reg: boot status register
* @cpu_boot_dev_status_reg: boot device status register
* @boot_err0_reg: boot error register
* @preboot_version_offset_reg: SRAM offset to preboot version register
* @boot_fit_version_offset_reg: SRAM offset to boot fit version register
* @sram_offset_mask: mask for getting offset into the SRAM
- * @cpu_timeout: CPU response timeout in usec
- * @boot_fit_timeout: Boot fit load timeout in usec
- * @skip_bmc: should BMC be skipped
- * @sram_bar_id: SRAM bar ID
*/
-struct fw_load_mgr {
+struct static_fw_load_mgr {
u64 preboot_version_max_off;
u64 boot_fit_version_max_off;
- u32 kmd_msg_to_cpu_reg;
- u32 cpu_cmd_status_to_host_reg;
u32 cpu_boot_status_reg;
u32 cpu_boot_dev_status_reg;
u32 boot_err0_reg;
u32 preboot_version_offset_reg;
u32 boot_fit_version_offset_reg;
u32 sram_offset_mask;
+};
+
+/**
+ * struct dynamic_fw_load_mgr - dynamic FW load manager
+ * TODO: currently empty, will be filled once boot stages implementation will
+ * progress.
+ */
+struct dynamic_fw_load_mgr {
+};
+
+/**
+ * struct fw_load_mgr - manager FW loading process
+ * @kmd_msg_to_cpu_reg: register address for KDM->CPU messages
+ * @cpu_cmd_status_to_host_reg: register address for CPU command status response
+ * @cpu_timeout: CPU response timeout in usec
+ * @boot_fit_timeout: Boot fit load timeout in usec
+ * @skip_bmc: should BMC be skipped
+ * @sram_bar_id: SRAM bar ID
+ * @static_loader: specific structure for static load
+ * @dynamic_loader: specific structure for dynamic load
+ */
+struct fw_load_mgr {
+ u32 kmd_msg_to_cpu_reg;
+ u32 cpu_cmd_status_to_host_reg;
u32 cpu_timeout;
u32 boot_fit_timeout;
u8 skip_bmc;
u8 sram_bar_id;
+
+ union {
+ struct static_fw_load_mgr static_loader;
+ struct dynamic_fw_load_mgr dynamic_loader;
+ };
};
/**
diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c
index 9e625ca94908..84c42868e7fd 100644
--- a/drivers/misc/habanalabs/gaudi/gaudi.c
+++ b/drivers/misc/habanalabs/gaudi/gaudi.c
@@ -3691,24 +3691,44 @@ static int gaudi_load_boot_fit_to_device(struct hl_device *hdev)
return hl_fw_load_fw_to_device(hdev, GAUDI_BOOT_FIT_FILE, dst, 0, 0);
}
+static void gaudi_init_dynamic_firmware_loader(struct hl_device *hdev)
+{
+
+}
+
+static void gaudi_init_static_firmware_loader(struct hl_device *hdev)
+{
+ struct static_fw_load_mgr *static_loader;
+
+ static_loader = &hdev->fw_loader.static_loader;
+
+ static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+ static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+ static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
+ static_loader->cpu_boot_dev_status_reg = mmCPU_BOOT_DEV_STS0;
+ static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
+ static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
+ static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
+ static_loader->sram_offset_mask = ~((u32)SRAM_BASE_ADDR);
+}
+
static void gaudi_init_firmware_loader(struct hl_device *hdev)
{
+ struct asic_fixed_properties *prop = &hdev->asic_prop;
struct fw_load_mgr *fw_loader = &hdev->fw_loader;
- fw_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
- fw_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+ /* fill common fields */
fw_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
fw_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
- fw_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
- fw_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
- fw_loader->sram_offset_mask = ~((u32)SRAM_BASE_ADDR);
fw_loader->cpu_timeout = GAUDI_CPU_TIMEOUT_USEC;
fw_loader->boot_fit_timeout = GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC;
fw_loader->skip_bmc = !hdev->bmc_enable;
- fw_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
- fw_loader->cpu_boot_dev_status_reg = mmCPU_BOOT_DEV_STS0;
- fw_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
fw_loader->sram_bar_id = SRAM_BAR_ID;
+
+ if (prop->dynamic_fw_load)
+ gaudi_init_dynamic_firmware_loader(hdev);
+ else
+ gaudi_init_static_firmware_loader(hdev);
}
static int gaudi_init_cpu(struct hl_device *hdev)
diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c
index dd55fec19e8d..dc5659340220 100644
--- a/drivers/misc/habanalabs/goya/goya.c
+++ b/drivers/misc/habanalabs/goya/goya.c
@@ -2402,24 +2402,44 @@ static int goya_load_boot_fit_to_device(struct hl_device *hdev)
return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
}
+static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
+{
+
+}
+
+static void goya_init_static_firmware_loader(struct hl_device *hdev)
+{
+ struct static_fw_load_mgr *static_loader;
+
+ static_loader = &hdev->fw_loader.static_loader;
+
+ static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+ static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+ static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
+ static_loader->cpu_boot_dev_status_reg = mmCPU_BOOT_DEV_STS0;
+ static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
+ static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
+ static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
+ static_loader->sram_offset_mask = ~((u32)SRAM_BASE_ADDR);
+}
+
static void goya_init_firmware_loader(struct hl_device *hdev)
{
+ struct asic_fixed_properties *prop = &hdev->asic_prop;
struct fw_load_mgr *fw_loader = &hdev->fw_loader;
- fw_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
- fw_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
+ /* fill common fields */
fw_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
fw_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
- fw_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
- fw_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
- fw_loader->sram_offset_mask = ~((u32)SRAM_BASE_ADDR);
fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
fw_loader->skip_bmc = false;
- fw_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
- fw_loader->cpu_boot_dev_status_reg = mmCPU_BOOT_DEV_STS0;
- fw_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
+
+ if (prop->dynamic_fw_load)
+ goya_init_dynamic_firmware_loader(hdev);
+ else
+ goya_init_static_firmware_loader(hdev);
}
static int goya_init_cpu(struct hl_device *hdev)
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/5] habanalabs: expose ASIC specific PCI info to common code
2021-04-28 11:33 [PATCH 1/5] habanalabs: use common fw_version read Oded Gabbay
2021-04-28 11:33 ` [PATCH 2/5] habanalabs: dynamic fw load reset protocol Oded Gabbay
@ 2021-04-28 11:33 ` Oded Gabbay
2021-04-28 11:33 ` [PATCH 4/5] habanalabs: update to latest f/w headers Oded Gabbay
2021-04-28 11:33 ` [PATCH 5/5] habanalabs: give FW a grace time for configuring iATU Oded Gabbay
3 siblings, 0 replies; 5+ messages in thread
From: Oded Gabbay @ 2021-04-28 11:33 UTC (permalink / raw)
To: linux-kernel; +Cc: Ohad Sharabi
From: Ohad Sharabi <osharabi@habana.ai>
LKD has interfaces in which it receives device address.
For instance the debugfs_read/write variants receives device address for
CFG/SRAM/DRAM for read/write and need to translate to the mapped PCI BAR
address.
In addition, the dynamic FW load protocol dictates that the address to
which the LKD will copy the image for the next FW component will be
received as a device address and can be placed either in SRAM or DRAM.
We need to distinguish those regions as the access methods to those
regions are different (in DRAM we possibly need to set the BAR base).
Looking forward this code will be used to remove duplicated code in the
debugfs_read/write that search the memory region for the input device
address.
Signed-off-by: Ohad Sharabi <osharabi@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
---
drivers/misc/habanalabs/common/habanalabs.h | 28 +++++++++++++++
drivers/misc/habanalabs/common/pci/pci.c | 26 ++++++++++++++
drivers/misc/habanalabs/gaudi/gaudi.c | 39 +++++++++++++++++++++
drivers/misc/habanalabs/goya/goya.c | 31 ++++++++++++++++
4 files changed, 124 insertions(+)
diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h
index 5df971e5c108..fff282774739 100644
--- a/drivers/misc/habanalabs/common/habanalabs.h
+++ b/drivers/misc/habanalabs/common/habanalabs.h
@@ -818,6 +818,30 @@ enum div_select_defs {
DIV_SEL_DIVIDED_PLL = 3,
};
+enum pci_region {
+ PCI_REGION_CFG,
+ PCI_REGION_SRAM,
+ PCI_REGION_DRAM,
+ PCI_REGION_SP_SRAM,
+ PCI_REGION_NUMBER,
+};
+
+/**
+ * struct pci_mem_region - describe memory region in a PCI bar
+ * @region_base: region base address
+ * @region_size: region size
+ * @offset_in_bar: region offset into the bar
+ * @bar_id: bar ID of the region
+ * @used: if used 1, otherwise 0
+ */
+struct pci_mem_region {
+ u64 region_base;
+ u64 region_size;
+ u32 offset_in_bar;
+ u8 bar_id;
+ u8 used;
+};
+
/**
* struct static_fw_load_mgr - static FW load manager
* @preboot_version_max_off: max offset to preboot version
@@ -2014,6 +2038,7 @@ struct hl_mmu_funcs {
* @mmu_priv: device-specific MMU data.
* @mmu_func: device-related MMU functions.
* @fw_loader: FW loader manager.
+ * @pci_mem_region: array of memory regions in the PCI
* @dram_used_mem: current DRAM memory consumption.
* @timeout_jiffies: device CS timeout value.
* @max_power: the max power of the device, as configured by the sysadmin. This
@@ -2135,6 +2160,8 @@ struct hl_device {
struct fw_load_mgr fw_loader;
+ struct pci_mem_region pci_mem_region[PCI_REGION_NUMBER];
+
atomic64_t dram_used_mem;
u64 timeout_jiffies;
u64 max_power;
@@ -2467,6 +2494,7 @@ int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
struct hl_inbound_pci_region *pci_region);
int hl_pci_set_outbound_region(struct hl_device *hdev,
struct hl_outbound_pci_region *pci_region);
+enum pci_region hl_get_pci_memory_region(struct hl_device *hdev, u64 addr);
int hl_pci_init(struct hl_device *hdev);
void hl_pci_fini(struct hl_device *hdev);
diff --git a/drivers/misc/habanalabs/common/pci/pci.c b/drivers/misc/habanalabs/common/pci/pci.c
index 5d07ca53d9ce..9ef6c46a3146 100644
--- a/drivers/misc/habanalabs/common/pci/pci.c
+++ b/drivers/misc/habanalabs/common/pci/pci.c
@@ -359,6 +359,32 @@ int hl_pci_set_outbound_region(struct hl_device *hdev,
return rc;
}
+/**
+ * hl_get_pci_memory_region() - get PCI region for given address
+ * @hdev: Pointer to hl_device structure.
+ * @addr: device address
+ *
+ * @return region index on success, otherwise PCI_REGION_NUMBER (invalid
+ * region index)
+ */
+enum pci_region hl_get_pci_memory_region(struct hl_device *hdev, u64 addr)
+{
+ int i;
+
+ for (i = 0 ; i < PCI_REGION_NUMBER ; i++) {
+ struct pci_mem_region *region = &hdev->pci_mem_region[i];
+
+ if (!region->used)
+ continue;
+
+ if ((addr >= region->region_base) &&
+ (addr < region->region_base + region->region_size))
+ return i;
+ }
+
+ return PCI_REGION_NUMBER;
+}
+
/**
* hl_pci_init() - PCI initialization code.
* @hdev: Pointer to hl_device structure.
diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c
index 84c42868e7fd..0b03c6946748 100644
--- a/drivers/misc/habanalabs/gaudi/gaudi.c
+++ b/drivers/misc/habanalabs/gaudi/gaudi.c
@@ -1590,6 +1590,43 @@ static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev)
return rc;
}
+static void gaudi_set_pci_memory_regions(struct hl_device *hdev)
+{
+ struct pci_mem_region *region;
+
+ /* CFG */
+ region = &hdev->pci_mem_region[PCI_REGION_CFG];
+ region->region_base = CFG_BASE;
+ region->region_size = CFG_SIZE;
+ region->offset_in_bar = CFG_BASE - SPI_FLASH_BASE_ADDR;
+ region->bar_id = CFG_BAR_ID;
+ region->used = 1;
+
+ /* SRAM */
+ region = &hdev->pci_mem_region[PCI_REGION_SRAM];
+ region->region_base = SRAM_BASE_ADDR;
+ region->region_size = SRAM_SIZE;
+ region->offset_in_bar = 0;
+ region->bar_id = SRAM_BAR_ID;
+ region->used = 1;
+
+ /* DRAM */
+ region = &hdev->pci_mem_region[PCI_REGION_DRAM];
+ region->region_base = DRAM_PHYS_BASE;
+ region->region_size = hdev->asic_prop.dram_size;
+ region->offset_in_bar = 0;
+ region->bar_id = HBM_BAR_ID;
+ region->used = 1;
+
+ /* SP SRAM */
+ region = &hdev->pci_mem_region[PCI_REGION_SP_SRAM];
+ region->region_base = PSOC_SCRATCHPAD_ADDR;
+ region->region_size = PSOC_SCRATCHPAD_SIZE;
+ region->offset_in_bar = PSOC_SCRATCHPAD_ADDR - SPI_FLASH_BASE_ADDR;
+ region->bar_id = CFG_BAR_ID;
+ region->used = 1;
+}
+
static int gaudi_sw_init(struct hl_device *hdev)
{
struct gaudi_device *gaudi;
@@ -1664,6 +1701,8 @@ static int gaudi_sw_init(struct hl_device *hdev)
hdev->supports_coresight = true;
hdev->supports_staged_submission = true;
+ gaudi_set_pci_memory_regions(hdev);
+
return 0;
free_cpu_accessible_dma_pool:
diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c
index dc5659340220..c3a241227fe0 100644
--- a/drivers/misc/habanalabs/goya/goya.c
+++ b/drivers/misc/habanalabs/goya/goya.c
@@ -849,6 +849,35 @@ void goya_late_fini(struct hl_device *hdev)
hdev->hl_chip_info->info = NULL;
}
+static void goya_set_pci_memory_regions(struct hl_device *hdev)
+{
+ struct pci_mem_region *region;
+
+ /* CFG */
+ region = &hdev->pci_mem_region[PCI_REGION_CFG];
+ region->region_base = CFG_BASE;
+ region->region_size = CFG_SIZE;
+ region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
+ region->bar_id = SRAM_CFG_BAR_ID;
+ region->used = 1;
+
+ /* SRAM */
+ region = &hdev->pci_mem_region[PCI_REGION_SRAM];
+ region->region_base = SRAM_BASE_ADDR;
+ region->region_size = SRAM_SIZE;
+ region->offset_in_bar = 0;
+ region->bar_id = SRAM_CFG_BAR_ID;
+ region->used = 1;
+
+ /* DRAM */
+ region = &hdev->pci_mem_region[PCI_REGION_DRAM];
+ region->region_base = DRAM_PHYS_BASE;
+ region->region_size = hdev->asic_prop.dram_size;
+ region->offset_in_bar = 0;
+ region->bar_id = DDR_BAR_ID;
+ region->used = 1;
+}
+
/*
* goya_sw_init - Goya software initialization code
*
@@ -919,6 +948,8 @@ static int goya_sw_init(struct hl_device *hdev)
hdev->supports_coresight = true;
hdev->supports_soft_reset = true;
+ goya_set_pci_memory_regions(hdev);
+
return 0;
free_cpu_accessible_dma_pool:
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 4/5] habanalabs: update to latest f/w headers
2021-04-28 11:33 [PATCH 1/5] habanalabs: use common fw_version read Oded Gabbay
2021-04-28 11:33 ` [PATCH 2/5] habanalabs: dynamic fw load reset protocol Oded Gabbay
2021-04-28 11:33 ` [PATCH 3/5] habanalabs: expose ASIC specific PCI info to common code Oded Gabbay
@ 2021-04-28 11:33 ` Oded Gabbay
2021-04-28 11:33 ` [PATCH 5/5] habanalabs: give FW a grace time for configuring iATU Oded Gabbay
3 siblings, 0 replies; 5+ messages in thread
From: Oded Gabbay @ 2021-04-28 11:33 UTC (permalink / raw)
To: linux-kernel
Update the common and GAUDI firmware header files to the latest version
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
---
.../misc/habanalabs/include/common/cpucp_if.h | 3 +
.../habanalabs/include/common/hl_boot_if.h | 80 ++++++++++---------
.../habanalabs/include/gaudi/gaudi_fw_if.h | 39 +++++++++
3 files changed, 83 insertions(+), 39 deletions(-)
diff --git a/drivers/misc/habanalabs/include/common/cpucp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h
index bf10ca8d2457..4f1123102968 100644
--- a/drivers/misc/habanalabs/include/common/cpucp_if.h
+++ b/drivers/misc/habanalabs/include/common/cpucp_if.h
@@ -631,6 +631,8 @@ struct cpucp_security_info {
* @card_name: card name that will be displayed in HWMON subsystem on the host
* @sec_info: security information
* @pll_map: Bit map of supported PLLs for current ASIC version.
+ * @mme_binning_mask: MME binning mask,
+ * (0 = functional, 1 = binned)
*/
struct cpucp_info {
struct cpucp_sensor sensors[CPUCP_MAX_SENSORS];
@@ -653,6 +655,7 @@ struct cpucp_info {
struct cpucp_security_info sec_info;
__le32 reserved6;
__u8 pll_map[PLL_MAP_LEN];
+ __le64 mme_binning_mask;
};
struct cpucp_mac_addr {
diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h
index 84c14688d69a..0fd749c92fc2 100644
--- a/drivers/misc/habanalabs/include/common/hl_boot_if.h
+++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h
@@ -99,6 +99,7 @@
#define CPU_BOOT_ERR0_PLL_FAIL (1 << 12)
#define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << 13)
#define CPU_BOOT_ERR0_ENABLED (1 << 31)
+#define CPU_BOOT_ERR1_ENABLED (1 << 31)
/*
* BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
@@ -219,6 +220,7 @@
#define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << 17)
#define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << 19)
#define CPU_BOOT_DEV_STS0_ENABLED (1 << 31)
+#define CPU_BOOT_DEV_STS1_ENABLED (1 << 31)
enum cpu_boot_status {
CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */
@@ -264,33 +266,33 @@ enum cpu_msg_status {
/* communication registers mapping - consider ABI when changing */
struct cpu_dyn_regs {
- uint32_t cpu_pq_base_addr_low;
- uint32_t cpu_pq_base_addr_high;
- uint32_t cpu_pq_length;
- uint32_t cpu_pq_init_status;
- uint32_t cpu_eq_base_addr_low;
- uint32_t cpu_eq_base_addr_high;
- uint32_t cpu_eq_length;
- uint32_t cpu_eq_ci;
- uint32_t cpu_cq_base_addr_low;
- uint32_t cpu_cq_base_addr_high;
- uint32_t cpu_cq_length;
- uint32_t cpu_pf_pq_pi;
- uint32_t cpu_boot_dev_sts0;
- uint32_t cpu_boot_dev_sts1;
- uint32_t cpu_boot_err0;
- uint32_t cpu_boot_err1;
- uint32_t cpu_boot_status;
- uint32_t fw_upd_sts;
- uint32_t fw_upd_cmd;
- uint32_t fw_upd_pending_sts;
- uint32_t fuse_ver_offset;
- uint32_t preboot_ver_offset;
- uint32_t uboot_ver_offset;
- uint32_t hw_state;
- uint32_t kmd_msg_to_cpu;
- uint32_t cpu_cmd_status_to_host;
- uint32_t reserved1[32]; /* reserve for future use */
+ __le32 cpu_pq_base_addr_low;
+ __le32 cpu_pq_base_addr_high;
+ __le32 cpu_pq_length;
+ __le32 cpu_pq_init_status;
+ __le32 cpu_eq_base_addr_low;
+ __le32 cpu_eq_base_addr_high;
+ __le32 cpu_eq_length;
+ __le32 cpu_eq_ci;
+ __le32 cpu_cq_base_addr_low;
+ __le32 cpu_cq_base_addr_high;
+ __le32 cpu_cq_length;
+ __le32 cpu_pf_pq_pi;
+ __le32 cpu_boot_dev_sts0;
+ __le32 cpu_boot_dev_sts1;
+ __le32 cpu_boot_err0;
+ __le32 cpu_boot_err1;
+ __le32 cpu_boot_status;
+ __le32 fw_upd_sts;
+ __le32 fw_upd_cmd;
+ __le32 fw_upd_pending_sts;
+ __le32 fuse_ver_offset;
+ __le32 preboot_ver_offset;
+ __le32 uboot_ver_offset;
+ __le32 hw_state;
+ __le32 kmd_msg_to_cpu;
+ __le32 cpu_cmd_status_to_host;
+ __le32 reserved1[32]; /* reserve for future use */
};
/* HCDM - Habana Communications Descriptor Magic */
@@ -299,11 +301,11 @@ struct cpu_dyn_regs {
/* this is the comms descriptor header - meta data */
struct comms_desc_header {
- uint32_t magic; /* magic for validation */
- uint32_t crc32; /* CRC32 of the descriptor w/o header */
- uint16_t size; /* size of the descriptor w/o header */
- uint8_t version; /* descriptor version */
- uint8_t reserved[5]; /* pad to 64 bit */
+ __le32 magic; /* magic for validation */
+ __le32 crc32; /* CRC32 of the descriptor w/o header */
+ __le16 size; /* size of the descriptor w/o header */
+ __u8 version; /* descriptor version */
+ __u8 reserved[5]; /* pad to 64 bit */
};
/* this is the main FW descriptor - consider ABI when changing */
@@ -314,7 +316,7 @@ struct lkd_fw_comms_desc {
char cur_fw_ver[VERSION_MAX_LEN];
/* can be used for 1 more version w/o ABI change */
char reserved0[VERSION_MAX_LEN];
- uint64_t img_addr; /* address for next FW component load */
+ __le64 img_addr; /* address for next FW component load */
};
/*
@@ -386,11 +388,11 @@ enum comms_cmd {
struct comms_command {
union { /* bit fields are only for FW use */
struct {
- unsigned int size :25; /* 32MB max. */
- unsigned int reserved :2;
+ u32 size :25; /* 32MB max. */
+ u32 reserved :2;
enum comms_cmd cmd :5; /* 32 commands */
};
- unsigned int val;
+ __le32 val;
};
};
@@ -449,11 +451,11 @@ enum comms_ram_types {
struct comms_status {
union { /* bit fields are only for FW use */
struct {
- unsigned int offset :26;
- unsigned int ram_type :2;
+ u32 offset :26;
+ enum comms_ram_types ram_type :2;
enum comms_sts status :4; /* 16 statuses */
};
- unsigned int val;
+ __le32 val;
};
};
diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h
index a9f51f9f9e92..a4afb984d0ae 100644
--- a/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h
+++ b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h
@@ -27,6 +27,7 @@ enum gaudi_nic_axi_error {
TXE,
QPC_RESP,
NON_AXI_ERR,
+ TMR,
};
/*
@@ -42,6 +43,44 @@ struct eq_nic_sei_event {
__u8 pad[6];
};
+/*
+ * struct gaudi_nic_status - describes the status of a NIC port.
+ * @port: NIC port index.
+ * @bad_format_cnt: e.g. CRC.
+ * @responder_out_of_sequence_psn_cnt: e.g NAK.
+ * @high_ber_reinit_cnt: link reinit due to high BER.
+ * @correctable_err_cnt: e.g. bit-flip.
+ * @uncorrectable_err_cnt: e.g. MAC errors.
+ * @retraining_cnt: re-training counter.
+ * @up: is port up.
+ * @pcs_link: has PCS link.
+ * @phy_ready: is PHY ready.
+ * @auto_neg: is Autoneg enabled.
+ */
+struct gaudi_nic_status {
+ __u32 port;
+ __u32 bad_format_cnt;
+ __u32 responder_out_of_sequence_psn_cnt;
+ __u32 high_ber_reinit;
+ __u32 correctable_err_cnt;
+ __u32 uncorrectable_err_cnt;
+ __u32 retraining_cnt;
+ __u8 up;
+ __u8 pcs_link;
+ __u8 phy_ready;
+ __u8 auto_neg;
+};
+
+struct gaudi_flops_2_data {
+ union {
+ struct {
+ __u32 spsram_init_done : 1;
+ __u32 reserved : 31;
+ };
+ __u32 data;
+ };
+};
+
#define GAUDI_PLL_FREQ_LOW 200000000 /* 200 MHz */
#endif /* GAUDI_FW_IF_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread