* [PATCH v2 01/13] target/arm: Move constant expanders to translate.h
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 02/13] target/arm: Share unallocated_encoding() and gen_exception_insn() Peter Maydell
` (11 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Some of the constant expanders defined in translate.c are generically
useful and will be used by the separate C files for VFP and Neon once
they are created; move the expander definitions to translate.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 24 ++++++++++++++++++++++++
target/arm/translate.c | 24 ------------------------
2 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index ccf60c96d84..b5b21619597 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -118,6 +118,30 @@ extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
extern TCGv_i64 cpu_exclusive_addr;
extern TCGv_i64 cpu_exclusive_val;
+/*
+ * Constant expanders for the decoders.
+ */
+
+static inline int negate(DisasContext *s, int x)
+{
+ return -x;
+}
+
+static inline int plus_2(DisasContext *s, int x)
+{
+ return x + 2;
+}
+
+static inline int times_2(DisasContext *s, int x)
+{
+ return x * 2;
+}
+
+static inline int times_4(DisasContext *s, int x)
+{
+ return x * 4;
+}
+
static inline int arm_dc_feature(DisasContext *dc, int feature)
{
return (dc->features & (1ULL << feature)) != 0;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 43ff0d4b8ac..bb9e228d1ae 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -109,30 +109,6 @@ static void arm_gen_condlabel(DisasContext *s)
}
}
-/*
- * Constant expanders for the decoders.
- */
-
-static int negate(DisasContext *s, int x)
-{
- return -x;
-}
-
-static int plus_2(DisasContext *s, int x)
-{
- return x + 2;
-}
-
-static int times_2(DisasContext *s, int x)
-{
- return x * 2;
-}
-
-static int times_4(DisasContext *s, int x)
-{
- return x * 4;
-}
-
/* Flags for the disas_set_da_iss info argument:
* lower bits hold the Rt register number, higher bits are flags.
*/
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 02/13] target/arm: Share unallocated_encoding() and gen_exception_insn()
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
2021-04-30 13:27 ` [PATCH v2 01/13] target/arm: Move constant expanders to translate.h Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 03/13] target/arm: Make functions used by m-nocp global Peter Maydell
` (10 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
The unallocated_encoding() function is the same in both
translate-a64.c and translate.c; make the translate.c function global
and drop the translate-a64.c version. To do this we need to also
share gen_exception_insn(), which currently exists in two slightly
different versions for A32 and A64: merge those into a single
function that can work for both.
This will be useful for splitting up translate.c, which will require
unallocated_encoding() to no longer be file-local. It's also
hopefully less confusing to have only one version of the function
rather than two.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.h | 2 --
target/arm/translate.h | 3 +++
target/arm/translate-a64.c | 15 ---------------
target/arm/translate.c | 14 +++++++++-----
4 files changed, 12 insertions(+), 22 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 868d3550486..89437276e70 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -18,8 +18,6 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H
-void unallocated_encoding(DisasContext *s);
-
#define unsupported_encoding(s, insn) \
do { \
qemu_log_mask(LOG_UNIMP, \
diff --git a/target/arm/translate.h b/target/arm/translate.h
index b5b21619597..8130a3be29d 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -229,6 +229,9 @@ void arm_free_cc(DisasCompare *cmp);
void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
void arm_gen_test_cc(int cc, TCGLabel *label);
MemOp pow2_align(unsigned i);
+void unallocated_encoding(DisasContext *s);
+void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
+ uint32_t syn, uint32_t target_el);
/* Return state of Alternate Half-precision flag, caller frees result */
static inline TCGv_i32 get_ahp_flag(void)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 95897e63af0..0c80d0b5055 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -359,14 +359,6 @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
s->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
- uint32_t syndrome, uint32_t target_el)
-{
- gen_a64_set_pc_im(pc);
- gen_exception(excp, syndrome, target_el);
- s->base.is_jmp = DISAS_NORETURN;
-}
-
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
{
TCGv_i32 tcg_syn;
@@ -437,13 +429,6 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
}
}
-void unallocated_encoding(DisasContext *s)
-{
- /* Unallocated and reserved encodings are uncategorized */
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
-}
-
static void init_tmp_a64_array(DisasContext *s)
{
#ifdef CONFIG_DEBUG_TCG
diff --git a/target/arm/translate.c b/target/arm/translate.c
index bb9e228d1ae..8b71b1c41b6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1069,11 +1069,15 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
s->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
- int syn, uint32_t target_el)
+void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
+ uint32_t syn, uint32_t target_el)
{
- gen_set_condexec(s);
- gen_set_pc_im(s, pc);
+ if (s->aarch64) {
+ gen_a64_set_pc_im(pc);
+ } else {
+ gen_set_condexec(s);
+ gen_set_pc_im(s, pc);
+ }
gen_exception(excp, syn, target_el);
s->base.is_jmp = DISAS_NORETURN;
}
@@ -1090,7 +1094,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
s->base.is_jmp = DISAS_NORETURN;
}
-static void unallocated_encoding(DisasContext *s)
+void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 03/13] target/arm: Make functions used by m-nocp global
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
2021-04-30 13:27 ` [PATCH v2 01/13] target/arm: Move constant expanders to translate.h Peter Maydell
2021-04-30 13:27 ` [PATCH v2 02/13] target/arm: Share unallocated_encoding() and gen_exception_insn() Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 04/13] target/arm: Split m-nocp trans functions into their own file Peter Maydell
` (9 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
We want to split out the .c.inc files which are currently included
into translate.c so they are separate compilation units. To do this
we need to make some functions which are currently file-local to
translate.c have global scope; create a translate-a32.h paralleling
the existing translate-a64.h as a place for these declarations to
live, so that code moved into the new compilation units can call
them.
The functions made global here are those required by the
m-nocp.decode functions, except that I have converted the whole
family of {read,write}_neon_element* and also both the load_cpu and
store_cpu functions for consistency, even though m-nocp only wants a
few functions from each.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a32.h | 57 ++++++++++++++++++++++++++++++++++
target/arm/translate.c | 39 +++++------------------
target/arm/translate-vfp.c.inc | 2 +-
3 files changed, 65 insertions(+), 33 deletions(-)
create mode 100644 target/arm/translate-a32.h
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
new file mode 100644
index 00000000000..c5d937b27e8
--- /dev/null
+++ b/target/arm/translate-a32.h
@@ -0,0 +1,57 @@
+/*
+ * AArch32 translation, common definitions.
+ *
+ * Copyright (c) 2021 Linaro, Ltd.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARM_TRANSLATE_A64_H
+#define TARGET_ARM_TRANSLATE_A64_H
+
+void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
+void arm_gen_condlabel(DisasContext *s);
+bool vfp_access_check(DisasContext *s);
+void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
+void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
+void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
+void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
+
+static inline TCGv_i32 load_cpu_offset(int offset)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_ld_i32(tmp, cpu_env, offset);
+ return tmp;
+}
+
+#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
+
+static inline void store_cpu_offset(TCGv_i32 var, int offset)
+{
+ tcg_gen_st_i32(var, cpu_env, offset);
+ tcg_temp_free_i32(var);
+}
+
+#define store_cpu_field(var, name) \
+ store_cpu_offset(var, offsetof(CPUARMState, name))
+
+/* Create a new temporary and set it to the value of a CPU register. */
+static inline TCGv_i32 load_reg(DisasContext *s, int reg)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ load_reg_var(s, tmp, reg);
+ return tmp;
+}
+
+#endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8b71b1c41b6..3c1d52279bc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -50,6 +50,7 @@
#define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8)
#include "translate.h"
+#include "translate-a32.h"
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
@@ -101,7 +102,7 @@ void arm_translate_init(void)
}
/* Generate a label used for skipping this instruction */
-static void arm_gen_condlabel(DisasContext *s)
+void arm_gen_condlabel(DisasContext *s)
{
if (!s->condjmp) {
s->condlabel = gen_new_label();
@@ -187,24 +188,6 @@ static inline int get_a32_user_mem_index(DisasContext *s)
}
}
-static inline TCGv_i32 load_cpu_offset(int offset)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp, cpu_env, offset);
- return tmp;
-}
-
-#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
-
-static inline void store_cpu_offset(TCGv_i32 var, int offset)
-{
- tcg_gen_st_i32(var, cpu_env, offset);
- tcg_temp_free_i32(var);
-}
-
-#define store_cpu_field(var, name) \
- store_cpu_offset(var, offsetof(CPUARMState, name))
-
/* The architectural value of PC. */
static uint32_t read_pc(DisasContext *s)
{
@@ -212,7 +195,7 @@ static uint32_t read_pc(DisasContext *s)
}
/* Set a variable to the value of a CPU register. */
-static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
+void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
{
if (reg == 15) {
tcg_gen_movi_i32(var, read_pc(s));
@@ -221,14 +204,6 @@ static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
}
}
-/* Create a new temporary and set it to the value of a CPU register. */
-static inline TCGv_i32 load_reg(DisasContext *s, int reg)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- load_reg_var(s, tmp, reg);
- return tmp;
-}
-
/*
* Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
* This is used for load/store for which use of PC implies (literal),
@@ -1208,7 +1183,7 @@ static inline void vfp_store_reg32(TCGv_i32 var, int reg)
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
}
-static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
+void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
{
long off = neon_element_offset(reg, ele, memop);
@@ -1234,7 +1209,7 @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
}
}
-static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
+void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
{
long off = neon_element_offset(reg, ele, memop);
@@ -1253,7 +1228,7 @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
}
}
-static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
+void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
{
long off = neon_element_offset(reg, ele, memop);
@@ -1272,7 +1247,7 @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
}
}
-static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
+void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
{
long off = neon_element_offset(reg, ele, memop);
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index e20d9c7ba66..c368ada877b 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -191,7 +191,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
* The most usual kind of VFP access check, for everything except
* FMXR/FMRX to the always-available special registers.
*/
-static bool vfp_access_check(DisasContext *s)
+bool vfp_access_check(DisasContext *s)
{
return full_vfp_access_check(s, false);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 04/13] target/arm: Split m-nocp trans functions into their own file
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (2 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 03/13] target/arm: Make functions used by m-nocp global Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h Peter Maydell
` (8 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Currently the trans functions for m-nocp.decode all live in
translate-vfp.inc.c; move them out into their own translation unit,
translate-m-nocp.c.
The trans_* functions here are pure code motion with no changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a32.h | 3 +
target/arm/translate-m-nocp.c | 221 +++++++++++++++++++++++++++++++++
target/arm/translate.c | 1 -
target/arm/translate-vfp.c.inc | 196 -----------------------------
target/arm/meson.build | 3 +-
5 files changed, 226 insertions(+), 198 deletions(-)
create mode 100644 target/arm/translate-m-nocp.c
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index c5d937b27e8..cb451f70a42 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -20,6 +20,9 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H
+/* Prototypes for autogenerated disassembler functions */
+bool disas_m_nocp(DisasContext *dc, uint32_t insn);
+
void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
void arm_gen_condlabel(DisasContext *s);
bool vfp_access_check(DisasContext *s);
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
new file mode 100644
index 00000000000..d47eb8e1535
--- /dev/null
+++ b/target/arm/translate-m-nocp.c
@@ -0,0 +1,221 @@
+/*
+ * ARM translation: M-profile NOCP special-case instructions
+ *
+ * Copyright (c) 2020 Linaro, Ltd.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "translate.h"
+#include "translate-a32.h"
+
+#include "decode-m-nocp.c.inc"
+
+/*
+ * Decode VLLDM and VLSTM are nonstandard because:
+ * * if there is no FPU then these insns must NOP in
+ * Secure state and UNDEF in Nonsecure state
+ * * if there is an FPU then these insns do not have
+ * the usual behaviour that vfp_access_check() provides of
+ * being controlled by CPACR/NSACR enable bits or the
+ * lazy-stacking logic.
+ */
+static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
+{
+ TCGv_i32 fptr;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+
+ if (a->op) {
+ /*
+ * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
+ * to take the IMPDEF option to make memory accesses to the stack
+ * slots that correspond to the D16-D31 registers (discarding
+ * read data and writing UNKNOWN values), so for us the T2
+ * encoding behaves identically to the T1 encoding.
+ */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+ return false;
+ }
+ } else {
+ /*
+ * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
+ * This is currently architecturally impossible, but we add the
+ * check to stay in line with the pseudocode. Note that we must
+ * emit code for the UNDEF so it takes precedence over the NOCP.
+ */
+ if (dc_isar_feature(aa32_simd_r32, s)) {
+ unallocated_encoding(s);
+ return true;
+ }
+ }
+
+ /*
+ * If not secure, UNDEF. We must emit code for this
+ * rather than returning false so that this takes
+ * precedence over the m-nocp.decode NOCP fallback.
+ */
+ if (!s->v8m_secure) {
+ unallocated_encoding(s);
+ return true;
+ }
+ /* If no fpu, NOP. */
+ if (!dc_isar_feature(aa32_vfp, s)) {
+ return true;
+ }
+
+ fptr = load_reg(s, a->rn);
+ if (a->l) {
+ gen_helper_v7m_vlldm(cpu_env, fptr);
+ } else {
+ gen_helper_v7m_vlstm(cpu_env, fptr);
+ }
+ tcg_temp_free_i32(fptr);
+
+ /* End the TB, because we have updated FP control bits */
+ s->base.is_jmp = DISAS_UPDATE_EXIT;
+ return true;
+}
+
+static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
+{
+ int btmreg, topreg;
+ TCGv_i64 zero;
+ TCGv_i32 aspen, sfpa;
+
+ if (!dc_isar_feature(aa32_m_sec_state, s)) {
+ /* Before v8.1M, fall through in decode to NOCP check */
+ return false;
+ }
+
+ /* Explicitly UNDEF because this takes precedence over NOCP */
+ if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
+ unallocated_encoding(s);
+ return true;
+ }
+
+ if (!dc_isar_feature(aa32_vfp_simd, s)) {
+ /* NOP if we have neither FP nor MVE */
+ return true;
+ }
+
+ /*
+ * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
+ * active floating point context so we must NOP (without doing
+ * any lazy state preservation or the NOCP check).
+ */
+ aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
+ sfpa = load_cpu_field(v7m.control[M_REG_S]);
+ tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
+ tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
+ tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
+ tcg_gen_or_i32(sfpa, sfpa, aspen);
+ arm_gen_condlabel(s);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
+
+ if (s->fp_excp_el != 0) {
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(), s->fp_excp_el);
+ return true;
+ }
+
+ topreg = a->vd + a->imm - 1;
+ btmreg = a->vd;
+
+ /* Convert to Sreg numbers if the insn specified in Dregs */
+ if (a->size == 3) {
+ topreg = topreg * 2 + 1;
+ btmreg *= 2;
+ }
+
+ if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
+ /* UNPREDICTABLE: we choose to undef */
+ unallocated_encoding(s);
+ return true;
+ }
+
+ /* Silently ignore requests to clear D16-D31 if they don't exist */
+ if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
+ topreg = 31;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /* Zero the Sregs from btmreg to topreg inclusive. */
+ zero = tcg_const_i64(0);
+ if (btmreg & 1) {
+ write_neon_element64(zero, btmreg >> 1, 1, MO_32);
+ btmreg++;
+ }
+ for (; btmreg + 1 <= topreg; btmreg += 2) {
+ write_neon_element64(zero, btmreg >> 1, 0, MO_64);
+ }
+ if (btmreg == topreg) {
+ write_neon_element64(zero, btmreg >> 1, 0, MO_32);
+ btmreg++;
+ }
+ assert(btmreg == topreg + 1);
+ /* TODO: when MVE is implemented, zero VPR here */
+ return true;
+}
+
+static bool trans_NOCP(DisasContext *s, arg_nocp *a)
+{
+ /*
+ * Handle M-profile early check for disabled coprocessor:
+ * all we need to do here is emit the NOCP exception if
+ * the coprocessor is disabled. Otherwise we return false
+ * and the real VFP/etc decode will handle the insn.
+ */
+ assert(arm_dc_feature(s, ARM_FEATURE_M));
+
+ if (a->cp == 11) {
+ a->cp = 10;
+ }
+ if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
+ (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
+ /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
+ a->cp = 10;
+ }
+
+ if (a->cp != 10) {
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(), default_exception_el(s));
+ return true;
+ }
+
+ if (s->fp_excp_el != 0) {
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(), s->fp_excp_el);
+ return true;
+ }
+
+ return false;
+}
+
+static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
+{
+ /* This range needs a coprocessor check for v8.1M and later only */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+ return false;
+ }
+ return trans_NOCP(s, a);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3c1d52279bc..46f6dfcf421 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1273,7 +1273,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
#define ARM_CP_RW_BIT (1 << 20)
/* Include the VFP and Neon decoders */
-#include "decode-m-nocp.c.inc"
#include "translate-vfp.c.inc"
#include "translate-neon.c.inc"
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index c368ada877b..500492f02fb 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -3800,202 +3800,6 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return true;
}
-/*
- * Decode VLLDM and VLSTM are nonstandard because:
- * * if there is no FPU then these insns must NOP in
- * Secure state and UNDEF in Nonsecure state
- * * if there is an FPU then these insns do not have
- * the usual behaviour that vfp_access_check() provides of
- * being controlled by CPACR/NSACR enable bits or the
- * lazy-stacking logic.
- */
-static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
-{
- TCGv_i32 fptr;
-
- if (!arm_dc_feature(s, ARM_FEATURE_M) ||
- !arm_dc_feature(s, ARM_FEATURE_V8)) {
- return false;
- }
-
- if (a->op) {
- /*
- * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
- * to take the IMPDEF option to make memory accesses to the stack
- * slots that correspond to the D16-D31 registers (discarding
- * read data and writing UNKNOWN values), so for us the T2
- * encoding behaves identically to the T1 encoding.
- */
- if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
- return false;
- }
- } else {
- /*
- * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
- * This is currently architecturally impossible, but we add the
- * check to stay in line with the pseudocode. Note that we must
- * emit code for the UNDEF so it takes precedence over the NOCP.
- */
- if (dc_isar_feature(aa32_simd_r32, s)) {
- unallocated_encoding(s);
- return true;
- }
- }
-
- /*
- * If not secure, UNDEF. We must emit code for this
- * rather than returning false so that this takes
- * precedence over the m-nocp.decode NOCP fallback.
- */
- if (!s->v8m_secure) {
- unallocated_encoding(s);
- return true;
- }
- /* If no fpu, NOP. */
- if (!dc_isar_feature(aa32_vfp, s)) {
- return true;
- }
-
- fptr = load_reg(s, a->rn);
- if (a->l) {
- gen_helper_v7m_vlldm(cpu_env, fptr);
- } else {
- gen_helper_v7m_vlstm(cpu_env, fptr);
- }
- tcg_temp_free_i32(fptr);
-
- /* End the TB, because we have updated FP control bits */
- s->base.is_jmp = DISAS_UPDATE_EXIT;
- return true;
-}
-
-static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
-{
- int btmreg, topreg;
- TCGv_i64 zero;
- TCGv_i32 aspen, sfpa;
-
- if (!dc_isar_feature(aa32_m_sec_state, s)) {
- /* Before v8.1M, fall through in decode to NOCP check */
- return false;
- }
-
- /* Explicitly UNDEF because this takes precedence over NOCP */
- if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
- unallocated_encoding(s);
- return true;
- }
-
- if (!dc_isar_feature(aa32_vfp_simd, s)) {
- /* NOP if we have neither FP nor MVE */
- return true;
- }
-
- /*
- * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
- * active floating point context so we must NOP (without doing
- * any lazy state preservation or the NOCP check).
- */
- aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
- sfpa = load_cpu_field(v7m.control[M_REG_S]);
- tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
- tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
- tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
- tcg_gen_or_i32(sfpa, sfpa, aspen);
- arm_gen_condlabel(s);
- tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
-
- if (s->fp_excp_el != 0) {
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
- syn_uncategorized(), s->fp_excp_el);
- return true;
- }
-
- topreg = a->vd + a->imm - 1;
- btmreg = a->vd;
-
- /* Convert to Sreg numbers if the insn specified in Dregs */
- if (a->size == 3) {
- topreg = topreg * 2 + 1;
- btmreg *= 2;
- }
-
- if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
- /* UNPREDICTABLE: we choose to undef */
- unallocated_encoding(s);
- return true;
- }
-
- /* Silently ignore requests to clear D16-D31 if they don't exist */
- if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
- topreg = 31;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- /* Zero the Sregs from btmreg to topreg inclusive. */
- zero = tcg_const_i64(0);
- if (btmreg & 1) {
- write_neon_element64(zero, btmreg >> 1, 1, MO_32);
- btmreg++;
- }
- for (; btmreg + 1 <= topreg; btmreg += 2) {
- write_neon_element64(zero, btmreg >> 1, 0, MO_64);
- }
- if (btmreg == topreg) {
- write_neon_element64(zero, btmreg >> 1, 0, MO_32);
- btmreg++;
- }
- assert(btmreg == topreg + 1);
- /* TODO: when MVE is implemented, zero VPR here */
- return true;
-}
-
-static bool trans_NOCP(DisasContext *s, arg_nocp *a)
-{
- /*
- * Handle M-profile early check for disabled coprocessor:
- * all we need to do here is emit the NOCP exception if
- * the coprocessor is disabled. Otherwise we return false
- * and the real VFP/etc decode will handle the insn.
- */
- assert(arm_dc_feature(s, ARM_FEATURE_M));
-
- if (a->cp == 11) {
- a->cp = 10;
- }
- if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
- (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
- /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
- a->cp = 10;
- }
-
- if (a->cp != 10) {
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
- syn_uncategorized(), default_exception_el(s));
- return true;
- }
-
- if (s->fp_excp_el != 0) {
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
- syn_uncategorized(), s->fp_excp_el);
- return true;
- }
-
- return false;
-}
-
-static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
-{
- /* This range needs a coprocessor check for v8.1M and later only */
- if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
- return false;
- }
- return trans_NOCP(s, a);
-}
-
static bool trans_VINS(DisasContext *s, arg_VINS *a)
{
TCGv_i32 rd, rm;
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 15b936c1010..bbee1325bc4 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -5,7 +5,7 @@ gen = [
decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'),
decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'),
decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'),
- decodetree.process('m-nocp.decode', extra_args: '--static-decode=disas_m_nocp'),
+ decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
@@ -26,6 +26,7 @@ arm_ss.add(files(
'op_helper.c',
'tlb_helper.c',
'translate.c',
+ 'translate-m-nocp.c',
'vec_helper.c',
'vfp_helper.c',
'cpu_tcg.c',
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (3 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 04/13] target/arm: Split m-nocp trans functions into their own file Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 15:39 ` Philippe Mathieu-Daudé
2021-04-30 16:37 ` Richard Henderson
2021-04-30 13:27 ` [PATCH v2 06/13] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc Peter Maydell
` (7 subsequent siblings)
12 siblings, 2 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Move the various gen_aa32* functions and macros out of translate.c
and into translate-a32.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++
target/arm/translate.c | 51 ++++++++++++------------------------
2 files changed, 69 insertions(+), 35 deletions(-)
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index cb451f70a42..522aa83636a 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -57,4 +57,57 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
return tmp;
}
+void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
+ TCGv_i32 a32, int index, MemOp opc);
+void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
+ TCGv_i32 a32, int index, MemOp opc);
+void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc);
+void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc);
+void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+ int index, MemOp opc);
+void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+ int index, MemOp opc);
+void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc);
+void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc);
+
+#define DO_GEN_LD(SUFF, OPC) \
+ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
+ TCGv_i32 a32, int index) \
+ { \
+ gen_aa32_ld_i32(s, val, a32, index, OPC); \
+ }
+
+#define DO_GEN_ST(SUFF, OPC) \
+ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
+ TCGv_i32 a32, int index) \
+ { \
+ gen_aa32_st_i32(s, val, a32, index, OPC); \
+ }
+
+static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index)
+{
+ gen_aa32_ld_i64(s, val, a32, index, MO_Q);
+}
+
+static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index)
+{
+ gen_aa32_st_i64(s, val, a32, index, MO_Q);
+}
+
+DO_GEN_LD(8u, MO_UB)
+DO_GEN_LD(16u, MO_UW)
+DO_GEN_LD(32u, MO_UL)
+DO_GEN_ST(8, MO_UB)
+DO_GEN_ST(16, MO_UW)
+DO_GEN_ST(32, MO_UL)
+
+#undef DO_GEN_LD
+#undef DO_GEN_ST
+
#endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 46f6dfcf421..5113cd2fea6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -899,24 +899,24 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
* Internal routines are used for NEON cases where the endianness
* and/or alignment has already been taken into account and manipulated.
*/
-static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
- TCGv_i32 a32, int index, MemOp opc)
+void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
+ TCGv_i32 a32, int index, MemOp opc)
{
TCGv addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_ld_i32(val, addr, index, opc);
tcg_temp_free(addr);
}
-static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
- TCGv_i32 a32, int index, MemOp opc)
+void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
+ TCGv_i32 a32, int index, MemOp opc)
{
TCGv addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_st_i32(val, addr, index, opc);
tcg_temp_free(addr);
}
-static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 a32, int index, MemOp opc)
+void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc)
{
TCGv addr = gen_aa32_addr(s, a32, opc);
@@ -929,8 +929,8 @@ static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
tcg_temp_free(addr);
}
-static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 a32, int index, MemOp opc)
+void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc)
{
TCGv addr = gen_aa32_addr(s, a32, opc);
@@ -946,26 +946,26 @@ static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
tcg_temp_free(addr);
}
-static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
- int index, MemOp opc)
+void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+ int index, MemOp opc)
{
gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc));
}
-static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
- int index, MemOp opc)
+void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+ int index, MemOp opc)
{
gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc));
}
-static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, MemOp opc)
+void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc)
{
gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc));
}
-static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, MemOp opc)
+void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc)
{
gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc));
}
@@ -984,25 +984,6 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
gen_aa32_st_i32(s, val, a32, index, OPC); \
}
-static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 a32, int index)
-{
- gen_aa32_ld_i64(s, val, a32, index, MO_Q);
-}
-
-static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
- TCGv_i32 a32, int index)
-{
- gen_aa32_st_i64(s, val, a32, index, MO_Q);
-}
-
-DO_GEN_LD(8u, MO_UB)
-DO_GEN_LD(16u, MO_UW)
-DO_GEN_LD(32u, MO_UL)
-DO_GEN_ST(8, MO_UB)
-DO_GEN_ST(16, MO_UW)
-DO_GEN_ST(32, MO_UL)
-
static inline void gen_hvc(DisasContext *s, int imm16)
{
/* The pre HVC helper handles cases when HVC gets trapped
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h
2021-04-30 13:27 ` [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h Peter Maydell
@ 2021-04-30 15:39 ` Philippe Mathieu-Daudé
2021-04-30 16:37 ` Richard Henderson
1 sibling, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-30 15:39 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 4/30/21 3:27 PM, Peter Maydell wrote:
> Move the various gen_aa32* functions and macros out of translate.c
> and into translate-a32.h.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++
> target/arm/translate.c | 51 ++++++++++++------------------------
> 2 files changed, 69 insertions(+), 35 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h
2021-04-30 13:27 ` [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h Peter Maydell
2021-04-30 15:39 ` Philippe Mathieu-Daudé
@ 2021-04-30 16:37 ` Richard Henderson
1 sibling, 0 replies; 18+ messages in thread
From: Richard Henderson @ 2021-04-30 16:37 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 4/30/21 6:27 AM, Peter Maydell wrote:
> Move the various gen_aa32* functions and macros out of translate.c
> and into translate-a32.h.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++
> target/arm/translate.c | 51 ++++++++++++------------------------
> 2 files changed, 69 insertions(+), 35 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 06/13] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (4 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 05/13] target/arm: Move gen_aa32 functions to translate-a32.h Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 07/13] target/arm: Make functions used by translate-vfp global Peter Maydell
` (6 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32()
and vfp_store_reg64() are used only in translate-vfp.c.inc. Move
them to that file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 20 --------------------
target/arm/translate-vfp.c.inc | 20 ++++++++++++++++++++
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5113cd2fea6..c8b9cedfcfd 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1144,26 +1144,6 @@ static long vfp_reg_offset(bool dp, unsigned reg)
}
}
-static inline void vfp_load_reg64(TCGv_i64 var, int reg)
-{
- tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
-}
-
-static inline void vfp_store_reg64(TCGv_i64 var, int reg)
-{
- tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
-}
-
-static inline void vfp_load_reg32(TCGv_i32 var, int reg)
-{
- tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
-}
-
-static inline void vfp_store_reg32(TCGv_i32 var, int reg)
-{
- tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
-}
-
void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
{
long off = neon_element_offset(reg, ele, memop);
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 500492f02fb..1004d1fd095 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -30,6 +30,26 @@
#include "decode-vfp.c.inc"
#include "decode-vfp-uncond.c.inc"
+static inline void vfp_load_reg64(TCGv_i64 var, int reg)
+{
+ tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
+}
+
+static inline void vfp_store_reg64(TCGv_i64 var, int reg)
+{
+ tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
+}
+
+static inline void vfp_load_reg32(TCGv_i32 var, int reg)
+{
+ tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
+}
+
+static inline void vfp_store_reg32(TCGv_i32 var, int reg)
+{
+ tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
+}
+
/*
* The imm8 encodes the sign bit, enough bits to represent an exponent in
* the range 01....1xx to 10....0xx, and the most significant 4 bits of
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 07/13] target/arm: Make functions used by translate-vfp global
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (5 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 06/13] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 08/13] target/arm: Make translate-vfp.c.inc its own compilation unit Peter Maydell
` (5 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Make the remaining functions which are needed by translate-vfp.c.inc
global.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: made gen_set_cpsr and gen_set_condexec not inline at rth's suggestion
---
target/arm/translate-a32.h | 18 ++++++++++++++++++
target/arm/translate.c | 25 ++++++++-----------------
2 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index 522aa83636a..326cbafe996 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -30,6 +30,13 @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
+TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
+void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
+void gen_set_condexec(DisasContext *s);
+void gen_set_pc_im(DisasContext *s, target_ulong val);
+void gen_lookup_tb(DisasContext *s);
+long vfp_reg_offset(bool dp, unsigned reg);
+long neon_full_reg_offset(unsigned reg);
static inline TCGv_i32 load_cpu_offset(int offset)
{
@@ -57,6 +64,8 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
return tmp;
}
+void store_reg(DisasContext *s, int reg, TCGv_i32 var);
+
void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
TCGv_i32 a32, int index, MemOp opc);
void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
@@ -110,4 +119,13 @@ DO_GEN_ST(32, MO_UL)
#undef DO_GEN_LD
#undef DO_GEN_ST
+#if defined(CONFIG_USER_ONLY)
+#define IS_USER(s) 1
+#else
+#define IS_USER(s) (s->user)
+#endif
+
+/* Set NZCV flags from the high 4 bits of var. */
+#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
+
#endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c8b9cedfcfd..c83f2205b67 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -52,12 +52,6 @@
#include "translate.h"
#include "translate-a32.h"
-#if defined(CONFIG_USER_ONLY)
-#define IS_USER(s) 1
-#else
-#define IS_USER(s) (s->user)
-#endif
-
/* These are TCG temporaries used only by the legacy iwMMXt decoder */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
/* These are TCG globals which alias CPUARMState fields */
@@ -209,7 +203,7 @@ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
* This is used for load/store for which use of PC implies (literal),
* or ADD that implies ADR.
*/
-static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
+TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
{
TCGv_i32 tmp = tcg_temp_new_i32();
@@ -223,7 +217,7 @@ static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
/* Set a CPU register. The source must be a temporary and will be
marked as dead. */
-static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
+void store_reg(DisasContext *s, int reg, TCGv_i32 var)
{
if (reg == 15) {
/* In Thumb mode, we must ignore bit 0.
@@ -264,15 +258,12 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
-
-static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
+void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
{
TCGv_i32 tmp_mask = tcg_const_i32(mask);
gen_helper_cpsr_write(cpu_env, var, tmp_mask);
tcg_temp_free_i32(tmp_mask);
}
-/* Set NZCV flags from the high 4 bits of var. */
-#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
static void gen_exception_internal(int excp)
{
@@ -697,7 +688,7 @@ void arm_gen_test_cc(int cc, TCGLabel *label)
arm_free_cc(&cmp);
}
-static inline void gen_set_condexec(DisasContext *s)
+void gen_set_condexec(DisasContext *s)
{
if (s->condexec_mask) {
uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
@@ -707,7 +698,7 @@ static inline void gen_set_condexec(DisasContext *s)
}
}
-static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
+void gen_set_pc_im(DisasContext *s, target_ulong val)
{
tcg_gen_movi_i32(cpu_R[15], val);
}
@@ -1074,7 +1065,7 @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
}
/* Force a TB lookup after an instruction that changes the CPU state. */
-static inline void gen_lookup_tb(DisasContext *s)
+void gen_lookup_tb(DisasContext *s)
{
tcg_gen_movi_i32(cpu_R[15], s->base.pc_next);
s->base.is_jmp = DISAS_EXIT;
@@ -1109,7 +1100,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
/*
* Return the offset of a "full" NEON Dreg.
*/
-static long neon_full_reg_offset(unsigned reg)
+long neon_full_reg_offset(unsigned reg)
{
return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
}
@@ -1135,7 +1126,7 @@ static long neon_element_offset(int reg, int element, MemOp memop)
}
/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */
-static long vfp_reg_offset(bool dp, unsigned reg)
+long vfp_reg_offset(bool dp, unsigned reg)
{
if (dp) {
return neon_element_offset(reg, 0, MO_64);
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 08/13] target/arm: Make translate-vfp.c.inc its own compilation unit
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (6 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 07/13] target/arm: Make functions used by translate-vfp global Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc Peter Maydell
` (4 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Switch translate-vfp.c.inc from being #included into translate.c
to being its own compilation unit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a32.h | 2 ++
target/arm/{translate-vfp.c.inc => translate-vfp.c} | 12 +++++++-----
target/arm/translate.c | 3 +--
target/arm/meson.build | 5 +++--
4 files changed, 13 insertions(+), 9 deletions(-)
rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (99%)
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index 326cbafe996..e767366f694 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -22,6 +22,8 @@
/* Prototypes for autogenerated disassembler functions */
bool disas_m_nocp(DisasContext *dc, uint32_t insn);
+bool disas_vfp(DisasContext *s, uint32_t insn);
+bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
void arm_gen_condlabel(DisasContext *s);
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c
similarity index 99%
rename from target/arm/translate-vfp.c.inc
rename to target/arm/translate-vfp.c
index 1004d1fd095..3da84f30a01 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c
@@ -20,11 +20,13 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-/*
- * This file is intended to be included from translate.c; it uses
- * some macros and definitions provided by that file.
- * It might be possible to convert it to a standalone .c file eventually.
- */
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "exec/exec-all.h"
+#include "exec/gen-icount.h"
+#include "translate.h"
+#include "translate-a32.h"
/* Include the generated VFP decoder */
#include "decode-vfp.c.inc"
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c83f2205b67..6aec494e81d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1224,8 +1224,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
#define ARM_CP_RW_BIT (1 << 20)
-/* Include the VFP and Neon decoders */
-#include "translate-vfp.c.inc"
+/* Include the Neon decoder */
#include "translate-neon.c.inc"
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index bbee1325bc4..f6360f33f11 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -3,8 +3,8 @@ gen = [
decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'),
decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'),
decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'),
- decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'),
- decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'),
+ decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'),
+ decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'),
decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
@@ -27,6 +27,7 @@ arm_ss.add(files(
'tlb_helper.c',
'translate.c',
'translate-m-nocp.c',
+ 'translate-vfp.c',
'vec_helper.c',
'vfp_helper.c',
'cpu_tcg.c',
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (7 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 08/13] target/arm: Make translate-vfp.c.inc its own compilation unit Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 10/13] target/arm: Delete unused typedef Peter Maydell
` (3 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
The function vfp_reg_ptr() is used only in translate-neon.c.inc;
move it there.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 7 -------
target/arm/translate-neon.c.inc | 7 +++++++
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6aec494e81d..095b5c509e1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1215,13 +1215,6 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
}
}
-static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
-{
- TCGv_ptr ret = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg));
- return ret;
-}
-
#define ARM_CP_RW_BIT (1 << 20)
/* Include the Neon decoder */
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index a02b8369a1d..73bf376ed32 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -60,6 +60,13 @@ static inline int neon_3same_fp_size(DisasContext *s, int x)
#include "decode-neon-ls.c.inc"
#include "decode-neon-shared.c.inc"
+static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
+{
+ TCGv_ptr ret = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg));
+ return ret;
+}
+
static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
{
long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 10/13] target/arm: Delete unused typedef
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (8 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 16:27 ` Philippe Mathieu-Daudé
2021-04-30 13:27 ` [PATCH v2 11/13] target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h Peter Maydell
` (2 subsequent siblings)
12 siblings, 1 reply; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
The VFPGenFixPointFn typedef is unused; delete it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 095b5c509e1..58cb3e8aafe 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -69,8 +69,6 @@ static const char * const regnames[] =
/* Function prototypes for gen_ functions calling Neon helpers. */
typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
TCGv_i32, TCGv_i32);
-/* Function prototypes for gen_ functions for fix point conversions */
-typedef void VFPGenFixPointFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
/* initialize TCG globals. */
void arm_translate_init(void)
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 11/13] target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (9 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 10/13] target/arm: Delete unused typedef Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 16:28 ` Philippe Mathieu-Daudé
2021-04-30 13:27 ` [PATCH v2 12/13] target/arm: Make functions used by translate-neon global Peter Maydell
2021-04-30 13:27 ` [PATCH v2 13/13] target/arm: Make translate-neon.c.inc its own compilation unit Peter Maydell
12 siblings, 1 reply; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Move the NeonGenThreeOpEnvFn typedef to translate.h together
with the other similar typedefs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 2 ++
target/arm/translate.c | 3 ---
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 8130a3be29d..12c28b0d32c 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -409,6 +409,8 @@ typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
+typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
+ TCGv_i32, TCGv_i32);
typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 58cb3e8aafe..7ff0425c752 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -66,9 +66,6 @@ static const char * const regnames[] =
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
-/* Function prototypes for gen_ functions calling Neon helpers. */
-typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
- TCGv_i32, TCGv_i32);
/* initialize TCG globals. */
void arm_translate_init(void)
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 12/13] target/arm: Make functions used by translate-neon global
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (10 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 11/13] target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
2021-04-30 13:27 ` [PATCH v2 13/13] target/arm: Make translate-neon.c.inc its own compilation unit Peter Maydell
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Make the remaining functions needed by the translate-neon code
global.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a32.h | 8 ++++++++
target/arm/translate.c | 10 ++--------
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index e767366f694..3ddb76b76b5 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -39,6 +39,8 @@ void gen_set_pc_im(DisasContext *s, target_ulong val);
void gen_lookup_tb(DisasContext *s);
long vfp_reg_offset(bool dp, unsigned reg);
long neon_full_reg_offset(unsigned reg);
+long neon_element_offset(int reg, int element, MemOp memop);
+void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
static inline TCGv_i32 load_cpu_offset(int offset)
{
@@ -130,4 +132,10 @@ DO_GEN_ST(32, MO_UL)
/* Set NZCV flags from the high 4 bits of var. */
#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
+/* Swap low and high halfwords. */
+static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
+{
+ tcg_gen_rotri_i32(dest, var, 16);
+}
+
#endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7ff0425c752..18de16ebd0a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -325,7 +325,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
}
/* Byteswap each halfword. */
-static void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
+void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
{
TCGv_i32 tmp = tcg_temp_new_i32();
TCGv_i32 mask = tcg_const_i32(0x00ff00ff);
@@ -346,12 +346,6 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
tcg_gen_ext16s_i32(dest, var);
}
-/* Swap low and high halfwords. */
-static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
-{
- tcg_gen_rotri_i32(dest, var, 16);
-}
-
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
tmp = (t0 ^ t1) & 0x8000;
t0 &= ~0x8000;
@@ -1104,7 +1098,7 @@ long neon_full_reg_offset(unsigned reg)
* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
* where 0 is the least significant end of the register.
*/
-static long neon_element_offset(int reg, int element, MemOp memop)
+long neon_element_offset(int reg, int element, MemOp memop)
{
int element_size = 1 << (memop & MO_SIZE);
int ofs = element * element_size;
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 13/13] target/arm: Make translate-neon.c.inc its own compilation unit
2021-04-30 13:27 [PATCH v2 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
` (11 preceding siblings ...)
2021-04-30 13:27 ` [PATCH v2 12/13] target/arm: Make functions used by translate-neon global Peter Maydell
@ 2021-04-30 13:27 ` Peter Maydell
12 siblings, 0 replies; 18+ messages in thread
From: Peter Maydell @ 2021-04-30 13:27 UTC (permalink / raw)
To: qemu-devel
Switch translate-neon.c.inc from being #included into translate.c
to being its own compilation unit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a32.h | 3 +++
.../arm/{translate-neon.c.inc => translate-neon.c} | 12 +++++++-----
target/arm/translate.c | 3 ---
target/arm/meson.build | 7 ++++---
4 files changed, 14 insertions(+), 11 deletions(-)
rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%)
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index 3ddb76b76b5..c997f4e3216 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -24,6 +24,9 @@
bool disas_m_nocp(DisasContext *dc, uint32_t insn);
bool disas_vfp(DisasContext *s, uint32_t insn);
bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
+bool disas_neon_dp(DisasContext *s, uint32_t insn);
+bool disas_neon_ls(DisasContext *s, uint32_t insn);
+bool disas_neon_shared(DisasContext *s, uint32_t insn);
void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
void arm_gen_condlabel(DisasContext *s);
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c
similarity index 99%
rename from target/arm/translate-neon.c.inc
rename to target/arm/translate-neon.c
index 73bf376ed32..658bd275dac 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c
@@ -20,11 +20,13 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-/*
- * This file is intended to be included from translate.c; it uses
- * some macros and definitions provided by that file.
- * It might be possible to convert it to a standalone .c file eventually.
- */
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "exec/exec-all.h"
+#include "exec/gen-icount.h"
+#include "translate.h"
+#include "translate-a32.h"
static inline int plus1(DisasContext *s, int x)
{
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 18de16ebd0a..455352bcf60 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1206,9 +1206,6 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
#define ARM_CP_RW_BIT (1 << 20)
-/* Include the Neon decoder */
-#include "translate-neon.c.inc"
-
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
{
tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
diff --git a/target/arm/meson.build b/target/arm/meson.build
index f6360f33f11..5bfaf43b500 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,8 +1,8 @@
gen = [
decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
- decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'),
- decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'),
- decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'),
+ decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
+ decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
+ decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'),
decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'),
decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
@@ -27,6 +27,7 @@ arm_ss.add(files(
'tlb_helper.c',
'translate.c',
'translate-m-nocp.c',
+ 'translate-neon.c',
'translate-vfp.c',
'vec_helper.c',
'vfp_helper.c',
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread