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From: Nikola Cornij <nikola.cornij@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Nikola Cornij <nikola.cornij@amd.com>,
	koba.ko@canonical.com, aurabindo.pillai@amd.com,
	mikita.lipski@amd.com, bskeggs@redhat.com
Subject: [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST
Date: Fri, 30 Apr 2021 17:45:31 -0400	[thread overview]
Message-ID: <20210430214531.24565-2-nikola.cornij@amd.com> (raw)
In-Reply-To: <20210430214531.24565-1-nikola.cornij@amd.com>

[why]
Previously used value was not safe to provide the correct value, i.e. it
could be 0 if not not configured, leading to no MST on this platform.

[how]
Do not use the value from BIOS, but from the structure populated at
encoder initialization time.

Fixes: 98025a62cb00 ("drm/dp_mst: Use Extended Base Receiver Capability DPCD space")
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bf7f8487945c..3642d7578658 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -942,7 +942,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
 	struct intel_dp *intel_dp = &dig_port->dp;
 	enum port port = dig_port->base.port;
 	int ret;
-	int bios_max_link_rate;
+	int max_source_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 
 	if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
 		return 0;
@@ -957,11 +957,11 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
 
 	/* create encoders */
 	intel_dp_create_fake_mst_encoders(dig_port);
-	bios_max_link_rate = intel_bios_dp_max_link_rate(&dig_port->base);
 	ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
 					   &intel_dp->aux, 16, 3,
 					   (u8)dig_port->max_lanes,
-					   (u8)(bios_max_link_rate / 27000), conn_base_id);
+					   (u8)(max_source_rate / 27000),
+					   conn_base_id);
 	if (ret)
 		return ret;
 
-- 
2.25.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: Nikola Cornij <nikola.cornij@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Nikola Cornij <nikola.cornij@amd.com>,
	koba.ko@canonical.com, aurabindo.pillai@amd.com,
	mikita.lipski@amd.com, bskeggs@redhat.com
Subject: [Intel-gfx] [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST
Date: Fri, 30 Apr 2021 17:45:31 -0400	[thread overview]
Message-ID: <20210430214531.24565-2-nikola.cornij@amd.com> (raw)
In-Reply-To: <20210430214531.24565-1-nikola.cornij@amd.com>

[why]
Previously used value was not safe to provide the correct value, i.e. it
could be 0 if not not configured, leading to no MST on this platform.

[how]
Do not use the value from BIOS, but from the structure populated at
encoder initialization time.

Fixes: 98025a62cb00 ("drm/dp_mst: Use Extended Base Receiver Capability DPCD space")
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bf7f8487945c..3642d7578658 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -942,7 +942,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
 	struct intel_dp *intel_dp = &dig_port->dp;
 	enum port port = dig_port->base.port;
 	int ret;
-	int bios_max_link_rate;
+	int max_source_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 
 	if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
 		return 0;
@@ -957,11 +957,11 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
 
 	/* create encoders */
 	intel_dp_create_fake_mst_encoders(dig_port);
-	bios_max_link_rate = intel_bios_dp_max_link_rate(&dig_port->base);
 	ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
 					   &intel_dp->aux, 16, 3,
 					   (u8)dig_port->max_lanes,
-					   (u8)(bios_max_link_rate / 27000), conn_base_id);
+					   (u8)(max_source_rate / 27000),
+					   conn_base_id);
 	if (ret)
 		return ret;
 
-- 
2.25.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Nikola Cornij <nikola.cornij@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Nikola Cornij <nikola.cornij@amd.com>,
	koba.ko@canonical.com, aurabindo.pillai@amd.com,
	jani.nikula@linux.intel.com, mikita.lipski@amd.com,
	ville.syrjala@linux.intel.com, bskeggs@redhat.com
Subject: [PATCH v2 1/1] drm/i915: Use the correct max source link rate for MST
Date: Fri, 30 Apr 2021 17:45:31 -0400	[thread overview]
Message-ID: <20210430214531.24565-2-nikola.cornij@amd.com> (raw)
In-Reply-To: <20210430214531.24565-1-nikola.cornij@amd.com>

[why]
Previously used value was not safe to provide the correct value, i.e. it
could be 0 if not not configured, leading to no MST on this platform.

[how]
Do not use the value from BIOS, but from the structure populated at
encoder initialization time.

Fixes: 98025a62cb00 ("drm/dp_mst: Use Extended Base Receiver Capability DPCD space")
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bf7f8487945c..3642d7578658 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -942,7 +942,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
 	struct intel_dp *intel_dp = &dig_port->dp;
 	enum port port = dig_port->base.port;
 	int ret;
-	int bios_max_link_rate;
+	int max_source_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 
 	if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
 		return 0;
@@ -957,11 +957,11 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
 
 	/* create encoders */
 	intel_dp_create_fake_mst_encoders(dig_port);
-	bios_max_link_rate = intel_bios_dp_max_link_rate(&dig_port->base);
 	ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
 					   &intel_dp->aux, 16, 3,
 					   (u8)dig_port->max_lanes,
-					   (u8)(bios_max_link_rate / 27000), conn_base_id);
+					   (u8)(max_source_rate / 27000),
+					   conn_base_id);
 	if (ret)
 		return ret;
 
-- 
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  reply	other threads:[~2021-04-30 21:45 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-30 21:45 [PATCH v2 0/1] drm/i915: Use the correct max source link rate for MST Nikola Cornij
2021-04-30 21:45 ` Nikola Cornij
2021-04-30 21:45 ` [Intel-gfx] " Nikola Cornij
2021-04-30 21:45 ` Nikola Cornij [this message]
2021-04-30 21:45   ` [PATCH v2 1/1] " Nikola Cornij
2021-04-30 21:45   ` [Intel-gfx] " Nikola Cornij
2021-04-30 22:41   ` Lyude Paul
2021-04-30 22:41     ` Lyude Paul
2021-04-30 22:41     ` [Intel-gfx] " Lyude Paul
2021-04-30 22:55     ` Cornij, Nikola
2021-04-30 22:55       ` Cornij, Nikola
2021-04-30 22:55       ` [Intel-gfx] " Cornij, Nikola
2021-05-03  8:44       ` Jani Nikula
2021-05-03  8:44         ` Jani Nikula
2021-05-03  8:44         ` [Intel-gfx] " Jani Nikula
2021-05-03 13:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork

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