* [PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers
2021-05-04 14:01 [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Bruno Larsen (billionai)
@ 2021-05-04 14:01 ` Bruno Larsen (billionai)
2021-05-05 4:10 ` David Gibson
2021-05-04 14:01 ` [PATCH v4 2/5] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Bruno Larsen (billionai) @ 2021-05-04 14:01 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
folded gen_{read,write}_xer into their only callers, spr_{read,write}_xer
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 37 ---------------------------------
target/ppc/translate_init.c.inc | 33 +++++++++++++++++++++++++++--
2 files changed, 31 insertions(+), 39 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b319d409c6..2f10aa2fea 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4175,43 +4175,6 @@ static void gen_tdi(DisasContext *ctx)
/*** Processor control ***/
-static void gen_read_xer(DisasContext *ctx, TCGv dst)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_mov_tl(dst, cpu_xer);
- tcg_gen_shli_tl(t0, cpu_so, XER_SO);
- tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
- tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_or_tl(dst, dst, t2);
- tcg_gen_or_tl(dst, dst, t0);
- if (is_isa300(ctx)) {
- tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
- tcg_gen_or_tl(dst, dst, t0);
- tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
- tcg_gen_or_tl(dst, dst, t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void gen_write_xer(TCGv src)
-{
- /* Write all flags, while reading back check for isa300 */
- tcg_gen_andi_tl(cpu_xer, src,
- ~((1u << XER_SO) |
- (1u << XER_OV) | (1u << XER_OV32) |
- (1u << XER_CA) | (1u << XER_CA32)));
- tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
- tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
- tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
- tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
- tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
-}
-
/* mcrxr */
static void gen_mcrxr(DisasContext *ctx)
{
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index d10d7e5bf6..d5527c149f 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -116,12 +116,41 @@ static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
/* XER */
static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
{
- gen_read_xer(ctx, cpu_gpr[gprn]);
+ TCGv dst = cpu_gpr[gprn];
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ tcg_gen_mov_tl(dst, cpu_xer);
+ tcg_gen_shli_tl(t0, cpu_so, XER_SO);
+ tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
+ tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_or_tl(dst, dst, t2);
+ tcg_gen_or_tl(dst, dst, t0);
+ if (is_isa300(ctx)) {
+ tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
+ tcg_gen_or_tl(dst, dst, t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
}
static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
{
- gen_write_xer(cpu_gpr[gprn]);
+ TCGv src = cpu_gpr[gprn];
+ /* Write all flags, while reading back check for isa300 */
+ tcg_gen_andi_tl(cpu_xer, src,
+ ~((1u << XER_SO) |
+ (1u << XER_OV) | (1u << XER_OV32) |
+ (1u << XER_CA) | (1u << XER_CA32)));
+ tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
+ tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
+ tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
+ tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
+ tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
}
/* LR */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers
2021-05-04 14:01 ` [PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers Bruno Larsen (billionai)
@ 2021-05-05 4:10 ` David Gibson
0 siblings, 0 replies; 14+ messages in thread
From: David Gibson @ 2021-05-05 4:10 UTC (permalink / raw)
To: Bruno Larsen (billionai)
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 4391 bytes --]
On Tue, May 04, 2021 at 11:01:53AM -0300, Bruno Larsen (billionai) wrote:
> folded gen_{read,write}_xer into their only callers, spr_{read,write}_xer
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Good cleanup on its own. Applied to ppc-for-6.1.
> ---
> target/ppc/translate.c | 37 ---------------------------------
> target/ppc/translate_init.c.inc | 33 +++++++++++++++++++++++++++--
> 2 files changed, 31 insertions(+), 39 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index b319d409c6..2f10aa2fea 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4175,43 +4175,6 @@ static void gen_tdi(DisasContext *ctx)
>
> /*** Processor control ***/
>
> -static void gen_read_xer(DisasContext *ctx, TCGv dst)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> - tcg_gen_mov_tl(dst, cpu_xer);
> - tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> - tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> - tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> - tcg_gen_or_tl(t0, t0, t1);
> - tcg_gen_or_tl(dst, dst, t2);
> - tcg_gen_or_tl(dst, dst, t0);
> - if (is_isa300(ctx)) {
> - tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> - tcg_gen_or_tl(dst, dst, t0);
> - tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> - tcg_gen_or_tl(dst, dst, t0);
> - }
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void gen_write_xer(TCGv src)
> -{
> - /* Write all flags, while reading back check for isa300 */
> - tcg_gen_andi_tl(cpu_xer, src,
> - ~((1u << XER_SO) |
> - (1u << XER_OV) | (1u << XER_OV32) |
> - (1u << XER_CA) | (1u << XER_CA32)));
> - tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> - tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> - tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> - tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> - tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> -}
> -
> /* mcrxr */
> static void gen_mcrxr(DisasContext *ctx)
> {
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index d10d7e5bf6..d5527c149f 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -116,12 +116,41 @@ static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
> /* XER */
> static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
> {
> - gen_read_xer(ctx, cpu_gpr[gprn]);
> + TCGv dst = cpu_gpr[gprn];
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> + tcg_gen_mov_tl(dst, cpu_xer);
> + tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> + tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> + tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> + tcg_gen_or_tl(t0, t0, t1);
> + tcg_gen_or_tl(dst, dst, t2);
> + tcg_gen_or_tl(dst, dst, t0);
> + if (is_isa300(ctx)) {
> + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> + tcg_gen_or_tl(dst, dst, t0);
> + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> + tcg_gen_or_tl(dst, dst, t0);
> + }
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> }
>
> static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
> {
> - gen_write_xer(cpu_gpr[gprn]);
> + TCGv src = cpu_gpr[gprn];
> + /* Write all flags, while reading back check for isa300 */
> + tcg_gen_andi_tl(cpu_xer, src,
> + ~((1u << XER_SO) |
> + (1u << XER_OV) | (1u << XER_OV32) |
> + (1u << XER_CA) | (1u << XER_CA32)));
> + tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> + tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> + tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> + tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> + tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> }
>
> /* LR */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 2/5] target/ppc: renamed SPR registration functions
2021-05-04 14:01 [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Bruno Larsen (billionai)
2021-05-04 14:01 ` [PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers Bruno Larsen (billionai)
@ 2021-05-04 14:01 ` Bruno Larsen (billionai)
2021-05-04 15:59 ` Richard Henderson
2021-05-05 4:11 ` David Gibson
2021-05-04 14:01 ` [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c Bruno Larsen (billionai)
` (3 subsequent siblings)
5 siblings, 2 replies; 14+ messages in thread
From: Bruno Larsen (billionai) @ 2021-05-04 14:01 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
Renamed all gen_spr_* and gen_* functions specifically related to
registering SPRs to register_*_sprs and register_*, to avoid future
confusion with other TCG related code.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/translate_init.c.inc | 860 ++++++++++++++++----------------
1 file changed, 430 insertions(+), 430 deletions(-)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index d5527c149f..4fac8a9950 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -842,7 +842,7 @@ static void _spr_register(CPUPPCState *env, int num, const char *name,
oea_read, oea_write, 0, ival)
/* Generic PowerPC SPRs */
-static void gen_spr_generic(CPUPPCState *env)
+static void register_generic_sprs(CPUPPCState *env)
{
/* Integer processing */
spr_register(env, SPR_XER, "XER",
@@ -887,7 +887,7 @@ static void gen_spr_generic(CPUPPCState *env)
}
/* SPR common to all non-embedded PowerPC, including 601 */
-static void gen_spr_ne_601(CPUPPCState *env)
+static void register_ne_601_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -906,7 +906,7 @@ static void gen_spr_ne_601(CPUPPCState *env)
}
/* Storage Description Register 1 */
-static void gen_spr_sdr1(CPUPPCState *env)
+static void register_sdr1_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
if (env->has_hv_mode) {
@@ -929,7 +929,7 @@ static void gen_spr_sdr1(CPUPPCState *env)
}
/* BATs 0-3 */
-static void gen_low_BATs(CPUPPCState *env)
+static void register_low_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U",
@@ -1001,7 +1001,7 @@ static void gen_low_BATs(CPUPPCState *env)
}
/* BATs 4-7 */
-static void gen_high_BATs(CPUPPCState *env)
+static void register_high_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT4U, "IBAT4U",
@@ -1073,7 +1073,7 @@ static void gen_high_BATs(CPUPPCState *env)
}
/* Generic PowerPC time base */
-static void gen_tbl(CPUPPCState *env)
+static void register_tbl(CPUPPCState *env)
{
spr_register(env, SPR_VTBL, "TBL",
&spr_read_tbl, SPR_NOACCESS,
@@ -1094,7 +1094,7 @@ static void gen_tbl(CPUPPCState *env)
}
/* Softare table search registers */
-static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
@@ -1133,7 +1133,7 @@ static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
}
/* SPR common to MPC755 and G2 */
-static void gen_spr_G2_755(CPUPPCState *env)
+static void register_G2_755_sprs(CPUPPCState *env)
{
/* SGPRs */
spr_register(env, SPR_SPRG4, "SPRG4",
@@ -1155,7 +1155,7 @@ static void gen_spr_G2_755(CPUPPCState *env)
}
/* SPR common to all 7xx PowerPC implementations */
-static void gen_spr_7xx(CPUPPCState *env)
+static void register_7xx_sprs(CPUPPCState *env)
{
/* Breakpoints */
/* XXX : not implemented */
@@ -1353,7 +1353,7 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
}
#endif /* CONFIG_USER_ONLY */
-static void gen_spr_amr(CPUPPCState *env)
+static void register_amr_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
/*
@@ -1385,7 +1385,7 @@ static void gen_spr_amr(CPUPPCState *env)
#endif /* !CONFIG_USER_ONLY */
}
-static void gen_spr_iamr(CPUPPCState *env)
+static void register_iamr_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
@@ -1406,7 +1406,7 @@ static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
}
#endif /* !CONFIG_USER_ONLY */
-static void gen_spr_thrm(CPUPPCState *env)
+static void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
/* XXX : not implemented */
@@ -1427,7 +1427,7 @@ static void gen_spr_thrm(CPUPPCState *env)
}
/* SPR specific to PowerPC 604 implementation */
-static void gen_spr_604(CPUPPCState *env)
+static void register_604_sprs(CPUPPCState *env)
{
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
@@ -1480,7 +1480,7 @@ static void gen_spr_604(CPUPPCState *env)
}
/* SPR specific to PowerPC 603 implementation */
-static void gen_spr_603(CPUPPCState *env)
+static void register_603_sprs(CPUPPCState *env)
{
/* External access control */
/* XXX : not implemented */
@@ -1498,7 +1498,7 @@ static void gen_spr_603(CPUPPCState *env)
}
/* SPR specific to PowerPC G2 implementation */
-static void gen_spr_G2(CPUPPCState *env)
+static void register_G2_sprs(CPUPPCState *env)
{
/* Memory base address */
/* MBAR */
@@ -1550,7 +1550,7 @@ static void gen_spr_G2(CPUPPCState *env)
}
/* SPR specific to PowerPC 602 implementation */
-static void gen_spr_602(CPUPPCState *env)
+static void register_602_sprs(CPUPPCState *env)
{
/* ESA registers */
/* XXX : not implemented */
@@ -1598,7 +1598,7 @@ static void gen_spr_602(CPUPPCState *env)
}
/* SPR specific to PowerPC 601 implementation */
-static void gen_spr_601(CPUPPCState *env)
+static void register_601_sprs(CPUPPCState *env)
{
/* Multiplication/division register */
/* MQ */
@@ -1674,7 +1674,7 @@ static void gen_spr_601(CPUPPCState *env)
#endif
}
-static void gen_spr_74xx(CPUPPCState *env)
+static void register_74xx_sprs(CPUPPCState *env)
{
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
@@ -1724,7 +1724,7 @@ static void gen_spr_74xx(CPUPPCState *env)
0x00000000);
}
-static void gen_l3_ctrl(CPUPPCState *env)
+static void register_l3_ctrl(CPUPPCState *env)
{
/* L3CR */
/* XXX : not implemented */
@@ -1746,7 +1746,7 @@ static void gen_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
@@ -1822,7 +1822,7 @@ static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
#endif
-static void gen_spr_usprg3(CPUPPCState *env)
+static void register_usprg3_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG3, "USPRG3",
&spr_read_ureg, SPR_NOACCESS,
@@ -1830,7 +1830,7 @@ static void gen_spr_usprg3(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_usprgh(CPUPPCState *env)
+static void register_usprgh_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
&spr_read_ureg, SPR_NOACCESS,
@@ -1851,7 +1851,7 @@ static void gen_spr_usprgh(CPUPPCState *env)
}
/* PowerPC BookE SPR */
-static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
+static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
{
const char *ivor_names[64] = {
"IVOR0", "IVOR1", "IVOR2", "IVOR3",
@@ -2027,7 +2027,7 @@ static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
0x00000000);
}
-static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
+static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
uint32_t maxsize, uint32_t flags,
uint32_t nentries)
{
@@ -2038,7 +2038,7 @@ static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
}
/* BookE 2.06 storage control registers */
-static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
+static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
uint32_t *tlbncfg, uint32_t mmucfg)
{
#if !defined(CONFIG_USER_ONLY)
@@ -2126,11 +2126,11 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
}
#endif
- gen_spr_usprgh(env);
+ register_usprgh_sprs(env);
}
/* SPR specific to PowerPC 440 implementation */
-static void gen_spr_440(CPUPPCState *env)
+static void register_440_sprs(CPUPPCState *env)
{
/* Cache control */
/* XXX : not implemented */
@@ -2271,7 +2271,7 @@ static void gen_spr_440(CPUPPCState *env)
}
/* SPR shared between PowerPC 40x implementations */
-static void gen_spr_40x(CPUPPCState *env)
+static void register_40x_sprs(CPUPPCState *env)
{
/* Cache */
/* not emulated, as QEMU do not emulate caches */
@@ -2326,7 +2326,7 @@ static void gen_spr_40x(CPUPPCState *env)
}
/* SPR specific to PowerPC 405 implementation */
-static void gen_spr_405(CPUPPCState *env)
+static void register_405_sprs(CPUPPCState *env)
{
/* MMU */
spr_register(env, SPR_40x_PID, "PID",
@@ -2428,11 +2428,11 @@ static void gen_spr_405(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
- gen_spr_usprgh(env);
+ register_usprgh_sprs(env);
}
/* SPR shared between PowerPC 401 & 403 implementations */
-static void gen_spr_401_403(CPUPPCState *env)
+static void register_401_403_sprs(CPUPPCState *env)
{
/* Time base */
spr_register(env, SPR_403_VTBL, "TBL",
@@ -2460,7 +2460,7 @@ static void gen_spr_401_403(CPUPPCState *env)
}
/* SPR specific to PowerPC 401 implementation */
-static void gen_spr_401(CPUPPCState *env)
+static void register_401_sprs(CPUPPCState *env)
{
/* Debug interface */
/* XXX : not implemented */
@@ -2502,9 +2502,9 @@ static void gen_spr_401(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_401x2(CPUPPCState *env)
+static void register_401x2_sprs(CPUPPCState *env)
{
- gen_spr_401(env);
+ register_401_sprs(env);
spr_register(env, SPR_40x_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2516,7 +2516,7 @@ static void gen_spr_401x2(CPUPPCState *env)
}
/* SPR specific to PowerPC 403 implementation */
-static void gen_spr_403(CPUPPCState *env)
+static void register_403_sprs(CPUPPCState *env)
{
/* Debug interface */
/* XXX : not implemented */
@@ -2552,7 +2552,7 @@ static void gen_spr_403(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_403_real(CPUPPCState *env)
+static void register_403_real_sprs(CPUPPCState *env)
{
spr_register(env, SPR_403_PBL1, "PBL1",
SPR_NOACCESS, SPR_NOACCESS,
@@ -2572,7 +2572,7 @@ static void gen_spr_403_real(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_403_mmu(CPUPPCState *env)
+static void register_403_mmu_sprs(CPUPPCState *env)
{
/* MMU */
spr_register(env, SPR_40x_PID, "PID",
@@ -2586,7 +2586,7 @@ static void gen_spr_403_mmu(CPUPPCState *env)
}
/* SPR specific to PowerPC compression coprocessor extension */
-static void gen_spr_compress(CPUPPCState *env)
+static void register_compress_sprs(CPUPPCState *env)
{
/* XXX : not implemented */
spr_register(env, SPR_401_SKR, "SKR",
@@ -2595,7 +2595,7 @@ static void gen_spr_compress(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_5xx_8xx(CPUPPCState *env)
+static void register_5xx_8xx_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -2713,7 +2713,7 @@ static void gen_spr_5xx_8xx(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_5xx(CPUPPCState *env)
+static void register_5xx_sprs(CPUPPCState *env)
{
/* XXX : not implemented */
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
@@ -2822,7 +2822,7 @@ static void gen_spr_5xx(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_8xx(CPUPPCState *env)
+static void register_8xx_sprs(CPUPPCState *env)
{
/* XXX : not implemented */
spr_register(env, SPR_MPC_IC_CST, "IC_CST",
@@ -3557,9 +3557,9 @@ static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
static void init_proc_401(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401_sprs(env);
init_excp_4xx_real(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3603,10 +3603,10 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
static void init_proc_401x2(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401x2_sprs(env);
+ register_compress_sprs(env);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -3661,11 +3661,11 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
static void init_proc_401x3(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401_sprs(env);
+ register_401x2_sprs(env);
+ register_compress_sprs(env);
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3714,10 +3714,10 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
static void init_proc_IOP480(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_401x2(env);
- gen_spr_compress(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_401x2_sprs(env);
+ register_compress_sprs(env);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -3772,10 +3772,10 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
static void init_proc_403(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_403(env);
- gen_spr_403_real(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_403_sprs(env);
+ register_403_real_sprs(env);
init_excp_4xx_real(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -3819,11 +3819,11 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
static void init_proc_403GCX(CPUPPCState *env)
{
- gen_spr_40x(env);
- gen_spr_401_403(env);
- gen_spr_403(env);
- gen_spr_403_real(env);
- gen_spr_403_mmu(env);
+ register_40x_sprs(env);
+ register_401_403_sprs(env);
+ register_403_sprs(env);
+ register_403_real_sprs(env);
+ register_403_mmu_sprs(env);
/* Bus access control */
/* not emulated, as QEMU never does speculative access */
spr_register(env, SPR_40x_SGR, "SGR",
@@ -3887,9 +3887,9 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
static void init_proc_405(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_40x(env);
- gen_spr_405(env);
+ register_tbl(env);
+ register_40x_sprs(env);
+ register_405_sprs(env);
/* Bus access control */
/* not emulated, as QEMU never does speculative access */
spr_register(env, SPR_40x_SGR, "SGR",
@@ -3953,10 +3953,10 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
static void init_proc_440EP(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4095,10 +4095,10 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
static void init_proc_440GP(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4178,10 +4178,10 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
static void init_proc_440x4(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4261,10 +4261,10 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
static void init_proc_440x5(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000000000FFFFULL);
+ register_440_sprs(env);
+ register_usprgh_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4400,9 +4400,9 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
static void init_proc_MPC5xx(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_5xx_8xx(env);
- gen_spr_5xx(env);
+ register_tbl(env);
+ register_5xx_8xx_sprs(env);
+ register_5xx_sprs(env);
init_excp_MPC5xx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4444,9 +4444,9 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
static void init_proc_MPC8xx(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_5xx_8xx(env);
- gen_spr_8xx(env);
+ register_tbl(env);
+ register_5xx_8xx_sprs(env);
+ register_8xx_sprs(env);
init_excp_MPC8xx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4488,12 +4488,12 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
static void init_proc_G2(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_G2_755_sprs(env);
+ register_G2_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* External access control */
/* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
@@ -4517,9 +4517,9 @@ static void init_proc_G2(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_G2(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4567,12 +4567,12 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
static void init_proc_G2LE(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_G2_755(env);
- gen_spr_G2(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_G2_755_sprs(env);
+ register_G2_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* External access control */
/* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
@@ -4597,9 +4597,9 @@ static void init_proc_G2LE(CPUPPCState *env)
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_G2(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4650,15 +4650,15 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
static void init_proc_e200(CPUPPCState *env)
{
/* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000070000FFFFULL);
+ register_tbl(env);
+ register_BookE_sprs(env, 0x000000070000FFFFULL);
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
&spr_read_spefscr, &spr_write_spefscr,
&spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
- gen_spr_BookE206(env, 0x0000005D, NULL, 0);
+ register_BookE206_sprs(env, 0x0000005D, NULL, 0);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4804,11 +4804,11 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
static void init_proc_e300(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_603_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -4852,9 +4852,9 @@ static void init_proc_e300(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -4950,11 +4950,11 @@ static void init_proc_e500(CPUPPCState *env, int version)
#endif
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/*
* XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
* complain when accessing them.
- * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
*/
switch (version) {
case fsl_e500v1:
@@ -4970,8 +4970,8 @@ static void init_proc_e500(CPUPPCState *env, int version)
ivor_mask = 0x000003FF0000FFFFULL;
break;
}
- gen_spr_BookE(env, ivor_mask);
- gen_spr_usprg3(env);
+ register_BookE_sprs(env, ivor_mask);
+ register_usprg3_sprs(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4989,17 +4989,17 @@ static void init_proc_e500(CPUPPCState *env, int version)
env->id_tlbs = 0;
switch (version) {
case fsl_e500v1:
- tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
- tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
+ tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
break;
case fsl_e500v2:
- tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
- tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
break;
case fsl_e500mc:
case fsl_e5500:
- tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
- tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
+ tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
break;
case fsl_e6500:
mmucfg = 0x6510B45;
@@ -5036,7 +5036,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
env->spr[SPR_PVR]);
}
- gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
+ register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -5394,9 +5394,9 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
static void init_proc_601(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_601(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_601_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5510,11 +5510,11 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
static void init_proc_602(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_602(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_602_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5527,8 +5527,8 @@ static void init_proc_602(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_602(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5580,11 +5580,11 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
static void init_proc_603(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_603_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5597,8 +5597,8 @@ static void init_proc_603(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5647,11 +5647,11 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
static void init_proc_603E(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_603(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_603_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5664,8 +5664,8 @@ static void init_proc_603E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5714,11 +5714,11 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
static void init_proc_604(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_604(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_604_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5726,7 +5726,7 @@ static void init_proc_604(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_604(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5778,9 +5778,9 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
static void init_proc_604E(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_604(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_604_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
@@ -5797,7 +5797,7 @@ static void init_proc_604E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5810,7 +5810,7 @@ static void init_proc_604E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_604(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5862,13 +5862,13 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
static void init_proc_740(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5881,7 +5881,7 @@ static void init_proc_740(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_7x0(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5933,18 +5933,18 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
static void init_proc_750(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -5957,7 +5957,7 @@ static void init_proc_750(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/*
* XXX: high BATs are also present but are known to be bugged on
* die version 1.x
@@ -6013,16 +6013,16 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
static void init_proc_750cl(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
/* Those registers are fake on 750CL */
spr_register(env, SPR_THRM1, "THRM1",
@@ -6123,9 +6123,9 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750cl has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_750cl(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6216,18 +6216,18 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
static void init_proc_750cx(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* This register is not implemented but is present for compatibility */
spr_register(env, SPR_SDA, "SDA",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6245,9 +6245,9 @@ static void init_proc_750cx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750cx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_750cx(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6299,18 +6299,18 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
static void init_proc_750fx(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6333,9 +6333,9 @@ static void init_proc_750fx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_7x0(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6387,18 +6387,18 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
static void init_proc_750gx(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* XXX : not implemented (XXX: different from 750fx) */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* XXX : not implemented */
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6421,9 +6421,9 @@ static void init_proc_750gx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
+ register_high_BATs(env);
init_excp_7x0(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6475,14 +6475,14 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
static void init_proc_745(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- gen_spr_G2_755(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
+ register_G2_755_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -6500,9 +6500,9 @@ static void init_proc_745(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_7x5(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6551,12 +6551,12 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
static void init_proc_755(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
- gen_spr_G2_755(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
+ register_G2_755_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* L2 cache control */
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
@@ -6569,7 +6569,7 @@ static void init_proc_755(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
@@ -6587,9 +6587,9 @@ static void init_proc_755(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_7x5(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6638,13 +6638,13 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
static void init_proc_7400(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -6658,9 +6658,9 @@ static void init_proc_7400(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_7400(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6718,13 +6718,13 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
static void init_proc_7410(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -6732,7 +6732,7 @@ static void init_proc_7410(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Thermal management */
- gen_spr_thrm(env);
+ register_thrm_sprs(env);
/* L2PMCR */
/* XXX : not implemented */
spr_register(env, SPR_L2PMCR, "L2PMCR",
@@ -6746,7 +6746,7 @@ static void init_proc_7410(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
+ register_low_BATs(env);
init_excp_7400(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6804,13 +6804,13 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
static void init_proc_7440(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -6857,8 +6857,8 @@ static void init_proc_7440(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6913,16 +6913,16 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
static void init_proc_7450(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
- gen_l3_ctrl(env);
+ register_l3_ctrl(env);
/* L3ITCR1 */
/* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
@@ -6992,8 +6992,8 @@ static void init_proc_7450(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -7048,13 +7048,13 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
static void init_proc_7445(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* LDSTCR */
/* XXX : not implemented */
@@ -7129,9 +7129,9 @@ static void init_proc_7445(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -7186,16 +7186,16 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
static void init_proc_7455(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
- gen_l3_ctrl(env);
+ register_l3_ctrl(env);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
@@ -7269,9 +7269,9 @@ static void init_proc_7455(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -7326,16 +7326,16 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
static void init_proc_7457(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
- gen_l3_ctrl(env);
+ register_l3_ctrl(env);
/* L3ITCR1 */
/* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
@@ -7433,9 +7433,9 @@ static void init_proc_7457(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -7490,13 +7490,13 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
static void init_proc_e600(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_sdr1(env);
- gen_spr_7xx(env);
+ register_ne_601_sprs(env);
+ register_sdr1_sprs(env);
+ register_7xx_sprs(env);
/* Time base */
- gen_tbl(env);
+ register_tbl(env);
/* 74xx specific SPR */
- gen_spr_74xx(env);
+ register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
@@ -7572,9 +7572,9 @@ static void init_proc_e600(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
+ register_low_BATs(env);
+ register_high_BATs(env);
+ register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -7699,7 +7699,7 @@ static int check_pow_970(CPUPPCState *env)
return 0;
}
-static void gen_spr_970_hid(CPUPPCState *env)
+static void register_970_hid_sprs(CPUPPCState *env)
{
/* Hardware implementation registers */
/* XXX : not implemented */
@@ -7717,7 +7717,7 @@ static void gen_spr_970_hid(CPUPPCState *env)
POWERPC970_HID5_INIT);
}
-static void gen_spr_970_hior(CPUPPCState *env)
+static void register_970_hior_sprs(CPUPPCState *env)
{
spr_register(env, SPR_HIOR, "SPR_HIOR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7725,7 +7725,7 @@ static void gen_spr_970_hior(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_ctrl(CPUPPCState *env)
+static void register_book3s_ctrl_sprs(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7737,7 +7737,7 @@ static void gen_spr_book3s_ctrl(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_altivec(CPUPPCState *env)
+static void register_book3s_altivec_sprs(CPUPPCState *env)
{
if (!(env->insns_flags & PPC_ALTIVEC)) {
return;
@@ -7750,7 +7750,7 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
}
-static void gen_spr_book3s_dbg(CPUPPCState *env)
+static void register_book3s_dbg_sprs(CPUPPCState *env)
{
/*
* TODO: different specs define different scopes for these,
@@ -7769,7 +7769,7 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
KVM_REG_PPC_DABRX, 0x00000000);
}
-static void gen_spr_book3s_207_dbg(CPUPPCState *env)
+static void register_book3s_207_dbg_sprs(CPUPPCState *env)
{
spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7788,7 +7788,7 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
KVM_REG_PPC_CIABR, 0x00000000);
}
-static void gen_spr_970_dbg(CPUPPCState *env)
+static void register_970_dbg_sprs(CPUPPCState *env)
{
/* Breakpoints */
spr_register(env, SPR_IABR, "IABR",
@@ -7797,7 +7797,7 @@ static void gen_spr_970_dbg(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
+static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7845,7 +7845,7 @@ static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
KVM_REG_PPC_SDAR, 0x00000000);
}
-static void gen_spr_book3s_pmu_user(CPUPPCState *env)
+static void register_book3s_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
&spr_read_ureg, SPR_NOACCESS,
@@ -7893,7 +7893,7 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_970_pmu_sup(CPUPPCState *env)
+static void register_970_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_970_PMC7, "PMC7",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7905,7 +7905,7 @@ static void gen_spr_970_pmu_sup(CPUPPCState *env)
KVM_REG_PPC_PMC8, 0x00000000);
}
-static void gen_spr_970_pmu_user(CPUPPCState *env)
+static void register_970_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_970_UPMC7, "UPMC7",
&spr_read_ureg, SPR_NOACCESS,
@@ -7917,7 +7917,7 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power8_pmu_sup(CPUPPCState *env)
+static void register_power8_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7953,7 +7953,7 @@ static void gen_spr_power8_pmu_sup(CPUPPCState *env)
KVM_REG_PPC_CSIGR, 0x00000000);
}
-static void gen_spr_power8_pmu_user(CPUPPCState *env)
+static void register_power8_pmu_user_sprs(CPUPPCState *env)
{
spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
&spr_read_ureg, SPR_NOACCESS,
@@ -7965,7 +7965,7 @@ static void gen_spr_power8_pmu_user(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power5p_ear(CPUPPCState *env)
+static void register_power5p_ear_sprs(CPUPPCState *env)
{
/* External access control */
spr_register(env, SPR_EAR, "EAR",
@@ -7974,7 +7974,7 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power5p_tb(CPUPPCState *env)
+static void register_power5p_tb_sprs(CPUPPCState *env)
{
/* TBU40 (High 40 bits of the Timebase register */
spr_register_hv(env, SPR_TBU40, "TBU40",
@@ -8002,7 +8002,7 @@ static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
}
#endif /* !defined(CONFIG_USER_ONLY) */
-static void gen_spr_970_lpar(CPUPPCState *env)
+static void register_970_lpar_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/*
@@ -8019,7 +8019,7 @@ static void gen_spr_970_lpar(CPUPPCState *env)
#endif
}
-static void gen_spr_power5p_lpar(CPUPPCState *env)
+static void register_power5p_lpar_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* Logical partitionning */
@@ -8035,7 +8035,7 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
#endif
}
-static void gen_spr_book3s_ids(CPUPPCState *env)
+static void register_book3s_ids_sprs(CPUPPCState *env)
{
/* FIXME: Will need to deal with thread vs core only SPRs */
@@ -8127,7 +8127,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_rmor(CPUPPCState *env)
+static void register_rmor_sprs(CPUPPCState *env)
{
spr_register_hv(env, SPR_RMOR, "RMOR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -8136,7 +8136,7 @@ static void gen_spr_rmor(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power8_ids(CPUPPCState *env)
+static void register_power8_ids_sprs(CPUPPCState *env)
{
/* Thread identification */
spr_register(env, SPR_TIR, "TIR",
@@ -8145,7 +8145,7 @@ static void gen_spr_power8_ids(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_book3s_purr(CPUPPCState *env)
+static void register_book3s_purr_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
@@ -8162,7 +8162,7 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
#endif
}
-static void gen_spr_power6_dbg(CPUPPCState *env)
+static void register_power6_dbg_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_CFAR, "SPR_CFAR",
@@ -8172,7 +8172,7 @@ static void gen_spr_power6_dbg(CPUPPCState *env)
#endif
}
-static void gen_spr_power5p_common(CPUPPCState *env)
+static void register_power5p_common_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_PPR, "PPR",
&spr_read_generic, &spr_write_generic,
@@ -8180,7 +8180,7 @@ static void gen_spr_power5p_common(CPUPPCState *env)
KVM_REG_PPC_PPR, 0x00000000);
}
-static void gen_spr_power6_common(CPUPPCState *env)
+static void register_power6_common_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
@@ -8211,7 +8211,7 @@ static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
spr_write_generic(ctx, sprn, gprn);
}
-static void gen_spr_power8_tce_address_control(CPUPPCState *env)
+static void register_power8_tce_address_control_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TAR, "TAR",
&spr_read_tar, &spr_write_tar,
@@ -8243,7 +8243,7 @@ static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
spr_write_prev_upper32(ctx, sprn, gprn);
}
-static void gen_spr_power8_tm(CPUPPCState *env)
+static void register_power8_tm_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TFHAR, "TFHAR",
&spr_read_tm, &spr_write_tm,
@@ -8287,7 +8287,7 @@ static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
spr_write_prev_upper32(ctx, sprn, gprn);
}
-static void gen_spr_power8_ebb(CPUPPCState *env)
+static void register_power8_ebb_sprs(CPUPPCState *env)
{
spr_register(env, SPR_BESCRS, "BESCRS",
&spr_read_ebb, &spr_write_ebb,
@@ -8320,7 +8320,7 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
}
/* Virtual Time Base */
-static void gen_spr_vtb(CPUPPCState *env)
+static void register_vtb_sprs(CPUPPCState *env)
{
spr_register_kvm_hv(env, SPR_VTB, "VTB",
SPR_NOACCESS, SPR_NOACCESS,
@@ -8329,7 +8329,7 @@ static void gen_spr_vtb(CPUPPCState *env)
KVM_REG_PPC_VTB, 0x00000000);
}
-static void gen_spr_power8_fscr(CPUPPCState *env)
+static void register_power8_fscr_sprs(CPUPPCState *env)
{
#if defined(CONFIG_USER_ONLY)
target_ulong initval = 1ULL << FSCR_TAR;
@@ -8342,7 +8342,7 @@ static void gen_spr_power8_fscr(CPUPPCState *env)
KVM_REG_PPC_FSCR, initval);
}
-static void gen_spr_power8_pspb(CPUPPCState *env)
+static void register_power8_pspb_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_PSPB, "PSPB",
SPR_NOACCESS, SPR_NOACCESS,
@@ -8350,7 +8350,7 @@ static void gen_spr_power8_pspb(CPUPPCState *env)
KVM_REG_PPC_PSPB, 0);
}
-static void gen_spr_power8_dpdes(CPUPPCState *env)
+static void register_power8_dpdes_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* Directed Privileged Door-bell Exception State, used for IPI */
@@ -8362,7 +8362,7 @@ static void gen_spr_power8_dpdes(CPUPPCState *env)
#endif
}
-static void gen_spr_power8_ic(CPUPPCState *env)
+static void register_power8_ic_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register_hv(env, SPR_IC, "IC",
@@ -8373,7 +8373,7 @@ static void gen_spr_power8_ic(CPUPPCState *env)
#endif
}
-static void gen_spr_power8_book4(CPUPPCState *env)
+static void register_power8_book4_sprs(CPUPPCState *env)
{
/* Add a number of P8 book4 registers */
#if !defined(CONFIG_USER_ONLY)
@@ -8392,7 +8392,7 @@ static void gen_spr_power8_book4(CPUPPCState *env)
#endif
}
-static void gen_spr_power7_book4(CPUPPCState *env)
+static void register_power7_book4_sprs(CPUPPCState *env)
{
/* Add a number of P7 book4 registers */
#if !defined(CONFIG_USER_ONLY)
@@ -8407,7 +8407,7 @@ static void gen_spr_power7_book4(CPUPPCState *env)
#endif
}
-static void gen_spr_power8_rpr(CPUPPCState *env)
+static void register_power8_rpr_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register_hv(env, SPR_RPR, "RPR",
@@ -8418,7 +8418,7 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
#endif
}
-static void gen_spr_power9_mmu(CPUPPCState *env)
+static void register_power9_mmu_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
/* Partition Table Control */
@@ -8438,13 +8438,13 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_tbl(env);
- gen_spr_usprg3(env);
- gen_spr_book3s_altivec(env);
- gen_spr_book3s_pmu_sup(env);
- gen_spr_book3s_pmu_user(env);
- gen_spr_book3s_ctrl(env);
+ register_ne_601_sprs(env);
+ register_tbl(env);
+ register_usprg3_sprs(env);
+ register_book3s_altivec_sprs(env);
+ register_book3s_pmu_sup_sprs(env);
+ register_book3s_pmu_user_sprs(env);
+ register_book3s_ctrl_sprs(env);
/*
* Can't find information on what this should be on reset. This
* value is the one used by 74xx processors.
@@ -8456,17 +8456,17 @@ static void init_proc_970(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_dbg_sprs(env);
/* 970 Specific Registers */
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
- gen_spr_970_pmu_sup(env);
- gen_spr_970_pmu_user(env);
- gen_spr_970_lpar(env);
- gen_spr_970_dbg(env);
+ register_970_hid_sprs(env);
+ register_970_hior_sprs(env);
+ register_low_BATs(env);
+ register_970_pmu_sup_sprs(env);
+ register_970_pmu_user_sprs(env);
+ register_970_lpar_sprs(env);
+ register_970_dbg_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -8529,19 +8529,19 @@ static void init_proc_power5plus(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_dbg_sprs(env);
/* POWER5+ Specific Registers */
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
- gen_spr_970_pmu_sup(env);
- gen_spr_970_pmu_user(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
+ register_970_hid_sprs(env);
+ register_970_hior_sprs(env);
+ register_low_BATs(env);
+ register_970_pmu_sup_sprs(env);
+ register_970_pmu_user_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -8608,21 +8608,21 @@ static void init_proc_POWER7(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_dbg_sprs(env);
/* POWER7 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_rmor(env);
- gen_spr_amr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power7_book4(env);
+ register_book3s_ids_sprs(env);
+ register_rmor_sprs(env);
+ register_amr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power7_book4_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -8754,34 +8754,34 @@ static void init_proc_POWER8(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_sdr1(env);
- gen_spr_book3s_207_dbg(env);
+ register_sdr1_sprs(env);
+ register_book3s_207_dbg_sprs(env);
/* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_rmor(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_power8_dpdes(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
+ register_book3s_ids_sprs(env);
+ register_rmor_sprs(env);
+ register_amr_sprs(env);
+ register_iamr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power8_tce_address_control_sprs(env);
+ register_power8_ids_sprs(env);
+ register_power8_ebb_sprs(env);
+ register_power8_fscr_sprs(env);
+ register_power8_pmu_sup_sprs(env);
+ register_power8_pmu_user_sprs(env);
+ register_power8_tm_sprs(env);
+ register_power8_pspb_sprs(env);
+ register_power8_dpdes_sprs(env);
+ register_vtb_sprs(env);
+ register_power8_ic_sprs(env);
+ register_power8_book4_sprs(env);
+ register_power8_rpr_sprs(env);
/* env variables */
env->dcache_line_size = 128;
@@ -8951,33 +8951,33 @@ static void init_proc_POWER9(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_book3s_207_dbg(env);
+ register_book3s_207_dbg_sprs(env);
/* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power5p_tb(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_power8_dpdes(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
- gen_spr_power9_mmu(env);
+ register_book3s_ids_sprs(env);
+ register_amr_sprs(env);
+ register_iamr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power5p_tb_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power8_tce_address_control_sprs(env);
+ register_power8_ids_sprs(env);
+ register_power8_ebb_sprs(env);
+ register_power8_fscr_sprs(env);
+ register_power8_pmu_sup_sprs(env);
+ register_power8_pmu_user_sprs(env);
+ register_power8_tm_sprs(env);
+ register_power8_pspb_sprs(env);
+ register_power8_dpdes_sprs(env);
+ register_vtb_sprs(env);
+ register_power8_ic_sprs(env);
+ register_power8_book4_sprs(env);
+ register_power8_rpr_sprs(env);
+ register_power9_mmu_sprs(env);
/* POWER9 Specific registers */
spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
@@ -9169,31 +9169,31 @@ static void init_proc_POWER10(CPUPPCState *env)
{
/* Common Registers */
init_proc_book3s_common(env);
- gen_spr_book3s_207_dbg(env);
+ register_book3s_207_dbg_sprs(env);
/* POWER8 Specific Registers */
- gen_spr_book3s_ids(env);
- gen_spr_amr(env);
- gen_spr_iamr(env);
- gen_spr_book3s_purr(env);
- gen_spr_power5p_common(env);
- gen_spr_power5p_lpar(env);
- gen_spr_power5p_ear(env);
- gen_spr_power6_common(env);
- gen_spr_power6_dbg(env);
- gen_spr_power8_tce_address_control(env);
- gen_spr_power8_ids(env);
- gen_spr_power8_ebb(env);
- gen_spr_power8_fscr(env);
- gen_spr_power8_pmu_sup(env);
- gen_spr_power8_pmu_user(env);
- gen_spr_power8_tm(env);
- gen_spr_power8_pspb(env);
- gen_spr_vtb(env);
- gen_spr_power8_ic(env);
- gen_spr_power8_book4(env);
- gen_spr_power8_rpr(env);
- gen_spr_power9_mmu(env);
+ register_book3s_ids_sprs(env);
+ register_amr_sprs(env);
+ register_iamr_sprs(env);
+ register_book3s_purr_sprs(env);
+ register_power5p_common_sprs(env);
+ register_power5p_lpar_sprs(env);
+ register_power5p_ear_sprs(env);
+ register_power6_common_sprs(env);
+ register_power6_dbg_sprs(env);
+ register_power8_tce_address_control_sprs(env);
+ register_power8_ids_sprs(env);
+ register_power8_ebb_sprs(env);
+ register_power8_fscr_sprs(env);
+ register_power8_pmu_sup_sprs(env);
+ register_power8_pmu_user_sprs(env);
+ register_power8_tm_sprs(env);
+ register_power8_pspb_sprs(env);
+ register_vtb_sprs(env);
+ register_power8_ic_sprs(env);
+ register_power8_book4_sprs(env);
+ register_power8_rpr_sprs(env);
+ register_power9_mmu_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
@@ -9398,7 +9398,7 @@ static void init_ppc_proc(PowerPCCPU *cpu)
env->tlb_type = TLB_NONE;
#endif
/* Register SPR common to all PowerPC implementations */
- gen_spr_generic(env);
+ register_generic_sprs(env);
spr_register(env, SPR_PVR, "PVR",
/* Linux permits userspace to read PVR */
#if defined(CONFIG_LINUX_USER)
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 2/5] target/ppc: renamed SPR registration functions
2021-05-04 14:01 ` [PATCH v4 2/5] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
@ 2021-05-04 15:59 ` Richard Henderson
2021-05-05 4:11 ` David Gibson
1 sibling, 0 replies; 14+ messages in thread
From: Richard Henderson @ 2021-05-04 15:59 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 5/4/21 7:01 AM, Bruno Larsen (billionai) wrote:
> Renamed all gen_spr_* and gen_* functions specifically related to
> registering SPRs to register_*_sprs and register_*, to avoid future
> confusion with other TCG related code.
>
> Signed-off-by: Bruno Larsen (billionai)<bruno.larsen@eldorado.org.br>
> ---
> target/ppc/translate_init.c.inc | 860 ++++++++++++++++----------------
> 1 file changed, 430 insertions(+), 430 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 2/5] target/ppc: renamed SPR registration functions
2021-05-04 14:01 ` [PATCH v4 2/5] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
2021-05-04 15:59 ` Richard Henderson
@ 2021-05-05 4:11 ` David Gibson
1 sibling, 0 replies; 14+ messages in thread
From: David Gibson @ 2021-05-05 4:11 UTC (permalink / raw)
To: Bruno Larsen (billionai)
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 73795 bytes --]
On Tue, May 04, 2021 at 11:01:54AM -0300, Bruno Larsen (billionai) wrote:
> Renamed all gen_spr_* and gen_* functions specifically related to
> registering SPRs to register_*_sprs and register_*, to avoid future
> confusion with other TCG related code.
>
> Signed-off-by: Bruno Larsen (billionai)
> <bruno.larsen@eldorado.org.br>
Sorry, this doesn't apply cleanly to the ppc-for-6.1 branch. Can you
rebase please.
> ---
> target/ppc/translate_init.c.inc | 860 ++++++++++++++++----------------
> 1 file changed, 430 insertions(+), 430 deletions(-)
>
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index d5527c149f..4fac8a9950 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -842,7 +842,7 @@ static void _spr_register(CPUPPCState *env, int num, const char *name,
> oea_read, oea_write, 0, ival)
>
> /* Generic PowerPC SPRs */
> -static void gen_spr_generic(CPUPPCState *env)
> +static void register_generic_sprs(CPUPPCState *env)
> {
> /* Integer processing */
> spr_register(env, SPR_XER, "XER",
> @@ -887,7 +887,7 @@ static void gen_spr_generic(CPUPPCState *env)
> }
>
> /* SPR common to all non-embedded PowerPC, including 601 */
> -static void gen_spr_ne_601(CPUPPCState *env)
> +static void register_ne_601_sprs(CPUPPCState *env)
> {
> /* Exception processing */
> spr_register_kvm(env, SPR_DSISR, "DSISR",
> @@ -906,7 +906,7 @@ static void gen_spr_ne_601(CPUPPCState *env)
> }
>
> /* Storage Description Register 1 */
> -static void gen_spr_sdr1(CPUPPCState *env)
> +static void register_sdr1_sprs(CPUPPCState *env)
> {
> #ifndef CONFIG_USER_ONLY
> if (env->has_hv_mode) {
> @@ -929,7 +929,7 @@ static void gen_spr_sdr1(CPUPPCState *env)
> }
>
> /* BATs 0-3 */
> -static void gen_low_BATs(CPUPPCState *env)
> +static void register_low_BATs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register(env, SPR_IBAT0U, "IBAT0U",
> @@ -1001,7 +1001,7 @@ static void gen_low_BATs(CPUPPCState *env)
> }
>
> /* BATs 4-7 */
> -static void gen_high_BATs(CPUPPCState *env)
> +static void register_high_BATs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register(env, SPR_IBAT4U, "IBAT4U",
> @@ -1073,7 +1073,7 @@ static void gen_high_BATs(CPUPPCState *env)
> }
>
> /* Generic PowerPC time base */
> -static void gen_tbl(CPUPPCState *env)
> +static void register_tbl(CPUPPCState *env)
> {
> spr_register(env, SPR_VTBL, "TBL",
> &spr_read_tbl, SPR_NOACCESS,
> @@ -1094,7 +1094,7 @@ static void gen_tbl(CPUPPCState *env)
> }
>
> /* Softare table search registers */
> -static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> +static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> {
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = nb_tlbs;
> @@ -1133,7 +1133,7 @@ static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> }
>
> /* SPR common to MPC755 and G2 */
> -static void gen_spr_G2_755(CPUPPCState *env)
> +static void register_G2_755_sprs(CPUPPCState *env)
> {
> /* SGPRs */
> spr_register(env, SPR_SPRG4, "SPRG4",
> @@ -1155,7 +1155,7 @@ static void gen_spr_G2_755(CPUPPCState *env)
> }
>
> /* SPR common to all 7xx PowerPC implementations */
> -static void gen_spr_7xx(CPUPPCState *env)
> +static void register_7xx_sprs(CPUPPCState *env)
> {
> /* Breakpoints */
> /* XXX : not implemented */
> @@ -1353,7 +1353,7 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
> }
> #endif /* CONFIG_USER_ONLY */
>
> -static void gen_spr_amr(CPUPPCState *env)
> +static void register_amr_sprs(CPUPPCState *env)
> {
> #ifndef CONFIG_USER_ONLY
> /*
> @@ -1385,7 +1385,7 @@ static void gen_spr_amr(CPUPPCState *env)
> #endif /* !CONFIG_USER_ONLY */
> }
>
> -static void gen_spr_iamr(CPUPPCState *env)
> +static void register_iamr_sprs(CPUPPCState *env)
> {
> #ifndef CONFIG_USER_ONLY
> spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
> @@ -1406,7 +1406,7 @@ static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static void gen_spr_thrm(CPUPPCState *env)
> +static void register_thrm_sprs(CPUPPCState *env)
> {
> /* Thermal management */
> /* XXX : not implemented */
> @@ -1427,7 +1427,7 @@ static void gen_spr_thrm(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 604 implementation */
> -static void gen_spr_604(CPUPPCState *env)
> +static void register_604_sprs(CPUPPCState *env)
> {
> /* Processor identification */
> spr_register(env, SPR_PIR, "PIR",
> @@ -1480,7 +1480,7 @@ static void gen_spr_604(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 603 implementation */
> -static void gen_spr_603(CPUPPCState *env)
> +static void register_603_sprs(CPUPPCState *env)
> {
> /* External access control */
> /* XXX : not implemented */
> @@ -1498,7 +1498,7 @@ static void gen_spr_603(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC G2 implementation */
> -static void gen_spr_G2(CPUPPCState *env)
> +static void register_G2_sprs(CPUPPCState *env)
> {
> /* Memory base address */
> /* MBAR */
> @@ -1550,7 +1550,7 @@ static void gen_spr_G2(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 602 implementation */
> -static void gen_spr_602(CPUPPCState *env)
> +static void register_602_sprs(CPUPPCState *env)
> {
> /* ESA registers */
> /* XXX : not implemented */
> @@ -1598,7 +1598,7 @@ static void gen_spr_602(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 601 implementation */
> -static void gen_spr_601(CPUPPCState *env)
> +static void register_601_sprs(CPUPPCState *env)
> {
> /* Multiplication/division register */
> /* MQ */
> @@ -1674,7 +1674,7 @@ static void gen_spr_601(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_74xx(CPUPPCState *env)
> +static void register_74xx_sprs(CPUPPCState *env)
> {
> /* Processor identification */
> spr_register(env, SPR_PIR, "PIR",
> @@ -1724,7 +1724,7 @@ static void gen_spr_74xx(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_l3_ctrl(CPUPPCState *env)
> +static void register_l3_ctrl(CPUPPCState *env)
> {
> /* L3CR */
> /* XXX : not implemented */
> @@ -1746,7 +1746,7 @@ static void gen_l3_ctrl(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> +static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> {
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = nb_tlbs;
> @@ -1822,7 +1822,7 @@ static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
>
> #endif
>
> -static void gen_spr_usprg3(CPUPPCState *env)
> +static void register_usprg3_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_USPRG3, "USPRG3",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -1830,7 +1830,7 @@ static void gen_spr_usprg3(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_usprgh(CPUPPCState *env)
> +static void register_usprgh_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_USPRG4, "USPRG4",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -1851,7 +1851,7 @@ static void gen_spr_usprgh(CPUPPCState *env)
> }
>
> /* PowerPC BookE SPR */
> -static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
> +static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
> {
> const char *ivor_names[64] = {
> "IVOR0", "IVOR1", "IVOR2", "IVOR3",
> @@ -2027,7 +2027,7 @@ static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
> 0x00000000);
> }
>
> -static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
> +static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
> uint32_t maxsize, uint32_t flags,
> uint32_t nentries)
> {
> @@ -2038,7 +2038,7 @@ static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
> }
>
> /* BookE 2.06 storage control registers */
> -static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
> +static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
> uint32_t *tlbncfg, uint32_t mmucfg)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -2126,11 +2126,11 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
> }
> #endif
>
> - gen_spr_usprgh(env);
> + register_usprgh_sprs(env);
> }
>
> /* SPR specific to PowerPC 440 implementation */
> -static void gen_spr_440(CPUPPCState *env)
> +static void register_440_sprs(CPUPPCState *env)
> {
> /* Cache control */
> /* XXX : not implemented */
> @@ -2271,7 +2271,7 @@ static void gen_spr_440(CPUPPCState *env)
> }
>
> /* SPR shared between PowerPC 40x implementations */
> -static void gen_spr_40x(CPUPPCState *env)
> +static void register_40x_sprs(CPUPPCState *env)
> {
> /* Cache */
> /* not emulated, as QEMU do not emulate caches */
> @@ -2326,7 +2326,7 @@ static void gen_spr_40x(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 405 implementation */
> -static void gen_spr_405(CPUPPCState *env)
> +static void register_405_sprs(CPUPPCState *env)
> {
> /* MMU */
> spr_register(env, SPR_40x_PID, "PID",
> @@ -2428,11 +2428,11 @@ static void gen_spr_405(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> spr_read_generic, &spr_write_generic,
> 0x00000000);
> - gen_spr_usprgh(env);
> + register_usprgh_sprs(env);
> }
>
> /* SPR shared between PowerPC 401 & 403 implementations */
> -static void gen_spr_401_403(CPUPPCState *env)
> +static void register_401_403_sprs(CPUPPCState *env)
> {
> /* Time base */
> spr_register(env, SPR_403_VTBL, "TBL",
> @@ -2460,7 +2460,7 @@ static void gen_spr_401_403(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 401 implementation */
> -static void gen_spr_401(CPUPPCState *env)
> +static void register_401_sprs(CPUPPCState *env)
> {
> /* Debug interface */
> /* XXX : not implemented */
> @@ -2502,9 +2502,9 @@ static void gen_spr_401(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_401x2(CPUPPCState *env)
> +static void register_401x2_sprs(CPUPPCState *env)
> {
> - gen_spr_401(env);
> + register_401_sprs(env);
> spr_register(env, SPR_40x_PID, "PID",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> @@ -2516,7 +2516,7 @@ static void gen_spr_401x2(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC 403 implementation */
> -static void gen_spr_403(CPUPPCState *env)
> +static void register_403_sprs(CPUPPCState *env)
> {
> /* Debug interface */
> /* XXX : not implemented */
> @@ -2552,7 +2552,7 @@ static void gen_spr_403(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_403_real(CPUPPCState *env)
> +static void register_403_real_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_403_PBL1, "PBL1",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -2572,7 +2572,7 @@ static void gen_spr_403_real(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_403_mmu(CPUPPCState *env)
> +static void register_403_mmu_sprs(CPUPPCState *env)
> {
> /* MMU */
> spr_register(env, SPR_40x_PID, "PID",
> @@ -2586,7 +2586,7 @@ static void gen_spr_403_mmu(CPUPPCState *env)
> }
>
> /* SPR specific to PowerPC compression coprocessor extension */
> -static void gen_spr_compress(CPUPPCState *env)
> +static void register_compress_sprs(CPUPPCState *env)
> {
> /* XXX : not implemented */
> spr_register(env, SPR_401_SKR, "SKR",
> @@ -2595,7 +2595,7 @@ static void gen_spr_compress(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_5xx_8xx(CPUPPCState *env)
> +static void register_5xx_8xx_sprs(CPUPPCState *env)
> {
> /* Exception processing */
> spr_register_kvm(env, SPR_DSISR, "DSISR",
> @@ -2713,7 +2713,7 @@ static void gen_spr_5xx_8xx(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_5xx(CPUPPCState *env)
> +static void register_5xx_sprs(CPUPPCState *env)
> {
> /* XXX : not implemented */
> spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
> @@ -2822,7 +2822,7 @@ static void gen_spr_5xx(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_8xx(CPUPPCState *env)
> +static void register_8xx_sprs(CPUPPCState *env)
> {
> /* XXX : not implemented */
> spr_register(env, SPR_MPC_IC_CST, "IC_CST",
> @@ -3557,9 +3557,9 @@ static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
>
> static void init_proc_401(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401_sprs(env);
> init_excp_4xx_real(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -3603,10 +3603,10 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
>
> static void init_proc_401x2(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401x2(env);
> - gen_spr_compress(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401x2_sprs(env);
> + register_compress_sprs(env);
> /* Memory management */
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> @@ -3661,11 +3661,11 @@ POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
>
> static void init_proc_401x3(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401(env);
> - gen_spr_401x2(env);
> - gen_spr_compress(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401_sprs(env);
> + register_401x2_sprs(env);
> + register_compress_sprs(env);
> init_excp_4xx_softmmu(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -3714,10 +3714,10 @@ POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
>
> static void init_proc_IOP480(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_401x2(env);
> - gen_spr_compress(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_401x2_sprs(env);
> + register_compress_sprs(env);
> /* Memory management */
> #if !defined(CONFIG_USER_ONLY)
> env->nb_tlb = 64;
> @@ -3772,10 +3772,10 @@ POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
>
> static void init_proc_403(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_403(env);
> - gen_spr_403_real(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_403_sprs(env);
> + register_403_real_sprs(env);
> init_excp_4xx_real(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -3819,11 +3819,11 @@ POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
>
> static void init_proc_403GCX(CPUPPCState *env)
> {
> - gen_spr_40x(env);
> - gen_spr_401_403(env);
> - gen_spr_403(env);
> - gen_spr_403_real(env);
> - gen_spr_403_mmu(env);
> + register_40x_sprs(env);
> + register_401_403_sprs(env);
> + register_403_sprs(env);
> + register_403_real_sprs(env);
> + register_403_mmu_sprs(env);
> /* Bus access control */
> /* not emulated, as QEMU never does speculative access */
> spr_register(env, SPR_40x_SGR, "SGR",
> @@ -3887,9 +3887,9 @@ POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
> static void init_proc_405(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_40x(env);
> - gen_spr_405(env);
> + register_tbl(env);
> + register_40x_sprs(env);
> + register_405_sprs(env);
> /* Bus access control */
> /* not emulated, as QEMU never does speculative access */
> spr_register(env, SPR_40x_SGR, "SGR",
> @@ -3953,10 +3953,10 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> static void init_proc_440EP(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4095,10 +4095,10 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
> static void init_proc_440GP(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4178,10 +4178,10 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
> static void init_proc_440x4(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4261,10 +4261,10 @@ POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
> static void init_proc_440x5(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000000000FFFFULL);
> - gen_spr_440(env);
> - gen_spr_usprgh(env);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000000000FFFFULL);
> + register_440_sprs(env);
> + register_usprgh_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4400,9 +4400,9 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
> static void init_proc_MPC5xx(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_5xx_8xx(env);
> - gen_spr_5xx(env);
> + register_tbl(env);
> + register_5xx_8xx_sprs(env);
> + register_5xx_sprs(env);
> init_excp_MPC5xx(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4444,9 +4444,9 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
> static void init_proc_MPC8xx(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_5xx_8xx(env);
> - gen_spr_8xx(env);
> + register_tbl(env);
> + register_5xx_8xx_sprs(env);
> + register_8xx_sprs(env);
> init_excp_MPC8xx(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4488,12 +4488,12 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
>
> static void init_proc_G2(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_G2_755(env);
> - gen_spr_G2(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_G2_755_sprs(env);
> + register_G2_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* External access control */
> /* XXX : not implemented */
> spr_register(env, SPR_EAR, "EAR",
> @@ -4517,9 +4517,9 @@ static void init_proc_G2(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_G2(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4567,12 +4567,12 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
>
> static void init_proc_G2LE(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_G2_755(env);
> - gen_spr_G2(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_G2_755_sprs(env);
> + register_G2_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* External access control */
> /* XXX : not implemented */
> spr_register(env, SPR_EAR, "EAR",
> @@ -4597,9 +4597,9 @@ static void init_proc_G2LE(CPUPPCState *env)
> 0x00000000);
>
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_G2(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4650,15 +4650,15 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
> static void init_proc_e200(CPUPPCState *env)
> {
> /* Time base */
> - gen_tbl(env);
> - gen_spr_BookE(env, 0x000000070000FFFFULL);
> + register_tbl(env);
> + register_BookE_sprs(env, 0x000000070000FFFFULL);
> /* XXX : not implemented */
> spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
> &spr_read_spefscr, &spr_write_spefscr,
> &spr_read_spefscr, &spr_write_spefscr,
> 0x00000000);
> /* Memory management */
> - gen_spr_BookE206(env, 0x0000005D, NULL, 0);
> + register_BookE206_sprs(env, 0x0000005D, NULL, 0);
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4804,11 +4804,11 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
>
> static void init_proc_e300(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_603(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_603_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -4852,9 +4852,9 @@ static void init_proc_e300(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_603(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -4950,11 +4950,11 @@ static void init_proc_e500(CPUPPCState *env, int version)
> #endif
>
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /*
> * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
> * complain when accessing them.
> - * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
> + * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
> */
> switch (version) {
> case fsl_e500v1:
> @@ -4970,8 +4970,8 @@ static void init_proc_e500(CPUPPCState *env, int version)
> ivor_mask = 0x000003FF0000FFFFULL;
> break;
> }
> - gen_spr_BookE(env, ivor_mask);
> - gen_spr_usprg3(env);
> + register_BookE_sprs(env, ivor_mask);
> + register_usprg3_sprs(env);
> /* Processor identification */
> spr_register(env, SPR_BOOKE_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4989,17 +4989,17 @@ static void init_proc_e500(CPUPPCState *env, int version)
> env->id_tlbs = 0;
> switch (version) {
> case fsl_e500v1:
> - tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
> - tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> + tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
> + tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> break;
> case fsl_e500v2:
> - tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
> - tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> + tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
> + tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
> break;
> case fsl_e500mc:
> case fsl_e5500:
> - tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
> - tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
> + tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
> + tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
> break;
> case fsl_e6500:
> mmucfg = 0x6510B45;
> @@ -5036,7 +5036,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
> cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> }
> - gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
> + register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -5394,9 +5394,9 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
>
> static void init_proc_601(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_601(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_601_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5510,11 +5510,11 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
>
> static void init_proc_602(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_602(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_602_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5527,8 +5527,8 @@ static void init_proc_602(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_602(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5580,11 +5580,11 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
>
> static void init_proc_603(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_603(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_603_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5597,8 +5597,8 @@ static void init_proc_603(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_603(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5647,11 +5647,11 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
>
> static void init_proc_603E(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_603(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_603_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5664,8 +5664,8 @@ static void init_proc_603E(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_603(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5714,11 +5714,11 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
>
> static void init_proc_604(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_604(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_604_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5726,7 +5726,7 @@ static void init_proc_604(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_604(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5778,9 +5778,9 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
>
> static void init_proc_604E(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_604(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_604_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_7XX_MMCR1, "MMCR1",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -5797,7 +5797,7 @@ static void init_proc_604E(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5810,7 +5810,7 @@ static void init_proc_604E(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_604(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5862,13 +5862,13 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
>
> static void init_proc_740(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5881,7 +5881,7 @@ static void init_proc_740(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_7x0(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5933,18 +5933,18 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
>
> static void init_proc_750(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -5957,7 +5957,7 @@ static void init_proc_750(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /*
> * XXX: high BATs are also present but are known to be bugged on
> * die version 1.x
> @@ -6013,16 +6013,16 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
>
> static void init_proc_750cl(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> /* Those registers are fake on 750CL */
> spr_register(env, SPR_THRM1, "THRM1",
> @@ -6123,9 +6123,9 @@ static void init_proc_750cl(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750cl has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_750cl(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6216,18 +6216,18 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
>
> static void init_proc_750cx(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* This register is not implemented but is present for compatibility */
> spr_register(env, SPR_SDA, "SDA",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6245,9 +6245,9 @@ static void init_proc_750cx(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750cx has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_750cx(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6299,18 +6299,18 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
>
> static void init_proc_750fx(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_750_THRM4, "THRM4",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6333,9 +6333,9 @@ static void init_proc_750fx(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_7x0(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6387,18 +6387,18 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
>
> static void init_proc_750gx(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* XXX : not implemented (XXX: different from 750fx) */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* XXX : not implemented */
> spr_register(env, SPR_750_THRM4, "THRM4",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -6421,9 +6421,9 @@ static void init_proc_750gx(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
> - gen_high_BATs(env);
> + register_high_BATs(env);
> init_excp_7x0(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6475,14 +6475,14 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
>
> static void init_proc_745(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> - gen_spr_G2_755(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> + register_G2_755_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -6500,9 +6500,9 @@ static void init_proc_745(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_7x5(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6551,12 +6551,12 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
>
> static void init_proc_755(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> - gen_spr_G2_755(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> + register_G2_755_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* L2 cache control */
> /* XXX : not implemented */
> spr_register(env, SPR_L2CR, "L2CR",
> @@ -6569,7 +6569,7 @@ static void init_proc_755(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -6587,9 +6587,9 @@ static void init_proc_755(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_6xx_7xx_soft_tlb(env, 64, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_6xx_7xx_soft_tlb(env, 64, 2);
> init_excp_7x5(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6638,13 +6638,13 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
>
> static void init_proc_7400(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -6658,9 +6658,9 @@ static void init_proc_7400(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_7400(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6718,13 +6718,13 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
>
> static void init_proc_7410(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -6732,7 +6732,7 @@ static void init_proc_7410(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Thermal management */
> - gen_spr_thrm(env);
> + register_thrm_sprs(env);
> /* L2PMCR */
> /* XXX : not implemented */
> spr_register(env, SPR_L2PMCR, "L2PMCR",
> @@ -6746,7 +6746,7 @@ static void init_proc_7410(CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> + register_low_BATs(env);
> init_excp_7400(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6804,13 +6804,13 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
>
> static void init_proc_7440(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -6857,8 +6857,8 @@ static void init_proc_7440(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6913,16 +6913,16 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
>
> static void init_proc_7450(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> - gen_l3_ctrl(env);
> + register_l3_ctrl(env);
> /* L3ITCR1 */
> /* XXX : not implemented */
> spr_register(env, SPR_L3ITCR1, "L3ITCR1",
> @@ -6992,8 +6992,8 @@ static void init_proc_7450(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -7048,13 +7048,13 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
>
> static void init_proc_7445(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* LDSTCR */
> /* XXX : not implemented */
> @@ -7129,9 +7129,9 @@ static void init_proc_7445(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -7186,16 +7186,16 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
>
> static void init_proc_7455(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> - gen_l3_ctrl(env);
> + register_l3_ctrl(env);
> /* LDSTCR */
> /* XXX : not implemented */
> spr_register(env, SPR_LDSTCR, "LDSTCR",
> @@ -7269,9 +7269,9 @@ static void init_proc_7455(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -7326,16 +7326,16 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
>
> static void init_proc_7457(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* Level 3 cache control */
> - gen_l3_ctrl(env);
> + register_l3_ctrl(env);
> /* L3ITCR1 */
> /* XXX : not implemented */
> spr_register(env, SPR_L3ITCR1, "L3ITCR1",
> @@ -7433,9 +7433,9 @@ static void init_proc_7457(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -7490,13 +7490,13 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
>
> static void init_proc_e600(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_sdr1(env);
> - gen_spr_7xx(env);
> + register_ne_601_sprs(env);
> + register_sdr1_sprs(env);
> + register_7xx_sprs(env);
> /* Time base */
> - gen_tbl(env);
> + register_tbl(env);
> /* 74xx specific SPR */
> - gen_spr_74xx(env);
> + register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> /* XXX : not implemented */
> spr_register(env, SPR_UBAMR, "UBAMR",
> @@ -7572,9 +7572,9 @@ static void init_proc_e600(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> /* Memory management */
> - gen_low_BATs(env);
> - gen_high_BATs(env);
> - gen_74xx_soft_tlb(env, 128, 2);
> + register_low_BATs(env);
> + register_high_BATs(env);
> + register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -7699,7 +7699,7 @@ static int check_pow_970(CPUPPCState *env)
> return 0;
> }
>
> -static void gen_spr_970_hid(CPUPPCState *env)
> +static void register_970_hid_sprs(CPUPPCState *env)
> {
> /* Hardware implementation registers */
> /* XXX : not implemented */
> @@ -7717,7 +7717,7 @@ static void gen_spr_970_hid(CPUPPCState *env)
> POWERPC970_HID5_INIT);
> }
>
> -static void gen_spr_970_hior(CPUPPCState *env)
> +static void register_970_hior_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_HIOR, "SPR_HIOR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7725,7 +7725,7 @@ static void gen_spr_970_hior(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_ctrl(CPUPPCState *env)
> +static void register_book3s_ctrl_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_CTRL, "SPR_CTRL",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7737,7 +7737,7 @@ static void gen_spr_book3s_ctrl(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_altivec(CPUPPCState *env)
> +static void register_book3s_altivec_sprs(CPUPPCState *env)
> {
> if (!(env->insns_flags & PPC_ALTIVEC)) {
> return;
> @@ -7750,7 +7750,7 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
>
> }
>
> -static void gen_spr_book3s_dbg(CPUPPCState *env)
> +static void register_book3s_dbg_sprs(CPUPPCState *env)
> {
> /*
> * TODO: different specs define different scopes for these,
> @@ -7769,7 +7769,7 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
> KVM_REG_PPC_DABRX, 0x00000000);
> }
>
> -static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> +static void register_book3s_207_dbg_sprs(CPUPPCState *env)
> {
> spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7788,7 +7788,7 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> KVM_REG_PPC_CIABR, 0x00000000);
> }
>
> -static void gen_spr_970_dbg(CPUPPCState *env)
> +static void register_970_dbg_sprs(CPUPPCState *env)
> {
> /* Breakpoints */
> spr_register(env, SPR_IABR, "IABR",
> @@ -7797,7 +7797,7 @@ static void gen_spr_970_dbg(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
> +static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7845,7 +7845,7 @@ static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
> KVM_REG_PPC_SDAR, 0x00000000);
> }
>
> -static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> +static void register_book3s_pmu_user_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -7893,7 +7893,7 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_970_pmu_sup(CPUPPCState *env)
> +static void register_970_pmu_sup_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_970_PMC7, "PMC7",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7905,7 +7905,7 @@ static void gen_spr_970_pmu_sup(CPUPPCState *env)
> KVM_REG_PPC_PMC8, 0x00000000);
> }
>
> -static void gen_spr_970_pmu_user(CPUPPCState *env)
> +static void register_970_pmu_user_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_970_UPMC7, "UPMC7",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -7917,7 +7917,7 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power8_pmu_sup(CPUPPCState *env)
> +static void register_power8_pmu_sup_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7953,7 +7953,7 @@ static void gen_spr_power8_pmu_sup(CPUPPCState *env)
> KVM_REG_PPC_CSIGR, 0x00000000);
> }
>
> -static void gen_spr_power8_pmu_user(CPUPPCState *env)
> +static void register_power8_pmu_user_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
> &spr_read_ureg, SPR_NOACCESS,
> @@ -7965,7 +7965,7 @@ static void gen_spr_power8_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power5p_ear(CPUPPCState *env)
> +static void register_power5p_ear_sprs(CPUPPCState *env)
> {
> /* External access control */
> spr_register(env, SPR_EAR, "EAR",
> @@ -7974,7 +7974,7 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power5p_tb(CPUPPCState *env)
> +static void register_power5p_tb_sprs(CPUPPCState *env)
> {
> /* TBU40 (High 40 bits of the Timebase register */
> spr_register_hv(env, SPR_TBU40, "TBU40",
> @@ -8002,7 +8002,7 @@ static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
> }
> #endif /* !defined(CONFIG_USER_ONLY) */
>
> -static void gen_spr_970_lpar(CPUPPCState *env)
> +static void register_970_lpar_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /*
> @@ -8019,7 +8019,7 @@ static void gen_spr_970_lpar(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power5p_lpar(CPUPPCState *env)
> +static void register_power5p_lpar_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* Logical partitionning */
> @@ -8035,7 +8035,7 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_book3s_ids(CPUPPCState *env)
> +static void register_book3s_ids_sprs(CPUPPCState *env)
> {
> /* FIXME: Will need to deal with thread vs core only SPRs */
>
> @@ -8127,7 +8127,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_rmor(CPUPPCState *env)
> +static void register_rmor_sprs(CPUPPCState *env)
> {
> spr_register_hv(env, SPR_RMOR, "RMOR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -8136,7 +8136,7 @@ static void gen_spr_rmor(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_power8_ids(CPUPPCState *env)
> +static void register_power8_ids_sprs(CPUPPCState *env)
> {
> /* Thread identification */
> spr_register(env, SPR_TIR, "TIR",
> @@ -8145,7 +8145,7 @@ static void gen_spr_power8_ids(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void gen_spr_book3s_purr(CPUPPCState *env)
> +static void register_book3s_purr_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
> @@ -8162,7 +8162,7 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power6_dbg(CPUPPCState *env)
> +static void register_power6_dbg_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register(env, SPR_CFAR, "SPR_CFAR",
> @@ -8172,7 +8172,7 @@ static void gen_spr_power6_dbg(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power5p_common(CPUPPCState *env)
> +static void register_power5p_common_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_PPR, "PPR",
> &spr_read_generic, &spr_write_generic,
> @@ -8180,7 +8180,7 @@ static void gen_spr_power5p_common(CPUPPCState *env)
> KVM_REG_PPC_PPR, 0x00000000);
> }
>
> -static void gen_spr_power6_common(CPUPPCState *env)
> +static void register_power6_common_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
> @@ -8211,7 +8211,7 @@ static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
> spr_write_generic(ctx, sprn, gprn);
> }
>
> -static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> +static void register_power8_tce_address_control_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TAR, "TAR",
> &spr_read_tar, &spr_write_tar,
> @@ -8243,7 +8243,7 @@ static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
> spr_write_prev_upper32(ctx, sprn, gprn);
> }
>
> -static void gen_spr_power8_tm(CPUPPCState *env)
> +static void register_power8_tm_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TFHAR, "TFHAR",
> &spr_read_tm, &spr_write_tm,
> @@ -8287,7 +8287,7 @@ static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
> spr_write_prev_upper32(ctx, sprn, gprn);
> }
>
> -static void gen_spr_power8_ebb(CPUPPCState *env)
> +static void register_power8_ebb_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_BESCRS, "BESCRS",
> &spr_read_ebb, &spr_write_ebb,
> @@ -8320,7 +8320,7 @@ static void gen_spr_power8_ebb(CPUPPCState *env)
> }
>
> /* Virtual Time Base */
> -static void gen_spr_vtb(CPUPPCState *env)
> +static void register_vtb_sprs(CPUPPCState *env)
> {
> spr_register_kvm_hv(env, SPR_VTB, "VTB",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -8329,7 +8329,7 @@ static void gen_spr_vtb(CPUPPCState *env)
> KVM_REG_PPC_VTB, 0x00000000);
> }
>
> -static void gen_spr_power8_fscr(CPUPPCState *env)
> +static void register_power8_fscr_sprs(CPUPPCState *env)
> {
> #if defined(CONFIG_USER_ONLY)
> target_ulong initval = 1ULL << FSCR_TAR;
> @@ -8342,7 +8342,7 @@ static void gen_spr_power8_fscr(CPUPPCState *env)
> KVM_REG_PPC_FSCR, initval);
> }
>
> -static void gen_spr_power8_pspb(CPUPPCState *env)
> +static void register_power8_pspb_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_PSPB, "PSPB",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -8350,7 +8350,7 @@ static void gen_spr_power8_pspb(CPUPPCState *env)
> KVM_REG_PPC_PSPB, 0);
> }
>
> -static void gen_spr_power8_dpdes(CPUPPCState *env)
> +static void register_power8_dpdes_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* Directed Privileged Door-bell Exception State, used for IPI */
> @@ -8362,7 +8362,7 @@ static void gen_spr_power8_dpdes(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power8_ic(CPUPPCState *env)
> +static void register_power8_ic_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register_hv(env, SPR_IC, "IC",
> @@ -8373,7 +8373,7 @@ static void gen_spr_power8_ic(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power8_book4(CPUPPCState *env)
> +static void register_power8_book4_sprs(CPUPPCState *env)
> {
> /* Add a number of P8 book4 registers */
> #if !defined(CONFIG_USER_ONLY)
> @@ -8392,7 +8392,7 @@ static void gen_spr_power8_book4(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power7_book4(CPUPPCState *env)
> +static void register_power7_book4_sprs(CPUPPCState *env)
> {
> /* Add a number of P7 book4 registers */
> #if !defined(CONFIG_USER_ONLY)
> @@ -8407,7 +8407,7 @@ static void gen_spr_power7_book4(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power8_rpr(CPUPPCState *env)
> +static void register_power8_rpr_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> spr_register_hv(env, SPR_RPR, "RPR",
> @@ -8418,7 +8418,7 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
> #endif
> }
>
> -static void gen_spr_power9_mmu(CPUPPCState *env)
> +static void register_power9_mmu_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* Partition Table Control */
> @@ -8438,13 +8438,13 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
>
> static void init_proc_book3s_common(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_tbl(env);
> - gen_spr_usprg3(env);
> - gen_spr_book3s_altivec(env);
> - gen_spr_book3s_pmu_sup(env);
> - gen_spr_book3s_pmu_user(env);
> - gen_spr_book3s_ctrl(env);
> + register_ne_601_sprs(env);
> + register_tbl(env);
> + register_usprg3_sprs(env);
> + register_book3s_altivec_sprs(env);
> + register_book3s_pmu_sup_sprs(env);
> + register_book3s_pmu_user_sprs(env);
> + register_book3s_ctrl_sprs(env);
> /*
> * Can't find information on what this should be on reset. This
> * value is the one used by 74xx processors.
> @@ -8456,17 +8456,17 @@ static void init_proc_970(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_dbg_sprs(env);
>
> /* 970 Specific Registers */
> - gen_spr_970_hid(env);
> - gen_spr_970_hior(env);
> - gen_low_BATs(env);
> - gen_spr_970_pmu_sup(env);
> - gen_spr_970_pmu_user(env);
> - gen_spr_970_lpar(env);
> - gen_spr_970_dbg(env);
> + register_970_hid_sprs(env);
> + register_970_hior_sprs(env);
> + register_low_BATs(env);
> + register_970_pmu_sup_sprs(env);
> + register_970_pmu_user_sprs(env);
> + register_970_lpar_sprs(env);
> + register_970_dbg_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -8529,19 +8529,19 @@ static void init_proc_power5plus(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_dbg_sprs(env);
>
> /* POWER5+ Specific Registers */
> - gen_spr_970_hid(env);
> - gen_spr_970_hior(env);
> - gen_low_BATs(env);
> - gen_spr_970_pmu_sup(env);
> - gen_spr_970_pmu_user(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> + register_970_hid_sprs(env);
> + register_970_hior_sprs(env);
> + register_low_BATs(env);
> + register_970_pmu_sup_sprs(env);
> + register_970_pmu_user_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -8608,21 +8608,21 @@ static void init_proc_POWER7(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_dbg_sprs(env);
>
> /* POWER7 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_rmor(env);
> - gen_spr_amr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power7_book4(env);
> + register_book3s_ids_sprs(env);
> + register_rmor_sprs(env);
> + register_amr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power7_book4_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -8754,34 +8754,34 @@ static void init_proc_POWER8(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_sdr1(env);
> - gen_spr_book3s_207_dbg(env);
> + register_sdr1_sprs(env);
> + register_book3s_207_dbg_sprs(env);
>
> /* POWER8 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_rmor(env);
> - gen_spr_amr(env);
> - gen_spr_iamr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power8_tce_address_control(env);
> - gen_spr_power8_ids(env);
> - gen_spr_power8_ebb(env);
> - gen_spr_power8_fscr(env);
> - gen_spr_power8_pmu_sup(env);
> - gen_spr_power8_pmu_user(env);
> - gen_spr_power8_tm(env);
> - gen_spr_power8_pspb(env);
> - gen_spr_power8_dpdes(env);
> - gen_spr_vtb(env);
> - gen_spr_power8_ic(env);
> - gen_spr_power8_book4(env);
> - gen_spr_power8_rpr(env);
> + register_book3s_ids_sprs(env);
> + register_rmor_sprs(env);
> + register_amr_sprs(env);
> + register_iamr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power8_tce_address_control_sprs(env);
> + register_power8_ids_sprs(env);
> + register_power8_ebb_sprs(env);
> + register_power8_fscr_sprs(env);
> + register_power8_pmu_sup_sprs(env);
> + register_power8_pmu_user_sprs(env);
> + register_power8_tm_sprs(env);
> + register_power8_pspb_sprs(env);
> + register_power8_dpdes_sprs(env);
> + register_vtb_sprs(env);
> + register_power8_ic_sprs(env);
> + register_power8_book4_sprs(env);
> + register_power8_rpr_sprs(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -8951,33 +8951,33 @@ static void init_proc_POWER9(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_book3s_207_dbg(env);
> + register_book3s_207_dbg_sprs(env);
>
> /* POWER8 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_amr(env);
> - gen_spr_iamr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power5p_tb(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power8_tce_address_control(env);
> - gen_spr_power8_ids(env);
> - gen_spr_power8_ebb(env);
> - gen_spr_power8_fscr(env);
> - gen_spr_power8_pmu_sup(env);
> - gen_spr_power8_pmu_user(env);
> - gen_spr_power8_tm(env);
> - gen_spr_power8_pspb(env);
> - gen_spr_power8_dpdes(env);
> - gen_spr_vtb(env);
> - gen_spr_power8_ic(env);
> - gen_spr_power8_book4(env);
> - gen_spr_power8_rpr(env);
> - gen_spr_power9_mmu(env);
> + register_book3s_ids_sprs(env);
> + register_amr_sprs(env);
> + register_iamr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power5p_tb_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power8_tce_address_control_sprs(env);
> + register_power8_ids_sprs(env);
> + register_power8_ebb_sprs(env);
> + register_power8_fscr_sprs(env);
> + register_power8_pmu_sup_sprs(env);
> + register_power8_pmu_user_sprs(env);
> + register_power8_tm_sprs(env);
> + register_power8_pspb_sprs(env);
> + register_power8_dpdes_sprs(env);
> + register_vtb_sprs(env);
> + register_power8_ic_sprs(env);
> + register_power8_book4_sprs(env);
> + register_power8_rpr_sprs(env);
> + register_power9_mmu_sprs(env);
>
> /* POWER9 Specific registers */
> spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
> @@ -9169,31 +9169,31 @@ static void init_proc_POWER10(CPUPPCState *env)
> {
> /* Common Registers */
> init_proc_book3s_common(env);
> - gen_spr_book3s_207_dbg(env);
> + register_book3s_207_dbg_sprs(env);
>
> /* POWER8 Specific Registers */
> - gen_spr_book3s_ids(env);
> - gen_spr_amr(env);
> - gen_spr_iamr(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power5p_lpar(env);
> - gen_spr_power5p_ear(env);
> - gen_spr_power6_common(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_power8_tce_address_control(env);
> - gen_spr_power8_ids(env);
> - gen_spr_power8_ebb(env);
> - gen_spr_power8_fscr(env);
> - gen_spr_power8_pmu_sup(env);
> - gen_spr_power8_pmu_user(env);
> - gen_spr_power8_tm(env);
> - gen_spr_power8_pspb(env);
> - gen_spr_vtb(env);
> - gen_spr_power8_ic(env);
> - gen_spr_power8_book4(env);
> - gen_spr_power8_rpr(env);
> - gen_spr_power9_mmu(env);
> + register_book3s_ids_sprs(env);
> + register_amr_sprs(env);
> + register_iamr_sprs(env);
> + register_book3s_purr_sprs(env);
> + register_power5p_common_sprs(env);
> + register_power5p_lpar_sprs(env);
> + register_power5p_ear_sprs(env);
> + register_power6_common_sprs(env);
> + register_power6_dbg_sprs(env);
> + register_power8_tce_address_control_sprs(env);
> + register_power8_ids_sprs(env);
> + register_power8_ebb_sprs(env);
> + register_power8_fscr_sprs(env);
> + register_power8_pmu_sup_sprs(env);
> + register_power8_pmu_user_sprs(env);
> + register_power8_tm_sprs(env);
> + register_power8_pspb_sprs(env);
> + register_vtb_sprs(env);
> + register_power8_ic_sprs(env);
> + register_power8_book4_sprs(env);
> + register_power8_rpr_sprs(env);
> + register_power9_mmu_sprs(env);
>
> /* FIXME: Filter fields properly based on privilege level */
> spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
> @@ -9398,7 +9398,7 @@ static void init_ppc_proc(PowerPCCPU *cpu)
> env->tlb_type = TLB_NONE;
> #endif
> /* Register SPR common to all PowerPC implementations */
> - gen_spr_generic(env);
> + register_generic_sprs(env);
> spr_register(env, SPR_PVR, "PVR",
> /* Linux permits userspace to read PVR */
> #if defined(CONFIG_LINUX_USER)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c
2021-05-04 14:01 [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Bruno Larsen (billionai)
2021-05-04 14:01 ` [PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers Bruno Larsen (billionai)
2021-05-04 14:01 ` [PATCH v4 2/5] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
@ 2021-05-04 14:01 ` Bruno Larsen (billionai)
2021-05-04 16:08 ` Richard Henderson
2021-05-05 4:14 ` David Gibson
2021-05-04 14:01 ` [PATCH v4 4/5] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
` (2 subsequent siblings)
5 siblings, 2 replies; 14+ messages in thread
From: Bruno Larsen (billionai) @ 2021-05-04 14:01 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
Moved all read and write callbacks for SPRs away from
translate_init.c.inc and into translate.c; these functions are
TCG only, so this motion is required to enable building with
the flag disable-tcg
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/translate.c | 1037 ++++++++++++++++++++++++++++++-
target/ppc/translate_init.c.inc | 1011 ------------------------------
2 files changed, 1028 insertions(+), 1020 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2f10aa2fea..e48fdc6cdf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -370,6 +370,1034 @@ static inline void gen_sync_exception(DisasContext *ctx)
}
#endif
+/*****************************************************************************/
+/* SPR READ/RITE CALLBACKS */
+
+static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
+{
+#if 0
+ sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
+ printf("ERROR: try to access SPR %d !\n", sprn);
+#endif
+}
+#define SPR_NOACCESS (&spr_noaccess)
+
+/* #define PPC_DUMP_SPR_ACCESSES */
+
+/*
+ * Generic callbacks:
+ * do nothing but store/retrieve spr value
+ */
+static void spr_load_dump_spr(int sprn)
+{
+#ifdef PPC_DUMP_SPR_ACCESSES
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_load_dump_spr(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+#endif
+}
+
+static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], sprn);
+ spr_load_dump_spr(sprn);
+}
+
+static void spr_store_dump_spr(int sprn)
+{
+#ifdef PPC_DUMP_SPR_ACCESSES
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_store_dump_spr(cpu_env, t0);
+ tcg_temp_free_i32(t0);
+#endif
+}
+
+static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_store_spr(sprn, cpu_gpr[gprn]);
+ spr_store_dump_spr(sprn);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
+{
+#ifdef TARGET_PPC64
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ spr_store_dump_spr(sprn);
+#else
+ spr_write_generic(ctx, sprn, gprn);
+#endif
+}
+
+static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_load_spr(t0, sprn);
+ tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
+ tcg_gen_and_tl(t0, t0, t1);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
+{
+}
+
+#endif
+
+/* SPR common to all PowerPC */
+/* XER */
+static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv dst = cpu_gpr[gprn];
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ tcg_gen_mov_tl(dst, cpu_xer);
+ tcg_gen_shli_tl(t0, cpu_so, XER_SO);
+ tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
+ tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_or_tl(dst, dst, t2);
+ tcg_gen_or_tl(dst, dst, t0);
+ if (is_isa300(ctx)) {
+ tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
+ tcg_gen_or_tl(dst, dst, t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv src = cpu_gpr[gprn];
+ /* Write all flags, while reading back check for isa300 */
+ tcg_gen_andi_tl(cpu_xer, src,
+ ~((1u << XER_SO) |
+ (1u << XER_OV) | (1u << XER_OV32) |
+ (1u << XER_CA) | (1u << XER_CA32)));
+ tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
+ tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
+ tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
+ tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
+ tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
+}
+
+/* LR */
+static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
+}
+
+static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
+}
+
+/* CFAR */
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
+}
+
+static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
+}
+#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
+
+/* CTR */
+static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
+}
+
+static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
+{
+ tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
+}
+
+/* User read access to SPR */
+/* USPRx */
+/* UMMCRx */
+/* UPMCx */
+/* USIA */
+/* UDECR */
+static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
+}
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
+}
+#endif
+
+/* SPR common to all non-embedded PowerPC */
+/* DECR */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+#endif
+
+/* SPR common to all non-embedded PowerPC, except 601 */
+/* Time base */
+static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+ATTRIBUTE_UNUSED
+static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
+}
+
+ATTRIBUTE_UNUSED
+static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+ATTRIBUTE_UNUSED
+static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
+}
+
+ATTRIBUTE_UNUSED
+static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
+}
+
+#if defined(TARGET_PPC64)
+ATTRIBUTE_UNUSED
+static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+/* HDECR */
+static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+#endif
+#endif
+
+#if !defined(CONFIG_USER_ONLY)
+/* IBAT0U...IBAT0U */
+/* IBAT0L...IBAT7L */
+static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+}
+
+static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
+}
+
+static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
+ gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
+ gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
+ gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+/* DBAT0U...DBAT7U */
+/* DBAT0L...DBAT7L */
+static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
+}
+
+static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
+}
+
+static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
+ gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
+ gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
+ gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
+ gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+/* SDR1 */
+static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
+}
+
+#if defined(TARGET_PPC64)
+/* 64 bits PowerPC specific SPRs */
+/* PIDR */
+static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
+}
+
+static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ tcg_temp_free(t0);
+}
+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
+}
+
+/* DPDES */
+static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
+}
+#endif
+#endif
+
+/* PowerPC 601 specific registers */
+/* RTC */
+static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
+}
+
+static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
+ /* Must stop the translation as endianness may have changed */
+ gen_stop_exception(ctx);
+}
+#endif
+
+/* Unified bats */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState,
+ IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
+}
+
+static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+#endif
+
+/* PowerPC 40x specific registers */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_store_spr(sprn, cpu_gpr[gprn]);
+ gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
+ /* We must stop translation as we may have rebooted */
+ gen_stop_exception(ctx);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+
+static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_stop_exception(ctx);
+ }
+}
+#endif
+
+/* PowerPC 403 specific registers */
+/* PBL1 / PBU1 / PBL2 / PBU2 */
+#if !defined(CONFIG_USER_ONLY)
+static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
+ offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
+}
+
+static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
+ gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
+ gen_store_spr(SPR_PIR, t0);
+ tcg_temp_free(t0);
+}
+#endif
+
+/* SPE specific registers */
+static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
+ tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
+ tcg_temp_free_i32(t0);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+/* Callback used to write the exception vector base */
+static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
+{
+ int sprn_offs;
+
+ if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR0;
+ } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
+ } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
+ sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
+ } else {
+ printf("Trying to write an unknown exception vector %d %03x\n",
+ sprn, sprn);
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+ return;
+ }
+
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+#endif
+
+#ifdef TARGET_PPC64
+#ifndef CONFIG_USER_ONLY
+static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 PR=0 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ if (ctx->pr) {
+ gen_load_spr(t1, SPR_UAMOR);
+ } else {
+ gen_load_spr(t1, SPR_AMOR);
+ }
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_AMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_AMR, t0);
+ spr_store_dump_spr(SPR_AMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_UAMOR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_UAMOR, t0);
+ spr_store_dump_spr(SPR_UAMOR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ /*
+ * Note, the HV=1 case is handled earlier by simply using
+ * spr_write_generic for HV mode in the SPR table
+ */
+
+ /* Build insertion mask into t1 based on context */
+ gen_load_spr(t1, SPR_AMOR);
+
+ /* Mask new bits into t2 */
+ tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
+
+ /* Load AMR and clear new bits in t0 */
+ gen_load_spr(t0, SPR_IAMR);
+ tcg_gen_andc_tl(t0, t0, t1);
+
+ /* Or'in new bits and write it out */
+ tcg_gen_or_tl(t0, t0, t2);
+ gen_store_spr(SPR_IAMR, t0);
+ spr_store_dump_spr(SPR_IAMR);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+#endif
+#endif
+
+#ifndef CONFIG_USER_ONLY
+static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_fixup_thrm(cpu_env);
+ gen_load_spr(cpu_gpr[gprn], sprn);
+ spr_load_dump_spr(sprn);
+}
+#endif /* !CONFIG_USER_ONLY */
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn],
+ ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
+}
+static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
+}
+
+#endif
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv val = tcg_temp_new();
+ tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
+ gen_store_spr(SPR_BOOKE_MAS3, val);
+ tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
+ gen_store_spr(SPR_BOOKE_MAS7, val);
+ tcg_temp_free(val);
+}
+
+static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv mas7 = tcg_temp_new();
+ TCGv mas3 = tcg_temp_new();
+ gen_load_spr(mas7, SPR_BOOKE_MAS7);
+ tcg_gen_shli_tl(mas7, mas7, 32);
+ gen_load_spr(mas3, SPR_BOOKE_MAS3);
+ tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
+ tcg_temp_free(mas3);
+ tcg_temp_free(mas7);
+}
+
+#endif
+
+#ifdef TARGET_PPC64
+static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
+ int bit, int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
+static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
+ int bit, int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
+static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv spr_up = tcg_temp_new();
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_shri_tl(spr_up, spr, 32);
+ tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
+
+ tcg_temp_free(spr);
+ tcg_temp_free(spr_up);
+}
+
+static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
+ gen_store_spr(sprn - 1, spr);
+
+ tcg_temp_free(spr);
+}
+
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv hmer = tcg_temp_new();
+
+ gen_load_spr(hmer, sprn);
+ tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
+ gen_store_spr(sprn, hmer);
+ spr_store_dump_spr(sprn);
+ tcg_temp_free(hmer);
+}
+
+static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
+}
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_prev_upper32(ctx, gprn, sprn);
+}
+
+static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_prev_upper32(ctx, sprn, gprn);
+}
+
+static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_generic(ctx, gprn, sprn);
+}
+
+static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_generic(ctx, sprn, gprn);
+}
+
+static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_prev_upper32(ctx, gprn, sprn);
+}
+
+static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_prev_upper32(ctx, sprn, gprn);
+}
+#endif
+
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
@@ -4262,15 +5290,6 @@ static void gen_mfmsr(DisasContext *ctx)
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
}
-static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
-{
-#if 0
- sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
- printf("ERROR: try to access SPR %d !\n", sprn);
-#endif
-}
-#define SPR_NOACCESS (&spr_noaccess)
-
/* mfspr */
static inline void gen_op_mfspr(DisasContext *ctx)
{
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 4fac8a9950..c913058170 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -43,705 +43,8 @@
#include "qapi/qapi-commands-machine-target.h"
/* #define PPC_DEBUG_SPR */
-/* #define PPC_DUMP_SPR_ACCESSES */
/* #define USE_APPLE_GDB */
-/*
- * Generic callbacks:
- * do nothing but store/retrieve spr value
- */
-static void spr_load_dump_spr(int sprn)
-{
-#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_load_dump_spr(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif
-}
-
-static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
-{
- gen_load_spr(cpu_gpr[gprn], sprn);
- spr_load_dump_spr(sprn);
-}
-
-static void spr_store_dump_spr(int sprn)
-{
-#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_store_dump_spr(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif
-}
-
-static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(sprn, cpu_gpr[gprn]);
- spr_store_dump_spr(sprn);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
-{
-#ifdef TARGET_PPC64
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
- spr_store_dump_spr(sprn);
-#else
- spr_write_generic(ctx, sprn, gprn);
-#endif
-}
-
-static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- gen_load_spr(t0, sprn);
- tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
- tcg_gen_and_tl(t0, t0, t1);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
-static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
-{
-}
-
-#endif
-
-/* SPR common to all PowerPC */
-/* XER */
-static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv dst = cpu_gpr[gprn];
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_mov_tl(dst, cpu_xer);
- tcg_gen_shli_tl(t0, cpu_so, XER_SO);
- tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
- tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_or_tl(dst, dst, t2);
- tcg_gen_or_tl(dst, dst, t0);
- if (is_isa300(ctx)) {
- tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
- tcg_gen_or_tl(dst, dst, t0);
- tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
- tcg_gen_or_tl(dst, dst, t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv src = cpu_gpr[gprn];
- /* Write all flags, while reading back check for isa300 */
- tcg_gen_andi_tl(cpu_xer, src,
- ~((1u << XER_SO) |
- (1u << XER_OV) | (1u << XER_OV32) |
- (1u << XER_CA) | (1u << XER_CA32)));
- tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
- tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
- tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
- tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
- tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
-}
-
-/* LR */
-static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
-}
-
-static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
-}
-
-/* CFAR */
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
-}
-
-static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
-}
-#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
-
-/* CTR */
-static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
-}
-
-static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
-{
- tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
-}
-
-/* User read access to SPR */
-/* USPRx */
-/* UMMCRx */
-/* UPMCx */
-/* USIA */
-/* UDECR */
-static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
-{
- gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
-}
-
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
-{
- gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
-}
-#endif
-
-/* SPR common to all non-embedded PowerPC */
-/* DECR */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-#endif
-
-/* SPR common to all non-embedded PowerPC, except 601 */
-/* Time base */
-static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-ATTRIBUTE_UNUSED
-static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
-}
-
-ATTRIBUTE_UNUSED
-static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-ATTRIBUTE_UNUSED
-static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
-}
-
-ATTRIBUTE_UNUSED
-static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
-}
-
-#if defined(TARGET_PPC64)
-ATTRIBUTE_UNUSED
-static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-/* HDECR */
-static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-#endif
-#endif
-
-#if !defined(CONFIG_USER_ONLY)
-/* IBAT0U...IBAT0U */
-/* IBAT0L...IBAT7L */
-static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
-}
-
-static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
-}
-
-static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
- gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
- gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-/* DBAT0U...DBAT7U */
-/* DBAT0L...DBAT7L */
-static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
-}
-
-static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
-}
-
-static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
- gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
- gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-/* SDR1 */
-static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
-}
-
-#if defined(TARGET_PPC64)
-/* 64 bits PowerPC specific SPRs */
-/* PIDR */
-static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
-}
-
-static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
- tcg_temp_free(t0);
-}
-static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
-}
-
-/* DPDES */
-static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
-}
-#endif
-#endif
-
-/* PowerPC 601 specific registers */
-/* RTC */
-static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
-}
-
-static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
- /* Must stop the translation as endianness may have changed */
- gen_stop_exception(ctx);
-}
-#endif
-
-/* Unified bats */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState,
- IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
-}
-
-static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
- gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-#endif
-
-/* PowerPC 40x specific registers */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_store_spr(sprn, cpu_gpr[gprn]);
- gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
- /* We must stop translation as we may have rebooted */
- gen_stop_exception(ctx);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-
-static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
-{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
-}
-#endif
-
-/* PowerPC 403 specific registers */
-/* PBL1 / PBU1 / PBL2 / PBU2 */
-#if !defined(CONFIG_USER_ONLY)
-static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
-}
-
-static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
- gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
- gen_store_spr(SPR_PIR, t0);
- tcg_temp_free(t0);
-}
-#endif
-
-/* SPE specific registers */
-static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
- tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
- tcg_temp_free_i32(t0);
-}
-
-static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
- tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
- tcg_temp_free_i32(t0);
-}
-
-#if !defined(CONFIG_USER_ONLY)
-/* Callback used to write the exception vector base */
-static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
-{
- int sprn_offs;
-
- if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
- sprn_offs = sprn - SPR_BOOKE_IVOR0;
- } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
- sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
- } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
- sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
- } else {
- printf("Trying to write an unknown exception vector %d %03x\n",
- sprn, sprn);
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
- return;
- }
-
- TCGv t0 = tcg_temp_new();
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
- tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-#endif
-
static inline void vscr_init(CPUPPCState *env, uint32_t val)
{
/* Altivec always uses round-to-nearest */
@@ -1254,105 +557,6 @@ static void register_7xx_sprs(CPUPPCState *env)
}
#ifdef TARGET_PPC64
-#ifndef CONFIG_USER_ONLY
-static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 PR=0 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- if (ctx->pr) {
- gen_load_spr(t1, SPR_UAMOR);
- } else {
- gen_load_spr(t1, SPR_AMOR);
- }
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_AMR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_AMR, t0);
- spr_store_dump_spr(SPR_AMR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- gen_load_spr(t1, SPR_AMOR);
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_UAMOR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_UAMOR, t0);
- spr_store_dump_spr(SPR_UAMOR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
-
- /*
- * Note, the HV=1 case is handled earlier by simply using
- * spr_write_generic for HV mode in the SPR table
- */
-
- /* Build insertion mask into t1 based on context */
- gen_load_spr(t1, SPR_AMOR);
-
- /* Mask new bits into t2 */
- tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
-
- /* Load AMR and clear new bits in t0 */
- gen_load_spr(t0, SPR_IAMR);
- tcg_gen_andc_tl(t0, t0, t1);
-
- /* Or'in new bits and write it out */
- tcg_gen_or_tl(t0, t0, t2);
- gen_store_spr(SPR_IAMR, t0);
- spr_store_dump_spr(SPR_IAMR);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-#endif /* CONFIG_USER_ONLY */
-
static void register_amr_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
@@ -1397,15 +601,6 @@ static void register_iamr_sprs(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-#ifndef CONFIG_USER_ONLY
-static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
-{
- gen_helper_fixup_thrm(cpu_env);
- gen_load_spr(cpu_gpr[gprn], sprn);
- spr_load_dump_spr(sprn);
-}
-#endif /* !CONFIG_USER_ONLY */
-
static void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
@@ -1771,57 +966,6 @@ static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
#endif
}
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv t0 = tcg_temp_new();
-
- tcg_gen_andi_tl(t0, cpu_gpr[gprn],
- ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
- gen_store_spr(sprn, t0);
- tcg_temp_free(t0);
-}
-
-static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
-}
-
-static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(sprn);
- gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
-}
-static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
-}
-
-#endif
-
static void register_usprg3_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG3, "USPRG3",
@@ -4902,31 +4046,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv val = tcg_temp_new();
- tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
- gen_store_spr(SPR_BOOKE_MAS3, val);
- tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
- gen_store_spr(SPR_BOOKE_MAS7, val);
- tcg_temp_free(val);
-}
-
-static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv mas7 = tcg_temp_new();
- TCGv mas3 = tcg_temp_new();
- gen_load_spr(mas7, SPR_BOOKE_MAS7);
- tcg_gen_shli_tl(mas7, mas7, 32);
- gen_load_spr(mas3, SPR_BOOKE_MAS3);
- tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
- tcg_temp_free(mas3);
- tcg_temp_free(mas7);
-}
-
-#endif
-
enum fsl_e500_version {
fsl_e500v1,
fsl_e500v2,
@@ -7638,58 +6757,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
#define POWERPC970_HID5_INIT 0x00000000
#endif
-static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
- int bit, int sprn, int cause)
-{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
-
- gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
-
- tcg_temp_free_i32(t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t1);
-}
-
-static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
- int bit, int sprn, int cause)
-{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
-
- gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
-
- tcg_temp_free_i32(t3);
- tcg_temp_free_i32(t2);
- tcg_temp_free_i32(t1);
-}
-
-static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- TCGv spr_up = tcg_temp_new();
- TCGv spr = tcg_temp_new();
-
- gen_load_spr(spr, sprn - 1);
- tcg_gen_shri_tl(spr_up, spr, 32);
- tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
-
- tcg_temp_free(spr);
- tcg_temp_free(spr_up);
-}
-
-static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv spr = tcg_temp_new();
-
- gen_load_spr(spr, sprn - 1);
- tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
- gen_store_spr(sprn - 1, spr);
-
- tcg_temp_free(spr);
-}
-
static int check_pow_970(CPUPPCState *env)
{
if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
@@ -7984,24 +7051,6 @@ static void register_power5p_tb_sprs(CPUPPCState *env)
0x00000000);
}
-#if !defined(CONFIG_USER_ONLY)
-static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv hmer = tcg_temp_new();
-
- gen_load_spr(hmer, sprn);
- tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
- gen_store_spr(sprn, hmer);
- spr_store_dump_spr(sprn);
- tcg_temp_free(hmer);
-}
-
-static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
-{
- gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
-}
-#endif /* !defined(CONFIG_USER_ONLY) */
-
static void register_970_lpar_sprs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -8199,18 +7248,6 @@ static void register_power6_common_sprs(CPUPPCState *env)
0x00000000);
}
-static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
- spr_write_generic(ctx, sprn, gprn);
-}
-
static void register_power8_tce_address_control_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TAR, "TAR",
@@ -8219,30 +7256,6 @@ static void register_power8_tce_address_control_sprs(CPUPPCState *env)
KVM_REG_PPC_TAR, 0x00000000);
}
-static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_write_generic(ctx, sprn, gprn);
-}
-
-static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_read_prev_upper32(ctx, gprn, sprn);
-}
-
-static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
- spr_write_prev_upper32(ctx, sprn, gprn);
-}
-
static void register_power8_tm_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_TFHAR, "TFHAR",
@@ -8263,30 +7276,6 @@ static void register_power8_tm_sprs(CPUPPCState *env)
0x00000000);
}
-static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_read_generic(ctx, gprn, sprn);
-}
-
-static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_write_generic(ctx, sprn, gprn);
-}
-
-static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_read_prev_upper32(ctx, gprn, sprn);
-}
-
-static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
-{
- gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
- spr_write_prev_upper32(ctx, sprn, gprn);
-}
-
static void register_power8_ebb_sprs(CPUPPCState *env)
{
spr_register(env, SPR_BESCRS, "BESCRS",
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c
2021-05-04 14:01 ` [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c Bruno Larsen (billionai)
@ 2021-05-04 16:08 ` Richard Henderson
2021-05-05 4:14 ` David Gibson
1 sibling, 0 replies; 14+ messages in thread
From: Richard Henderson @ 2021-05-04 16:08 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 5/4/21 7:01 AM, Bruno Larsen (billionai) wrote:
> Moved all read and write callbacks for SPRs away from
> translate_init.c.inc and into translate.c; these functions are
> TCG only, so this motion is required to enable building with
> the flag disable-tcg
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +/*****************************************************************************/
> +/* SPR READ/RITE CALLBACKS */
WRITE.
r~
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c
2021-05-04 14:01 ` [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c Bruno Larsen (billionai)
2021-05-04 16:08 ` Richard Henderson
@ 2021-05-05 4:14 ` David Gibson
1 sibling, 0 replies; 14+ messages in thread
From: David Gibson @ 2021-05-05 4:14 UTC (permalink / raw)
To: Bruno Larsen (billionai)
Cc: farosas, richard.henderson, qemu-devel, lucas.araujo,
fernando.valle, qemu-ppc, matheus.ferst, luis.pires
[-- Attachment #1: Type: text/plain, Size: 67840 bytes --]
On Tue, May 04, 2021 at 11:01:55AM -0300, Bruno Larsen (billionai) wrote:
> Moved all read and write callbacks for SPRs away from
> translate_init.c.inc and into translate.c; these functions are
> TCG only, so this motion is required to enable building with
> the flag disable-tcg
>
> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> ---
> target/ppc/translate.c | 1037 ++++++++++++++++++++++++++++++-
> target/ppc/translate_init.c.inc | 1011 ------------------------------
> 2 files changed, 1028 insertions(+), 1020 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 2f10aa2fea..e48fdc6cdf 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -370,6 +370,1034 @@ static inline void gen_sync_exception(DisasContext *ctx)
> }
> #endif
>
> +/*****************************************************************************/
> +/* SPR READ/RITE CALLBACKS */
s/RITE/WRITE/
Otherwise, LGTM.
> +
> +static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
> +{
> +#if 0
> + sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
> + printf("ERROR: try to access SPR %d !\n", sprn);
> +#endif
> +}
> +#define SPR_NOACCESS (&spr_noaccess)
> +
> +/* #define PPC_DUMP_SPR_ACCESSES */
> +
> +/*
> + * Generic callbacks:
> + * do nothing but store/retrieve spr value
> + */
> +static void spr_load_dump_spr(int sprn)
> +{
> +#ifdef PPC_DUMP_SPR_ACCESSES
> + TCGv_i32 t0 = tcg_const_i32(sprn);
> + gen_helper_load_dump_spr(cpu_env, t0);
> + tcg_temp_free_i32(t0);
> +#endif
> +}
> +
> +static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_load_spr(cpu_gpr[gprn], sprn);
> + spr_load_dump_spr(sprn);
> +}
> +
> +static void spr_store_dump_spr(int sprn)
> +{
> +#ifdef PPC_DUMP_SPR_ACCESSES
> + TCGv_i32 t0 = tcg_const_i32(sprn);
> + gen_helper_store_dump_spr(cpu_env, t0);
> + tcg_temp_free_i32(t0);
> +#endif
> +}
> +
> +static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_store_spr(sprn, cpu_gpr[gprn]);
> + spr_store_dump_spr(sprn);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
> +{
> +#ifdef TARGET_PPC64
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> + spr_store_dump_spr(sprn);
> +#else
> + spr_write_generic(ctx, sprn, gprn);
> +#endif
> +}
> +
> +static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + gen_load_spr(t0, sprn);
> + tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
> + tcg_gen_and_tl(t0, t0, t1);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> +}
> +
> +static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
> +{
> +}
> +
> +#endif
> +
> +/* SPR common to all PowerPC */
> +/* XER */
> +static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv dst = cpu_gpr[gprn];
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> + tcg_gen_mov_tl(dst, cpu_xer);
> + tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> + tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> + tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> + tcg_gen_or_tl(t0, t0, t1);
> + tcg_gen_or_tl(dst, dst, t2);
> + tcg_gen_or_tl(dst, dst, t0);
> + if (is_isa300(ctx)) {
> + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> + tcg_gen_or_tl(dst, dst, t0);
> + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> + tcg_gen_or_tl(dst, dst, t0);
> + }
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +
> +static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv src = cpu_gpr[gprn];
> + /* Write all flags, while reading back check for isa300 */
> + tcg_gen_andi_tl(cpu_xer, src,
> + ~((1u << XER_SO) |
> + (1u << XER_OV) | (1u << XER_OV32) |
> + (1u << XER_CA) | (1u << XER_CA32)));
> + tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> + tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> + tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> + tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> + tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> +}
> +
> +/* LR */
> +static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
> +}
> +
> +static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
> +{
> + tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
> +}
> +
> +/* CFAR */
> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> +static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> +}
> +
> +static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
> +{
> + tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> +}
> +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
> +
> +/* CTR */
> +static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
> +}
> +
> +static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
> +{
> + tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
> +}
> +
> +/* User read access to SPR */
> +/* USPRx */
> +/* UMMCRx */
> +/* UPMCx */
> +/* USIA */
> +/* UDECR */
> +static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
> +}
> +
> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> +static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
> +}
> +#endif
> +
> +/* SPR common to all non-embedded PowerPC */
> +/* DECR */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +#endif
> +
> +/* SPR common to all non-embedded PowerPC, except 601 */
> +/* Time base */
> +static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +ATTRIBUTE_UNUSED
> +static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +#if defined(TARGET_PPC64)
> +ATTRIBUTE_UNUSED
> +static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +/* HDECR */
> +static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_end();
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +#endif
> +#endif
> +
> +#if !defined(CONFIG_USER_ONLY)
> +/* IBAT0U...IBAT0U */
> +/* IBAT0L...IBAT7L */
> +static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> +}
> +
> +static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
> +}
> +
> +static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
> + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
> + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
> + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +/* DBAT0U...DBAT7U */
> +/* DBAT0L...DBAT7L */
> +static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
> +}
> +
> +static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
> +}
> +
> +static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
> + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
> + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
> + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
> + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +/* SDR1 */
> +static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +#if defined(TARGET_PPC64)
> +/* 64 bits PowerPC specific SPRs */
> +/* PIDR */
> +static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
> +}
> +
> +static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
> + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> + tcg_temp_free(t0);
> +}
> +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +/* DPDES */
> +static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
> +}
> +
> +static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
> +}
> +#endif
> +#endif
> +
> +/* PowerPC 601 specific registers */
> +/* RTC */
> +static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
> +}
> +
> +static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
> + /* Must stop the translation as endianness may have changed */
> + gen_stop_exception(ctx);
> +}
> +#endif
> +
> +/* Unified bats */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState,
> + IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> +}
> +
> +static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> + gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> + gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +#endif
> +
> +/* PowerPC 40x specific registers */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_store_spr(sprn, cpu_gpr[gprn]);
> + gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> + /* We must stop translation as we may have rebooted */
> + gen_stop_exception(ctx);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +
> +static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> + gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_stop_exception(ctx);
> + }
> +}
> +#endif
> +
> +/* PowerPC 403 specific registers */
> +/* PBL1 / PBU1 / PBL2 / PBU2 */
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
> +{
> + tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> + offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
> +}
> +
> +static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
> + gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
> + gen_store_spr(SPR_PIR, t0);
> + tcg_temp_free(t0);
> +}
> +#endif
> +
> +/* SPE specific registers */
> +static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> + tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
> + tcg_temp_free_i32(t0);
> +}
> +
> +static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
> + tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> + tcg_temp_free_i32(t0);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +/* Callback used to write the exception vector base */
> +static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
> + tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
> +{
> + int sprn_offs;
> +
> + if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
> + sprn_offs = sprn - SPR_BOOKE_IVOR0;
> + } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
> + sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
> + } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
> + sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
> + } else {
> + printf("Trying to write an unknown exception vector %d %03x\n",
> + sprn, sprn);
> + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
> + return;
> + }
> +
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
> + tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +#endif
> +
> +#ifdef TARGET_PPC64
> +#ifndef CONFIG_USER_ONLY
> +static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /*
> + * Note, the HV=1 PR=0 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + if (ctx->pr) {
> + gen_load_spr(t1, SPR_UAMOR);
> + } else {
> + gen_load_spr(t1, SPR_AMOR);
> + }
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_AMR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_AMR, t0);
> + spr_store_dump_spr(SPR_AMR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +
> +static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /*
> + * Note, the HV=1 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + gen_load_spr(t1, SPR_AMOR);
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_UAMOR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_UAMOR, t0);
> + spr_store_dump_spr(SPR_UAMOR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +
> +static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + /*
> + * Note, the HV=1 case is handled earlier by simply using
> + * spr_write_generic for HV mode in the SPR table
> + */
> +
> + /* Build insertion mask into t1 based on context */
> + gen_load_spr(t1, SPR_AMOR);
> +
> + /* Mask new bits into t2 */
> + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> +
> + /* Load AMR and clear new bits in t0 */
> + gen_load_spr(t0, SPR_IAMR);
> + tcg_gen_andc_tl(t0, t0, t1);
> +
> + /* Or'in new bits and write it out */
> + tcg_gen_or_tl(t0, t0, t2);
> + gen_store_spr(SPR_IAMR, t0);
> + spr_store_dump_spr(SPR_IAMR);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
> +#endif
> +#endif
> +
> +#ifndef CONFIG_USER_ONLY
> +static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_helper_fixup_thrm(cpu_env);
> + gen_load_spr(cpu_gpr[gprn], sprn);
> + spr_load_dump_spr(sprn);
> +}
> +#endif /* !CONFIG_USER_ONLY */
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> +
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> +
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv t0 = tcg_temp_new();
> +
> + tcg_gen_andi_tl(t0, cpu_gpr[gprn],
> + ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> +}
> +
> +static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv_i32 t0 = tcg_const_i32(sprn);
> + gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
> + tcg_temp_free_i32(t0);
> +}
> +static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
> +}
> +static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
> +}
> +
> +#endif
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv val = tcg_temp_new();
> + tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
> + gen_store_spr(SPR_BOOKE_MAS3, val);
> + tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
> + gen_store_spr(SPR_BOOKE_MAS7, val);
> + tcg_temp_free(val);
> +}
> +
> +static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv mas7 = tcg_temp_new();
> + TCGv mas3 = tcg_temp_new();
> + gen_load_spr(mas7, SPR_BOOKE_MAS7);
> + tcg_gen_shli_tl(mas7, mas7, 32);
> + gen_load_spr(mas3, SPR_BOOKE_MAS3);
> + tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
> + tcg_temp_free(mas3);
> + tcg_temp_free(mas7);
> +}
> +
> +#endif
> +
> +#ifdef TARGET_PPC64
> +static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> + int bit, int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> +static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
> + int bit, int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> +static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
> +{
> + TCGv spr_up = tcg_temp_new();
> + TCGv spr = tcg_temp_new();
> +
> + gen_load_spr(spr, sprn - 1);
> + tcg_gen_shri_tl(spr_up, spr, 32);
> + tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
> +
> + tcg_temp_free(spr);
> + tcg_temp_free(spr_up);
> +}
> +
> +static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv spr = tcg_temp_new();
> +
> + gen_load_spr(spr, sprn - 1);
> + tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
> + gen_store_spr(sprn - 1, spr);
> +
> + tcg_temp_free(spr);
> +}
> +
> +#if !defined(CONFIG_USER_ONLY)
> +static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
> +{
> + TCGv hmer = tcg_temp_new();
> +
> + gen_load_spr(hmer, sprn);
> + tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
> + gen_store_spr(sprn, hmer);
> + spr_store_dump_spr(sprn);
> + tcg_temp_free(hmer);
> +}
> +
> +static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
> +}
> +#endif /* !defined(CONFIG_USER_ONLY) */
> +
> +static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_read_generic(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_write_generic(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_read_generic(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_write_generic(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_read_prev_upper32(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_write_prev_upper32(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_read_generic(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_write_generic(ctx, sprn, gprn);
> +}
> +
> +static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_read_prev_upper32(ctx, gprn, sprn);
> +}
> +
> +static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_write_prev_upper32(ctx, sprn, gprn);
> +}
> +#endif
> +
> #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
> GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
>
> @@ -4262,15 +5290,6 @@ static void gen_mfmsr(DisasContext *ctx)
> tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
> }
>
> -static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
> -{
> -#if 0
> - sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
> - printf("ERROR: try to access SPR %d !\n", sprn);
> -#endif
> -}
> -#define SPR_NOACCESS (&spr_noaccess)
> -
> /* mfspr */
> static inline void gen_op_mfspr(DisasContext *ctx)
> {
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index 4fac8a9950..c913058170 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -43,705 +43,8 @@
> #include "qapi/qapi-commands-machine-target.h"
>
> /* #define PPC_DEBUG_SPR */
> -/* #define PPC_DUMP_SPR_ACCESSES */
> /* #define USE_APPLE_GDB */
>
> -/*
> - * Generic callbacks:
> - * do nothing but store/retrieve spr value
> - */
> -static void spr_load_dump_spr(int sprn)
> -{
> -#ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> - gen_helper_load_dump_spr(cpu_env, t0);
> - tcg_temp_free_i32(t0);
> -#endif
> -}
> -
> -static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_load_spr(cpu_gpr[gprn], sprn);
> - spr_load_dump_spr(sprn);
> -}
> -
> -static void spr_store_dump_spr(int sprn)
> -{
> -#ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> - gen_helper_store_dump_spr(cpu_env, t0);
> - tcg_temp_free_i32(t0);
> -#endif
> -}
> -
> -static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_store_spr(sprn, cpu_gpr[gprn]);
> - spr_store_dump_spr(sprn);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
> -{
> -#ifdef TARGET_PPC64
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> - spr_store_dump_spr(sprn);
> -#else
> - spr_write_generic(ctx, sprn, gprn);
> -#endif
> -}
> -
> -static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - gen_load_spr(t0, sprn);
> - tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
> - tcg_gen_and_tl(t0, t0, t1);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> -}
> -
> -static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
> -{
> -}
> -
> -#endif
> -
> -/* SPR common to all PowerPC */
> -/* XER */
> -static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
> -{
> - TCGv dst = cpu_gpr[gprn];
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> - tcg_gen_mov_tl(dst, cpu_xer);
> - tcg_gen_shli_tl(t0, cpu_so, XER_SO);
> - tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
> - tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
> - tcg_gen_or_tl(t0, t0, t1);
> - tcg_gen_or_tl(dst, dst, t2);
> - tcg_gen_or_tl(dst, dst, t0);
> - if (is_isa300(ctx)) {
> - tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> - tcg_gen_or_tl(dst, dst, t0);
> - tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> - tcg_gen_or_tl(dst, dst, t0);
> - }
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv src = cpu_gpr[gprn];
> - /* Write all flags, while reading back check for isa300 */
> - tcg_gen_andi_tl(cpu_xer, src,
> - ~((1u << XER_SO) |
> - (1u << XER_OV) | (1u << XER_OV32) |
> - (1u << XER_CA) | (1u << XER_CA32)));
> - tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
> - tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
> - tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
> - tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
> - tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
> -}
> -
> -/* LR */
> -static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
> -}
> -
> -static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
> -{
> - tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
> -}
> -
> -/* CFAR */
> -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> -static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
> -}
> -
> -static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
> -{
> - tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
> -}
> -#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
> -
> -/* CTR */
> -static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
> -}
> -
> -static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
> -{
> - tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
> -}
> -
> -/* User read access to SPR */
> -/* USPRx */
> -/* UMMCRx */
> -/* UPMCx */
> -/* USIA */
> -/* UDECR */
> -static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
> -}
> -
> -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> -static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
> -}
> -#endif
> -
> -/* SPR common to all non-embedded PowerPC */
> -/* DECR */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -#endif
> -
> -/* SPR common to all non-embedded PowerPC, except 601 */
> -/* Time base */
> -static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -ATTRIBUTE_UNUSED
> -static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -#if defined(TARGET_PPC64)
> -ATTRIBUTE_UNUSED
> -static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -/* HDECR */
> -static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -#endif
> -#endif
> -
> -#if !defined(CONFIG_USER_ONLY)
> -/* IBAT0U...IBAT0U */
> -/* IBAT0L...IBAT7L */
> -static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> -}
> -
> -static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
> -}
> -
> -static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
> - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
> - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
> - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -/* DBAT0U...DBAT7U */
> -/* DBAT0L...DBAT7L */
> -static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
> -}
> -
> -static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
> -}
> -
> -static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
> - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
> - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
> - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
> - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -/* SDR1 */
> -static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -#if defined(TARGET_PPC64)
> -/* 64 bits PowerPC specific SPRs */
> -/* PIDR */
> -static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
> -}
> -
> -static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
> - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> - tcg_temp_free(t0);
> -}
> -static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -/* DPDES */
> -static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
> -}
> -
> -static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
> -}
> -#endif
> -#endif
> -
> -/* PowerPC 601 specific registers */
> -/* RTC */
> -static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
> -}
> -
> -static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
> - /* Must stop the translation as endianness may have changed */
> - gen_stop_exception(ctx);
> -}
> -#endif
> -
> -/* Unified bats */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState,
> - IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
> -}
> -
> -static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> - gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> - gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -#endif
> -
> -/* PowerPC 40x specific registers */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_store_spr(sprn, cpu_gpr[gprn]);
> - gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> - /* We must stop translation as we may have rebooted */
> - gen_stop_exception(ctx);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -
> -static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> -{
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> - gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> -}
> -#endif
> -
> -/* PowerPC 403 specific registers */
> -/* PBL1 / PBU1 / PBL2 / PBU2 */
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
> -{
> - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
> - offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
> -}
> -
> -static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
> - gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
> - gen_store_spr(SPR_PIR, t0);
> - tcg_temp_free(t0);
> -}
> -#endif
> -
> -/* SPE specific registers */
> -static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
> -{
> - TCGv_i32 t0 = tcg_temp_new_i32();
> - tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> - tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
> - tcg_temp_free_i32(t0);
> -}
> -
> -static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_temp_new_i32();
> - tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
> - tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
> - tcg_temp_free_i32(t0);
> -}
> -
> -#if !defined(CONFIG_USER_ONLY)
> -/* Callback used to write the exception vector base */
> -static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
> - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
> -{
> - int sprn_offs;
> -
> - if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
> - sprn_offs = sprn - SPR_BOOKE_IVOR0;
> - } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
> - sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
> - } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
> - sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
> - } else {
> - printf("Trying to write an unknown exception vector %d %03x\n",
> - sprn, sprn);
> - gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
> - return;
> - }
> -
> - TCGv t0 = tcg_temp_new();
> - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
> - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
> - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -#endif
> -
> static inline void vscr_init(CPUPPCState *env, uint32_t val)
> {
> /* Altivec always uses round-to-nearest */
> @@ -1254,105 +557,6 @@ static void register_7xx_sprs(CPUPPCState *env)
> }
>
> #ifdef TARGET_PPC64
> -#ifndef CONFIG_USER_ONLY
> -static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> -
> - /*
> - * Note, the HV=1 PR=0 case is handled earlier by simply using
> - * spr_write_generic for HV mode in the SPR table
> - */
> -
> - /* Build insertion mask into t1 based on context */
> - if (ctx->pr) {
> - gen_load_spr(t1, SPR_UAMOR);
> - } else {
> - gen_load_spr(t1, SPR_AMOR);
> - }
> -
> - /* Mask new bits into t2 */
> - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> -
> - /* Load AMR and clear new bits in t0 */
> - gen_load_spr(t0, SPR_AMR);
> - tcg_gen_andc_tl(t0, t0, t1);
> -
> - /* Or'in new bits and write it out */
> - tcg_gen_or_tl(t0, t0, t2);
> - gen_store_spr(SPR_AMR, t0);
> - spr_store_dump_spr(SPR_AMR);
> -
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> -
> - /*
> - * Note, the HV=1 case is handled earlier by simply using
> - * spr_write_generic for HV mode in the SPR table
> - */
> -
> - /* Build insertion mask into t1 based on context */
> - gen_load_spr(t1, SPR_AMOR);
> -
> - /* Mask new bits into t2 */
> - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> -
> - /* Load AMR and clear new bits in t0 */
> - gen_load_spr(t0, SPR_UAMOR);
> - tcg_gen_andc_tl(t0, t0, t1);
> -
> - /* Or'in new bits and write it out */
> - tcg_gen_or_tl(t0, t0, t2);
> - gen_store_spr(SPR_UAMOR, t0);
> - spr_store_dump_spr(SPR_UAMOR);
> -
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -
> -static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - TCGv t2 = tcg_temp_new();
> -
> - /*
> - * Note, the HV=1 case is handled earlier by simply using
> - * spr_write_generic for HV mode in the SPR table
> - */
> -
> - /* Build insertion mask into t1 based on context */
> - gen_load_spr(t1, SPR_AMOR);
> -
> - /* Mask new bits into t2 */
> - tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
> -
> - /* Load AMR and clear new bits in t0 */
> - gen_load_spr(t0, SPR_IAMR);
> - tcg_gen_andc_tl(t0, t0, t1);
> -
> - /* Or'in new bits and write it out */
> - tcg_gen_or_tl(t0, t0, t2);
> - gen_store_spr(SPR_IAMR, t0);
> - spr_store_dump_spr(SPR_IAMR);
> -
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - tcg_temp_free(t2);
> -}
> -#endif /* CONFIG_USER_ONLY */
> -
> static void register_amr_sprs(CPUPPCState *env)
> {
> #ifndef CONFIG_USER_ONLY
> @@ -1397,15 +601,6 @@ static void register_iamr_sprs(CPUPPCState *env)
> }
> #endif /* TARGET_PPC64 */
>
> -#ifndef CONFIG_USER_ONLY
> -static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_helper_fixup_thrm(cpu_env);
> - gen_load_spr(cpu_gpr[gprn], sprn);
> - spr_load_dump_spr(sprn);
> -}
> -#endif /* !CONFIG_USER_ONLY */
> -
> static void register_thrm_sprs(CPUPPCState *env)
> {
> /* Thermal management */
> @@ -1771,57 +966,6 @@ static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
> #endif
> }
>
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> -
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> -
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv t0 = tcg_temp_new();
> -
> - tcg_gen_andi_tl(t0, cpu_gpr[gprn],
> - ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
> - gen_store_spr(sprn, t0);
> - tcg_temp_free(t0);
> -}
> -
> -static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> - gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
> - tcg_temp_free_i32(t0);
> -}
> -static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
> -}
> -static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
> -}
> -
> -#endif
> -
> static void register_usprg3_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_USPRG3, "USPRG3",
> @@ -4902,31 +4046,6 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
> POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
> }
>
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv val = tcg_temp_new();
> - tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
> - gen_store_spr(SPR_BOOKE_MAS3, val);
> - tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
> - gen_store_spr(SPR_BOOKE_MAS7, val);
> - tcg_temp_free(val);
> -}
> -
> -static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
> -{
> - TCGv mas7 = tcg_temp_new();
> - TCGv mas3 = tcg_temp_new();
> - gen_load_spr(mas7, SPR_BOOKE_MAS7);
> - tcg_gen_shli_tl(mas7, mas7, 32);
> - gen_load_spr(mas3, SPR_BOOKE_MAS3);
> - tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
> - tcg_temp_free(mas3);
> - tcg_temp_free(mas7);
> -}
> -
> -#endif
> -
> enum fsl_e500_version {
> fsl_e500v1,
> fsl_e500v2,
> @@ -7638,58 +6757,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
> #define POWERPC970_HID5_INIT 0x00000000
> #endif
>
> -static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> - int bit, int sprn, int cause)
> -{
> - TCGv_i32 t1 = tcg_const_i32(bit);
> - TCGv_i32 t2 = tcg_const_i32(sprn);
> - TCGv_i32 t3 = tcg_const_i32(cause);
> -
> - gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
> -
> - tcg_temp_free_i32(t3);
> - tcg_temp_free_i32(t2);
> - tcg_temp_free_i32(t1);
> -}
> -
> -static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
> - int bit, int sprn, int cause)
> -{
> - TCGv_i32 t1 = tcg_const_i32(bit);
> - TCGv_i32 t2 = tcg_const_i32(sprn);
> - TCGv_i32 t3 = tcg_const_i32(cause);
> -
> - gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
> -
> - tcg_temp_free_i32(t3);
> - tcg_temp_free_i32(t2);
> - tcg_temp_free_i32(t1);
> -}
> -
> -static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
> -{
> - TCGv spr_up = tcg_temp_new();
> - TCGv spr = tcg_temp_new();
> -
> - gen_load_spr(spr, sprn - 1);
> - tcg_gen_shri_tl(spr_up, spr, 32);
> - tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
> -
> - tcg_temp_free(spr);
> - tcg_temp_free(spr_up);
> -}
> -
> -static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv spr = tcg_temp_new();
> -
> - gen_load_spr(spr, sprn - 1);
> - tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
> - gen_store_spr(sprn - 1, spr);
> -
> - tcg_temp_free(spr);
> -}
> -
> static int check_pow_970(CPUPPCState *env)
> {
> if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
> @@ -7984,24 +7051,6 @@ static void register_power5p_tb_sprs(CPUPPCState *env)
> 0x00000000);
> }
>
> -#if !defined(CONFIG_USER_ONLY)
> -static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
> -{
> - TCGv hmer = tcg_temp_new();
> -
> - gen_load_spr(hmer, sprn);
> - tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
> - gen_store_spr(sprn, hmer);
> - spr_store_dump_spr(sprn);
> - tcg_temp_free(hmer);
> -}
> -
> -static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
> -}
> -#endif /* !defined(CONFIG_USER_ONLY) */
> -
> static void register_970_lpar_sprs(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -8199,18 +7248,6 @@ static void register_power6_common_sprs(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> - spr_read_generic(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> - spr_write_generic(ctx, sprn, gprn);
> -}
> -
> static void register_power8_tce_address_control_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TAR, "TAR",
> @@ -8219,30 +7256,6 @@ static void register_power8_tce_address_control_sprs(CPUPPCState *env)
> KVM_REG_PPC_TAR, 0x00000000);
> }
>
> -static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_read_generic(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_write_generic(ctx, sprn, gprn);
> -}
> -
> -static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_read_prev_upper32(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> - spr_write_prev_upper32(ctx, sprn, gprn);
> -}
> -
> static void register_power8_tm_sprs(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_TFHAR, "TFHAR",
> @@ -8263,30 +7276,6 @@ static void register_power8_tm_sprs(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_read_generic(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_write_generic(ctx, sprn, gprn);
> -}
> -
> -static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_read_prev_upper32(ctx, gprn, sprn);
> -}
> -
> -static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
> -{
> - gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> - spr_write_prev_upper32(ctx, sprn, gprn);
> -}
> -
> static void register_power8_ebb_sprs(CPUPPCState *env)
> {
> spr_register(env, SPR_BESCRS, "BESCRS",
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 4/5] target/ppc: turned SPR R/W callbacks not static
2021-05-04 14:01 [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Bruno Larsen (billionai)
` (2 preceding siblings ...)
2021-05-04 14:01 ` [PATCH v4 3/5] target/ppc: move SPR R/W callbacks to translate.c Bruno Larsen (billionai)
@ 2021-05-04 14:01 ` Bruno Larsen (billionai)
2021-05-04 16:40 ` Richard Henderson
2021-05-04 14:01 ` [PATCH v4 5/5] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
2021-05-04 20:38 ` [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Fabiano Rosas
5 siblings, 1 reply; 14+ messages in thread
From: Bruno Larsen (billionai) @ 2021-05-04 14:01 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
To be able to compile translate_init.c.inc as a standalone file,
we have to make the callbacks accessible outside of translate.c;
This patch does exactly that
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/spr_tcg.h | 134 ++++++++++++++++++++++++++
target/ppc/translate.c | 210 ++++++++++++++++++++---------------------
2 files changed, 237 insertions(+), 107 deletions(-)
create mode 100644 target/ppc/spr_tcg.h
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
new file mode 100644
index 0000000000..1d2890dea0
--- /dev/null
+++ b/target/ppc/spr_tcg.h
@@ -0,0 +1,134 @@
+/*
+ * PowerPC emulation for qemu: read/write callbacks for SPRs
+ *
+ * Copyright (C) 2021 Instituto de Pesquisas Eldorado
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef SPR_TCG_H
+#define SPR_TCG_H
+
+/* prototypes for readers and writers for SPRs */
+void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
+void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
+void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
+void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
+void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
+void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_lr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ctr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ctr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ureg(DisasContext *ctx, int gprn, int sprn);
+void spr_read_tbl(DisasContext *ctx, int gprn, int sprn);
+void spr_read_tbu(DisasContext *ctx, int gprn, int sprn);
+void spr_read_atbl(DisasContext *ctx, int gprn, int sprn);
+void spr_read_atbu(DisasContext *ctx, int gprn, int sprn);
+void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn);
+void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn);
+void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn);
+
+#ifndef CONFIG_USER_ONLY
+void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
+void spr_write_clear(DisasContext *ctx, int sprn, int gprn);
+void spr_access_nop(DisasContext *ctx, int sprn, int gprn);
+void spr_read_decr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_decr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_tbl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_tbu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_atbl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_atbu(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ibat(DisasContext *ctx, int gprn, int sprn);
+void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn);
+void spr_read_dbat(DisasContext *ctx, int gprn, int sprn);
+void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn);
+void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn);
+void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn);
+void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn);
+void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn);
+void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn);
+void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn);
+void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn);
+void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn);
+void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
+void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_pir(DisasContext *ctx, int sprn, int gprn);
+void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn);
+void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn);
+void spr_read_thrm(DisasContext *ctx, int gprn, int sprn);
+void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn);
+void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn);
+void spr_write_eplc(DisasContext *ctx, int sprn, int gprn);
+void spr_write_epsc(DisasContext *ctx, int sprn, int gprn);
+void spr_write_mas73(DisasContext *ctx, int sprn, int gprn);
+void spr_read_mas73(DisasContext *ctx, int gprn, int sprn);
+#ifdef TARGET_PPC64
+void spr_read_cfar(DisasContext *ctx, int gprn, int sprn);
+void spr_write_cfar(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ureg(DisasContext *ctx, int sprn, int gprn);
+void spr_read_purr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_purr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_vtb(DisasContext *ctx, int gprn, int sprn);
+void spr_write_vtb(DisasContext *ctx, int sprn, int gprn);
+void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn);
+void spr_write_pidr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_hior(DisasContext *ctx, int gprn, int sprn);
+void spr_write_hior(DisasContext *ctx, int sprn, int gprn);
+void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_pcr(DisasContext *ctx, int sprn, int gprn);
+void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn);
+void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn);
+void spr_write_amr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_uamor(DisasContext *ctx, int sprn, int gprn);
+void spr_write_iamr(DisasContext *ctx, int sprn, int gprn);
+#endif
+#endif
+
+#ifdef TARGET_PPC64
+void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn);
+void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn);
+void spr_read_tar(DisasContext *ctx, int gprn, int sprn);
+void spr_write_tar(DisasContext *ctx, int sprn, int gprn);
+void spr_read_tm(DisasContext *ctx, int gprn, int sprn);
+void spr_write_tm(DisasContext *ctx, int sprn, int gprn);
+void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn);
+void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ebb(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ebb(DisasContext *ctx, int sprn, int gprn);
+void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn);
+void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn);
+void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
+void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
+#endif
+
+#endif
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e48fdc6cdf..0c7628657b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -36,6 +36,7 @@
#include "exec/translator.h"
#include "exec/log.h"
#include "qemu/atomic128.h"
+#include "spr_tcg.h"
#define CPU_SINGLE_STEP 0x1
@@ -373,7 +374,7 @@ static inline void gen_sync_exception(DisasContext *ctx)
/*****************************************************************************/
/* SPR READ/RITE CALLBACKS */
-static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
+void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
{
#if 0
sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
@@ -397,7 +398,7 @@ static void spr_load_dump_spr(int sprn)
#endif
}
-static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
+void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
{
gen_load_spr(cpu_gpr[gprn], sprn);
spr_load_dump_spr(sprn);
@@ -412,14 +413,14 @@ static void spr_store_dump_spr(int sprn)
#endif
}
-static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
+void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
{
gen_store_spr(sprn, cpu_gpr[gprn]);
spr_store_dump_spr(sprn);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
{
#ifdef TARGET_PPC64
TCGv t0 = tcg_temp_new();
@@ -432,7 +433,7 @@ static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
#endif
}
-static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
+void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -444,7 +445,7 @@ static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t1);
}
-static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
+void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
{
}
@@ -452,7 +453,7 @@ static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
/* SPR common to all PowerPC */
/* XER */
-static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
+void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
{
TCGv dst = cpu_gpr[gprn];
TCGv t0 = tcg_temp_new();
@@ -476,7 +477,7 @@ static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
tcg_temp_free(t2);
}
-static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
+void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
{
TCGv src = cpu_gpr[gprn];
/* Write all flags, while reading back check for isa300 */
@@ -492,36 +493,36 @@ static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
}
/* LR */
-static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
}
-static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
{
tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
}
/* CFAR */
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
+void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
}
-static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
+void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
{
tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
}
#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
/* CTR */
-static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
}
-static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
{
tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
}
@@ -532,13 +533,13 @@ static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
/* UPMCx */
/* USIA */
/* UDECR */
-static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
{
gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
}
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
{
gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
}
@@ -547,7 +548,7 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
/* SPR common to all non-embedded PowerPC */
/* DECR */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -558,7 +559,7 @@ static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -572,7 +573,7 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
/* SPR common to all non-embedded PowerPC, except 601 */
/* Time base */
-static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -584,7 +585,7 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -596,20 +597,18 @@ static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
}
}
-ATTRIBUTE_UNUSED
-static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
}
-ATTRIBUTE_UNUSED
-static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
+void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -621,7 +620,7 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -633,21 +632,18 @@ static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
}
}
-ATTRIBUTE_UNUSED
-static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
}
-ATTRIBUTE_UNUSED
-static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
}
#if defined(TARGET_PPC64)
-ATTRIBUTE_UNUSED
-static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -658,7 +654,7 @@ static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -670,7 +666,7 @@ static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
}
/* HDECR */
-static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -682,7 +678,7 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -694,7 +690,7 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
+void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -705,7 +701,7 @@ static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
+void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -716,7 +712,7 @@ static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -733,42 +729,42 @@ static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
/* IBAT0U...IBAT0U */
/* IBAT0L...IBAT7L */
-static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
-static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
}
-static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
@@ -777,42 +773,42 @@ static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
/* DBAT0U...DBAT7U */
/* DBAT0L...DBAT7L */
-static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
+void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
}
-static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
+void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
}
-static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
@@ -820,7 +816,7 @@ static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
}
/* SDR1 */
-static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
+void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
}
@@ -828,45 +824,45 @@ static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
#if defined(TARGET_PPC64)
/* 64 bits PowerPC specific SPRs */
/* PIDR */
-static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
}
-static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
+void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
}
-static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
tcg_temp_free(t0);
}
-static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
}
/* DPDES */
-static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
+void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
}
-static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
+void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
}
@@ -875,28 +871,28 @@ static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
/* PowerPC 601 specific registers */
/* RTC */
-static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
+void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
}
-static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
+void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
/* Must stop the translation as endianness may have changed */
@@ -906,21 +902,21 @@ static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
/* Unified bats */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
+void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState,
IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
-static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
+void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
@@ -930,7 +926,7 @@ static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
/* PowerPC 40x specific registers */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
+void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -941,7 +937,7 @@ static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
}
}
-static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
+void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -952,7 +948,7 @@ static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -966,7 +962,7 @@ static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
+void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -977,7 +973,7 @@ static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -988,7 +984,7 @@ static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
}
}
-static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
{
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -1003,20 +999,20 @@ static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
/* PowerPC 403 specific registers */
/* PBL1 / PBU1 / PBL2 / PBU2 */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
}
-static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
+void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
@@ -1026,7 +1022,7 @@ static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
#endif
/* SPE specific registers */
-static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
+void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
@@ -1034,7 +1030,7 @@ static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
tcg_temp_free_i32(t0);
}
-static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
@@ -1044,7 +1040,7 @@ static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
/* Callback used to write the exception vector base */
-static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
+void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
@@ -1054,7 +1050,7 @@ static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
+void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
{
int sprn_offs;
@@ -1082,7 +1078,7 @@ static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
#ifdef TARGET_PPC64
#ifndef CONFIG_USER_ONLY
-static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -1117,7 +1113,7 @@ static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t2);
}
-static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
+void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -1148,7 +1144,7 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t2);
}
-static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -1182,7 +1178,7 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
#endif
#ifndef CONFIG_USER_ONLY
-static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
+void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
{
gen_helper_fixup_thrm(cpu_env);
gen_load_spr(cpu_gpr[gprn], sprn);
@@ -1191,7 +1187,7 @@ static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
#endif /* !CONFIG_USER_ONLY */
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
@@ -1200,7 +1196,7 @@ static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
+void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
@@ -1209,7 +1205,7 @@ static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
@@ -1219,22 +1215,22 @@ static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
-static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
+void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t0 = tcg_const_i32(sprn);
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
tcg_temp_free_i32(t0);
}
-static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
+void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
}
-static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
+void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
}
@@ -1242,7 +1238,7 @@ static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
#endif
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
+void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
{
TCGv val = tcg_temp_new();
tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
@@ -1252,7 +1248,7 @@ static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(val);
}
-static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
+void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
{
TCGv mas7 = tcg_temp_new();
TCGv mas3 = tcg_temp_new();
@@ -1295,7 +1291,7 @@ static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
tcg_temp_free_i32(t1);
}
-static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
+void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
{
TCGv spr_up = tcg_temp_new();
TCGv spr = tcg_temp_new();
@@ -1308,7 +1304,7 @@ static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
tcg_temp_free(spr_up);
}
-static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
{
TCGv spr = tcg_temp_new();
@@ -1320,7 +1316,7 @@ static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
+void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
{
TCGv hmer = tcg_temp_new();
@@ -1331,67 +1327,67 @@ static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(hmer);
}
-static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
+void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
}
#endif /* !defined(CONFIG_USER_ONLY) */
-static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
spr_read_generic(ctx, gprn, sprn);
}
-static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
spr_write_generic(ctx, sprn, gprn);
}
-static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_read_generic(ctx, gprn, sprn);
}
-static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_write_generic(ctx, sprn, gprn);
}
-static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
+void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_read_prev_upper32(ctx, gprn, sprn);
}
-static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
{
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
spr_write_prev_upper32(ctx, sprn, gprn);
}
-static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_read_generic(ctx, gprn, sprn);
}
-static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_write_generic(ctx, sprn, gprn);
}
-static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
+void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_read_prev_upper32(ctx, gprn, sprn);
}
-static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
+void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
{
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
spr_write_prev_upper32(ctx, sprn, gprn);
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 4/5] target/ppc: turned SPR R/W callbacks not static
2021-05-04 14:01 ` [PATCH v4 4/5] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
@ 2021-05-04 16:40 ` Richard Henderson
0 siblings, 0 replies; 14+ messages in thread
From: Richard Henderson @ 2021-05-04 16:40 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: farosas, luis.pires, lucas.araujo, fernando.valle, qemu-ppc,
matheus.ferst, david
On 5/4/21 7:01 AM, Bruno Larsen (billionai) wrote:
> To be able to compile translate_init.c.inc as a standalone file,
> we have to make the callbacks accessible outside of translate.c;
> This patch does exactly that
>
> Signed-off-by: Bruno Larsen (billionai)<bruno.larsen@eldorado.org.br>
> ---
> target/ppc/spr_tcg.h | 134 ++++++++++++++++++++++++++
> target/ppc/translate.c | 210 ++++++++++++++++++++---------------------
> 2 files changed, 237 insertions(+), 107 deletions(-)
> create mode 100644 target/ppc/spr_tcg.h
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 5/5] target/ppc: isolated cpu init from translation logic
2021-05-04 14:01 [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Bruno Larsen (billionai)
` (3 preceding siblings ...)
2021-05-04 14:01 ` [PATCH v4 4/5] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
@ 2021-05-04 14:01 ` Bruno Larsen (billionai)
2021-05-04 20:38 ` [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Fabiano Rosas
5 siblings, 0 replies; 14+ messages in thread
From: Bruno Larsen (billionai) @ 2021-05-04 14:01 UTC (permalink / raw)
To: qemu-devel
Cc: farosas, richard.henderson, luis.pires, lucas.araujo,
fernando.valle, qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
finished isolation of CPU initialization logic from
translation logic. CPU initialization now only has common code
and may or may not call accelerator-specific code, as the
build options require.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/{translate_init.c.inc => cpu_init.c} | 6 ++++++
target/ppc/meson.build | 1 +
target/ppc/spr_tcg.h | 2 ++
target/ppc/translate.c | 4 ++--
4 files changed, 11 insertions(+), 2 deletions(-)
rename target/ppc/{translate_init.c.inc => cpu_init.c} (99%)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/cpu_init.c
similarity index 99%
rename from target/ppc/translate_init.c.inc
rename to target/ppc/cpu_init.c
index c913058170..0a1d67a98c 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/cpu_init.c
@@ -18,6 +18,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "disas/dis-asm.h"
#include "exec/gdbstub.h"
#include "kvm_ppc.h"
@@ -42,6 +43,11 @@
#include "fpu/softfloat.h"
#include "qapi/qapi-commands-machine-target.h"
+#include "exec/helper-proto.h"
+#include "helper_regs.h"
+#include "internal.h"
+#include "spr_tcg.h"
+
/* #define PPC_DEBUG_SPR */
/* #define USE_APPLE_GDB */
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index bbfef90e08..ad53629298 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -2,6 +2,7 @@ ppc_ss = ss.source_set()
ppc_ss.add(files(
'cpu-models.c',
'cpu.c',
+ 'cpu_init.c',
'dfp_helper.c',
'excp_helper.c',
'fpu_helper.c',
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 1d2890dea0..0be5f347d5 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -19,6 +19,8 @@
#ifndef SPR_TCG_H
#define SPR_TCG_H
+#define SPR_NOACCESS (&spr_noaccess)
+
/* prototypes for readers and writers for SPRs */
void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0c7628657b..7958f2f7da 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -38,6 +38,8 @@
#include "qemu/atomic128.h"
#include "spr_tcg.h"
+#include "qemu/qemu-print.h"
+#include "qapi/error.h"
#define CPU_SINGLE_STEP 0x1
#define CPU_BRANCH_STEP 0x2
@@ -381,7 +383,6 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
printf("ERROR: try to access SPR %d !\n", sprn);
#endif
}
-#define SPR_NOACCESS (&spr_noaccess)
/* #define PPC_DUMP_SPR_ACCESSES */
@@ -8617,7 +8618,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
};
#include "helper_regs.h"
-#include "translate_init.c.inc"
/*****************************************************************************/
/* Misc PowerPC helpers */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 0/5] target/ppc: Untangle CPU init from translation
2021-05-04 14:01 [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Bruno Larsen (billionai)
` (4 preceding siblings ...)
2021-05-04 14:01 ` [PATCH v4 5/5] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
@ 2021-05-04 20:38 ` Fabiano Rosas
2021-05-05 11:30 ` Bruno Piazera Larsen
5 siblings, 1 reply; 14+ messages in thread
From: Fabiano Rosas @ 2021-05-04 20:38 UTC (permalink / raw)
To: Bruno Larsen (billionai), qemu-devel
Cc: richard.henderson, lucas.araujo, luis.pires, fernando.valle,
qemu-ppc, Bruno Larsen (billionai),
matheus.ferst, david
"Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br> writes:
> Based-on: ppc-for-6.1 tree
>
> This patch series aims to remove the logic of initializing CPU from
> the file related to TCG translation. To achieve this, we have to make
> it so registering SPRs isn't directly tied to TCG, and move code only
> related to translation out of translate_init.c.inc and into translate.c.
> This is in preparation to compile this target without TCG.
>
> Changes for v4:
> * reordered patches, to make partially applying simpler
> * removed patches that were already applied
> * undone creation of spt_tcg.c.inc, now waiting for further cleanup
> * moved SPR_NOACCESS motion to last patch, and to spr_tcg.h
>
> Changes for v3:
> * fixed the parameters of _spr_register
> * remove some redundant #include statements
> * removed some functions that were mentioned in v2 as unnecessary
> * added copyright header to relevant files
> * removed first patch, that was already applied
> * removed a changed that would add a regression
>
> Changes for v2:
> * split and reordered patches, to make it easier to review
> * improved commit messages
> * Undid creation of spr_common, as it was unnecessary
> * kept more functions as static
> * ensured that the project builds after every commit
>
> Bruno Larsen (billionai) (5):
> target/ppc: Fold gen_*_xer into their callers
> target/ppc: renamed SPR registration functions
> target/ppc: move SPR R/W callbacks to translate.c
> target/ppc: turned SPR R/W callbacks not static
> target/ppc: isolated cpu init from translation logic
>
> .../ppc/{translate_init.c.inc => cpu_init.c} | 1848 ++++-------------
> target/ppc/meson.build | 1 +
> target/ppc/spr_tcg.h | 136 ++
> target/ppc/translate.c | 1072 +++++++++-
> 4 files changed, 1598 insertions(+), 1459 deletions(-)
> rename target/ppc/{translate_init.c.inc => cpu_init.c} (89%)
> create mode 100644 target/ppc/spr_tcg.h
We're still missing some changes:
- some files (hw/ppc/pnv.c, hw/ppc/spapr.c) use oea_read to check if an
SPR exists. This needs to be changed to something that is present in
both configs (I believe Bruno is working on this).
- The commit 6113563982 ("target/ppc: Clean up _spr_register et al")
from the ppc-for-6.1 branch missed some TCG-specific code in
gen_spr_BookE206:
$ ../configure --target-list=ppc64-softmmu --disable-tcg
$ make
(...)
[193/264] Compiling C object libqemu-ppc64-softmmu.fa.p/target_ppc_cpu_init.c.o
FAILED: libqemu-ppc64-softmmu.fa.p/target_ppc_cpu_init.c.o
(...)
../target/ppc/cpu_init.c: In function ‘register_BookE206_sprs’:
../target/ppc/cpu_init.c:1207:16: error: variable ‘uea_write’ set but not used [-Werror=unused-but-set-variable]
void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
^~~~~~~~~
cc1: all warnings being treated as errors
We need something like:
--- a/target/ppc/translate_init.c.inc 2021-05-04 16:24:53.549556292 -0400
+++ b/target/ppc/translate_init.c.inc 2021-05-04 16:26:41.005280971 -0400
@@ -2025,11 +2025,13 @@
/* TLB assist registers */
/* XXX : not implemented */
for (i = 0; i < 8; i++) {
+#ifdef CONFIG_TCG
void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
&spr_write_generic32;
if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
uea_write = &spr_write_generic;
}
+#endif
if (mas_mask & (1 << i)) {
spr_register(env, mas_sprn[i], mas_names[i],
SPR_NOACCESS, SPR_NOACCESS,
---
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v4 0/5] target/ppc: Untangle CPU init from translation
2021-05-04 20:38 ` [PATCH v4 0/5] target/ppc: Untangle CPU init from translation Fabiano Rosas
@ 2021-05-05 11:30 ` Bruno Piazera Larsen
0 siblings, 0 replies; 14+ messages in thread
From: Bruno Piazera Larsen @ 2021-05-05 11:30 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: richard.henderson, lucas.araujo, luis.pires, fernando.valle,
qemu-ppc, matheus.ferst, david
[-- Attachment #1: Type: text/plain, Size: 5023 bytes --]
On 04/05/2021 17:38, Fabiano Rosas wrote:
> "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br> writes:
>
>> Based-on: ppc-for-6.1 tree
>>
>> This patch series aims to remove the logic of initializing CPU from
>> the file related to TCG translation. To achieve this, we have to make
>> it so registering SPRs isn't directly tied to TCG, and move code only
>> related to translation out of translate_init.c.inc and into translate.c.
>> This is in preparation to compile this target without TCG.
>>
>> Changes for v4:
>> * reordered patches, to make partially applying simpler
>> * removed patches that were already applied
>> * undone creation of spt_tcg.c.inc, now waiting for further cleanup
>> * moved SPR_NOACCESS motion to last patch, and to spr_tcg.h
>>
>> Changes for v3:
>> * fixed the parameters of _spr_register
>> * remove some redundant #include statements
>> * removed some functions that were mentioned in v2 as unnecessary
>> * added copyright header to relevant files
>> * removed first patch, that was already applied
>> * removed a changed that would add a regression
>>
>> Changes for v2:
>> * split and reordered patches, to make it easier to review
>> * improved commit messages
>> * Undid creation of spr_common, as it was unnecessary
>> * kept more functions as static
>> * ensured that the project builds after every commit
>>
>> Bruno Larsen (billionai) (5):
>> target/ppc: Fold gen_*_xer into their callers
>> target/ppc: renamed SPR registration functions
>> target/ppc: move SPR R/W callbacks to translate.c
>> target/ppc: turned SPR R/W callbacks not static
>> target/ppc: isolated cpu init from translation logic
>>
>> .../ppc/{translate_init.c.inc => cpu_init.c} | 1848 ++++-------------
>> target/ppc/meson.build | 1 +
>> target/ppc/spr_tcg.h | 136 ++
>> target/ppc/translate.c | 1072 +++++++++-
>> 4 files changed, 1598 insertions(+), 1459 deletions(-)
>> rename target/ppc/{translate_init.c.inc => cpu_init.c} (89%)
>> create mode 100644 target/ppc/spr_tcg.h
> We're still missing some changes:
>
> - some files (hw/ppc/pnv.c, hw/ppc/spapr.c) use oea_read to check if an
> SPR exists. This needs to be changed to something that is present in
> both configs (I believe Bruno is working on this).
>
> - The commit 6113563982 ("target/ppc: Clean up _spr_register et al")
> from the ppc-for-6.1 branch missed some TCG-specific code in
> gen_spr_BookE206:
These patches are all in preparation for disabling TCG. I wouldn't
expect the project to support that flag yet, so the errors make sense
and are being worked on.
I guess I did things in a weird order, so let me explain my thought
process for the work so far: In my first RFC (when I still thought it
was an easy-ish fix) I tried to define what needed to be done so the
project would build. Then I went back to the drawing board, and decided
to implement good solutions, and only expect the --disable-tcg to work
at the very end of these, otherwise the bodged solutions could be
forgotten and committed into the final tree by accident. Now that I know
the code motion was done in a satisfactory manner, I'll move on to these
issues and what else shows up.
>
> $ ../configure --target-list=ppc64-softmmu --disable-tcg
> $ make
> (...)
> [193/264] Compiling C object libqemu-ppc64-softmmu.fa.p/target_ppc_cpu_init.c.o
> FAILED: libqemu-ppc64-softmmu.fa.p/target_ppc_cpu_init.c.o
> (...)
> ../target/ppc/cpu_init.c: In function ‘register_BookE206_sprs’:
> ../target/ppc/cpu_init.c:1207:16: error: variable ‘uea_write’ set but not used [-Werror=unused-but-set-variable]
> void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
> ^~~~~~~~~
> cc1: all warnings being treated as errors
>
> We need something like:
>
> --- a/target/ppc/translate_init.c.inc 2021-05-04 16:24:53.549556292 -0400
> +++ b/target/ppc/translate_init.c.inc 2021-05-04 16:26:41.005280971 -0400
> @@ -2025,11 +2025,13 @@
> /* TLB assist registers */
> /* XXX : not implemented */
> for (i = 0; i < 8; i++) {
> +#ifdef CONFIG_TCG
> void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
> &spr_write_generic32;
> if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
> uea_write = &spr_write_generic;
> }
> +#endif
> if (mas_mask & (1 << i)) {
> spr_register(env, mas_sprn[i], mas_names[i],
> SPR_NOACCESS, SPR_NOACCESS,
> ---
Also ran into this problem, I intend to fix it as well. If you find
anything else, let me know :)
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
[-- Attachment #2: Type: text/html, Size: 5786 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread