* [PULL 01/10] hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 02/10] hw/sparc/sun4m: Introduce Sun4mMachineClass Mark Cave-Ayland
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Introduce the TYPE_SUN4M_MACHINE and have all sun4m
machines inherit it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20210503171303.822501-2-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/sun4m.c | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 1a00816d9a..9d07fa43d6 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -107,6 +107,8 @@ struct sun4m_hwdef {
uint8_t nvram_machine_id;
};
+#define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common")
+
const char *fw_cfg_arch_key_name(uint16_t key)
{
static const struct {
@@ -1433,7 +1435,7 @@ static void ss5_class_init(ObjectClass *oc, void *data)
static const TypeInfo ss5_type = {
.name = MACHINE_TYPE_NAME("SS-5"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = ss5_class_init,
};
@@ -1453,7 +1455,7 @@ static void ss10_class_init(ObjectClass *oc, void *data)
static const TypeInfo ss10_type = {
.name = MACHINE_TYPE_NAME("SS-10"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = ss10_class_init,
};
@@ -1473,7 +1475,7 @@ static void ss600mp_class_init(ObjectClass *oc, void *data)
static const TypeInfo ss600mp_type = {
.name = MACHINE_TYPE_NAME("SS-600MP"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = ss600mp_class_init,
};
@@ -1493,7 +1495,7 @@ static void ss20_class_init(ObjectClass *oc, void *data)
static const TypeInfo ss20_type = {
.name = MACHINE_TYPE_NAME("SS-20"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = ss20_class_init,
};
@@ -1512,7 +1514,7 @@ static void voyager_class_init(ObjectClass *oc, void *data)
static const TypeInfo voyager_type = {
.name = MACHINE_TYPE_NAME("Voyager"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = voyager_class_init,
};
@@ -1531,7 +1533,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data)
static const TypeInfo ss_lx_type = {
.name = MACHINE_TYPE_NAME("LX"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = ss_lx_class_init,
};
@@ -1550,7 +1552,7 @@ static void ss4_class_init(ObjectClass *oc, void *data)
static const TypeInfo ss4_type = {
.name = MACHINE_TYPE_NAME("SS-4"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = ss4_class_init,
};
@@ -1569,7 +1571,7 @@ static void scls_class_init(ObjectClass *oc, void *data)
static const TypeInfo scls_type = {
.name = MACHINE_TYPE_NAME("SPARCClassic"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = scls_class_init,
};
@@ -1588,10 +1590,20 @@ static void sbook_class_init(ObjectClass *oc, void *data)
static const TypeInfo sbook_type = {
.name = MACHINE_TYPE_NAME("SPARCbook"),
- .parent = TYPE_MACHINE,
+ .parent = TYPE_SUN4M_MACHINE,
.class_init = sbook_class_init,
};
+static const TypeInfo sun4m_machine_types[] = {
+ {
+ .name = TYPE_SUN4M_MACHINE,
+ .parent = TYPE_MACHINE,
+ .abstract = true,
+ }
+};
+
+DEFINE_TYPES(sun4m_machine_types)
+
static void sun4m_register_types(void)
{
type_register_static(&idreg_info);
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 02/10] hw/sparc/sun4m: Introduce Sun4mMachineClass
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 01/10] hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 03/10] hw/sparc/sun4m: Factor out sun4m_machine_class_init() Mark Cave-Ayland
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Instead of passing the sun4m_hwdef structure via
machine_init(), store it into the MachineClass.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20210503171303.822501-3-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/sun4m.c | 50 +++++++++++++++++++++++++++++++++++++-----------
1 file changed, 39 insertions(+), 11 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 9d07fa43d6..c2bc8a9fa5 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -107,7 +107,16 @@ struct sun4m_hwdef {
uint8_t nvram_machine_id;
};
+struct Sun4mMachineClass {
+ /*< private >*/
+ MachineClass parent_obj;
+ /*< public >*/
+ const struct sun4m_hwdef *hwdef;
+};
+typedef struct Sun4mMachineClass Sun4mMachineClass;
+
#define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common")
+DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE)
const char *fw_cfg_arch_key_name(uint16_t key)
{
@@ -839,9 +848,9 @@ static void dummy_fdc_tc(void *opaque, int irq, int level)
{
}
-static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
- MachineState *machine)
+static void sun4m_hw_init(MachineState *machine)
{
+ const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef;
DeviceState *slavio_intctl;
unsigned int i;
Nvram *nvram;
@@ -1368,60 +1377,61 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
/* SPARCstation 5 hardware initialisation */
static void ss5_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[0], machine);
+ sun4m_hw_init(machine);
}
/* SPARCstation 10 hardware initialisation */
static void ss10_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[1], machine);
+ sun4m_hw_init(machine);
}
/* SPARCserver 600MP hardware initialisation */
static void ss600mp_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[2], machine);
+ sun4m_hw_init(machine);
}
/* SPARCstation 20 hardware initialisation */
static void ss20_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[3], machine);
+ sun4m_hw_init(machine);
}
/* SPARCstation Voyager hardware initialisation */
static void vger_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[4], machine);
+ sun4m_hw_init(machine);
}
/* SPARCstation LX hardware initialisation */
static void ss_lx_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[5], machine);
+ sun4m_hw_init(machine);
}
/* SPARCstation 4 hardware initialisation */
static void ss4_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[6], machine);
+ sun4m_hw_init(machine);
}
/* SPARCClassic hardware initialisation */
static void scls_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[7], machine);
+ sun4m_hw_init(machine);
}
/* SPARCbook hardware initialisation */
static void sbook_init(MachineState *machine)
{
- sun4m_hw_init(&sun4m_hwdefs[8], machine);
+ sun4m_hw_init(machine);
}
static void ss5_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 5";
mc->init = ss5_init;
@@ -1431,6 +1441,7 @@ static void ss5_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[0];
}
static const TypeInfo ss5_type = {
@@ -1442,6 +1453,7 @@ static const TypeInfo ss5_type = {
static void ss10_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 10";
mc->init = ss10_init;
@@ -1451,6 +1463,7 @@ static void ss10_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[1];
}
static const TypeInfo ss10_type = {
@@ -1462,6 +1475,7 @@ static const TypeInfo ss10_type = {
static void ss600mp_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCserver 600MP";
mc->init = ss600mp_init;
@@ -1471,6 +1485,7 @@ static void ss600mp_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[2];
}
static const TypeInfo ss600mp_type = {
@@ -1482,6 +1497,7 @@ static const TypeInfo ss600mp_type = {
static void ss20_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 20";
mc->init = ss20_init;
@@ -1491,6 +1507,7 @@ static void ss20_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[3];
}
static const TypeInfo ss20_type = {
@@ -1502,6 +1519,7 @@ static const TypeInfo ss20_type = {
static void voyager_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation Voyager";
mc->init = vger_init;
@@ -1510,6 +1528,7 @@ static void voyager_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[4];
}
static const TypeInfo voyager_type = {
@@ -1521,6 +1540,7 @@ static const TypeInfo voyager_type = {
static void ss_lx_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation LX";
mc->init = ss_lx_init;
@@ -1529,6 +1549,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[5];
}
static const TypeInfo ss_lx_type = {
@@ -1540,6 +1561,7 @@ static const TypeInfo ss_lx_type = {
static void ss4_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 4";
mc->init = ss4_init;
@@ -1548,6 +1570,7 @@ static void ss4_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[6];
}
static const TypeInfo ss4_type = {
@@ -1559,6 +1582,7 @@ static const TypeInfo ss4_type = {
static void scls_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCClassic";
mc->init = scls_init;
@@ -1567,6 +1591,7 @@ static void scls_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[7];
}
static const TypeInfo scls_type = {
@@ -1578,6 +1603,7 @@ static const TypeInfo scls_type = {
static void sbook_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCbook";
mc->init = sbook_init;
@@ -1586,6 +1612,7 @@ static void sbook_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
mc->default_display = "tcx";
mc->default_ram_id = "sun4m.ram";
+ smc->hwdef = &sun4m_hwdefs[8];
}
static const TypeInfo sbook_type = {
@@ -1598,6 +1625,7 @@ static const TypeInfo sun4m_machine_types[] = {
{
.name = TYPE_SUN4M_MACHINE,
.parent = TYPE_MACHINE,
+ .class_size = sizeof(Sun4mMachineClass),
.abstract = true,
}
};
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 03/10] hw/sparc/sun4m: Factor out sun4m_machine_class_init()
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 01/10] hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 02/10] hw/sparc/sun4m: Introduce Sun4mMachineClass Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 04/10] hw/sparc/sun4m: Register machine types in sun4m_machine_types[] Mark Cave-Ayland
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Factor out the class_init code common to all machines
to sun4m_machine_class_init().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20210503171303.822501-4-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/sun4m.c | 103 ++++-------------------------------------------
1 file changed, 8 insertions(+), 95 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index c2bc8a9fa5..56f927e66c 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -1374,58 +1374,15 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
},
};
-/* SPARCstation 5 hardware initialisation */
-static void ss5_init(MachineState *machine)
+static void sun4m_machine_class_init(ObjectClass *oc, void *data)
{
- sun4m_hw_init(machine);
-}
-
-/* SPARCstation 10 hardware initialisation */
-static void ss10_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
-}
-
-/* SPARCserver 600MP hardware initialisation */
-static void ss600mp_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
-}
-
-/* SPARCstation 20 hardware initialisation */
-static void ss20_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
-}
-
-/* SPARCstation Voyager hardware initialisation */
-static void vger_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
-}
-
-/* SPARCstation LX hardware initialisation */
-static void ss_lx_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
-}
-
-/* SPARCstation 4 hardware initialisation */
-static void ss4_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
-}
-
-/* SPARCClassic hardware initialisation */
-static void scls_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
-}
+ MachineClass *mc = MACHINE_CLASS(oc);
-/* SPARCbook hardware initialisation */
-static void sbook_init(MachineState *machine)
-{
- sun4m_hw_init(machine);
+ mc->init = sun4m_hw_init;
+ mc->block_default_type = IF_SCSI;
+ mc->default_boot_order = "c";
+ mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
}
static void ss5_class_init(ObjectClass *oc, void *data)
@@ -1434,13 +1391,8 @@ static void ss5_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 5";
- mc->init = ss5_init;
- mc->block_default_type = IF_SCSI;
mc->is_default = true;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[0];
}
@@ -1456,13 +1408,8 @@ static void ss10_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 10";
- mc->init = ss10_init;
- mc->block_default_type = IF_SCSI;
mc->max_cpus = 4;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[1];
}
@@ -1478,13 +1425,8 @@ static void ss600mp_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCserver 600MP";
- mc->init = ss600mp_init;
- mc->block_default_type = IF_SCSI;
mc->max_cpus = 4;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[2];
}
@@ -1500,13 +1442,8 @@ static void ss20_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 20";
- mc->init = ss20_init;
- mc->block_default_type = IF_SCSI;
mc->max_cpus = 4;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[3];
}
@@ -1522,12 +1459,7 @@ static void voyager_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation Voyager";
- mc->init = vger_init;
- mc->block_default_type = IF_SCSI;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[4];
}
@@ -1543,12 +1475,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation LX";
- mc->init = ss_lx_init;
- mc->block_default_type = IF_SCSI;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[5];
}
@@ -1564,12 +1491,7 @@ static void ss4_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCstation 4";
- mc->init = ss4_init;
- mc->block_default_type = IF_SCSI;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[6];
}
@@ -1585,12 +1507,7 @@ static void scls_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCClassic";
- mc->init = scls_init;
- mc->block_default_type = IF_SCSI;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[7];
}
@@ -1606,12 +1523,7 @@ static void sbook_class_init(ObjectClass *oc, void *data)
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
mc->desc = "Sun4m platform, SPARCbook";
- mc->init = sbook_init;
- mc->block_default_type = IF_SCSI;
- mc->default_boot_order = "c";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
smc->hwdef = &sun4m_hwdefs[8];
}
@@ -1626,6 +1538,7 @@ static const TypeInfo sun4m_machine_types[] = {
.name = TYPE_SUN4M_MACHINE,
.parent = TYPE_MACHINE,
.class_size = sizeof(Sun4mMachineClass),
+ .class_init = sun4m_machine_class_init,
.abstract = true,
}
};
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 04/10] hw/sparc/sun4m: Register machine types in sun4m_machine_types[]
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (2 preceding siblings ...)
2021-05-05 7:35 ` [PULL 03/10] hw/sparc/sun4m: Factor out sun4m_machine_class_init() Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 05/10] hw/sparc/sun4m: Fix code style for checkpatch.pl Mark Cave-Ayland
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20210503171303.822501-5-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/sun4m.c | 100 +++++++++++++++++------------------------------
1 file changed, 36 insertions(+), 64 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 56f927e66c..a625c41cd3 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -1396,12 +1396,6 @@ static void ss5_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[0];
}
-static const TypeInfo ss5_type = {
- .name = MACHINE_TYPE_NAME("SS-5"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = ss5_class_init,
-};
-
static void ss10_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1413,12 +1407,6 @@ static void ss10_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[1];
}
-static const TypeInfo ss10_type = {
- .name = MACHINE_TYPE_NAME("SS-10"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = ss10_class_init,
-};
-
static void ss600mp_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1430,12 +1418,6 @@ static void ss600mp_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[2];
}
-static const TypeInfo ss600mp_type = {
- .name = MACHINE_TYPE_NAME("SS-600MP"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = ss600mp_class_init,
-};
-
static void ss20_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1447,12 +1429,6 @@ static void ss20_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[3];
}
-static const TypeInfo ss20_type = {
- .name = MACHINE_TYPE_NAME("SS-20"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = ss20_class_init,
-};
-
static void voyager_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1463,12 +1439,6 @@ static void voyager_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[4];
}
-static const TypeInfo voyager_type = {
- .name = MACHINE_TYPE_NAME("Voyager"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = voyager_class_init,
-};
-
static void ss_lx_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1479,12 +1449,6 @@ static void ss_lx_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[5];
}
-static const TypeInfo ss_lx_type = {
- .name = MACHINE_TYPE_NAME("LX"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = ss_lx_class_init,
-};
-
static void ss4_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1495,12 +1459,6 @@ static void ss4_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[6];
}
-static const TypeInfo ss4_type = {
- .name = MACHINE_TYPE_NAME("SS-4"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = ss4_class_init,
-};
-
static void scls_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1511,12 +1469,6 @@ static void scls_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[7];
}
-static const TypeInfo scls_type = {
- .name = MACHINE_TYPE_NAME("SPARCClassic"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = scls_class_init,
-};
-
static void sbook_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1527,14 +1479,44 @@ static void sbook_class_init(ObjectClass *oc, void *data)
smc->hwdef = &sun4m_hwdefs[8];
}
-static const TypeInfo sbook_type = {
- .name = MACHINE_TYPE_NAME("SPARCbook"),
- .parent = TYPE_SUN4M_MACHINE,
- .class_init = sbook_class_init,
-};
-
static const TypeInfo sun4m_machine_types[] = {
{
+ .name = MACHINE_TYPE_NAME("SS-5"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = ss5_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("SS-10"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = ss10_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("SS-600MP"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = ss600mp_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("SS-20"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = ss20_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("Voyager"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = voyager_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("LX"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = ss_lx_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("SS-4"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = ss4_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("SPARCClassic"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = scls_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("SPARCbook"),
+ .parent = TYPE_SUN4M_MACHINE,
+ .class_init = sbook_class_init,
+ }, {
.name = TYPE_SUN4M_MACHINE,
.parent = TYPE_MACHINE,
.class_size = sizeof(Sun4mMachineClass),
@@ -1551,16 +1533,6 @@ static void sun4m_register_types(void)
type_register_static(&afx_info);
type_register_static(&prom_info);
type_register_static(&ram_info);
-
- type_register_static(&ss5_type);
- type_register_static(&ss10_type);
- type_register_static(&ss600mp_type);
- type_register_static(&ss20_type);
- type_register_static(&voyager_type);
- type_register_static(&ss_lx_type);
- type_register_static(&ss4_type);
- type_register_static(&scls_type);
- type_register_static(&sbook_type);
}
type_init(sun4m_register_types)
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 05/10] hw/sparc/sun4m: Fix code style for checkpatch.pl
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (3 preceding siblings ...)
2021-05-05 7:35 ` [PULL 04/10] hw/sparc/sun4m: Register machine types in sun4m_machine_types[] Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 06/10] hw/sparc/sun4m: Move each sun4m_hwdef definition in its class_init Mark Cave-Ayland
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
We are going to move this code, fix its style first.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20210503171303.822501-6-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/sun4m.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index a625c41cd3..956216591b 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -1181,11 +1181,11 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.dma_base = 0xef0400000ULL,
.esp_base = 0xef0800000ULL,
.le_base = 0xef0c00000ULL,
- .apc_base = 0xefa000000ULL, // XXX should not exist
+ .apc_base = 0xefa000000ULL, /* XXX should not exist */
.aux1_base = 0xff1800000ULL,
.aux2_base = 0xff1a01000ULL,
.ecc_base = 0xf00000000ULL,
- .ecc_version = 0x10000000, // version 0, implementation 1
+ .ecc_version = 0x10000000, /* version 0, implementation 1 */
.nvram_machine_id = 0x72,
.machine_id = ss10_id,
.iommu_version = 0x03000000,
@@ -1204,11 +1204,11 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.dma_base = 0xef0081000ULL,
.esp_base = 0xef0080000ULL,
.le_base = 0xef0060000ULL,
- .apc_base = 0xefa000000ULL, // XXX should not exist
+ .apc_base = 0xefa000000ULL, /* XXX should not exist */
.aux1_base = 0xff1800000ULL,
- .aux2_base = 0xff1a01000ULL, // XXX should not exist
+ .aux2_base = 0xff1a01000ULL, /* XXX should not exist */
.ecc_base = 0xf00000000ULL,
- .ecc_version = 0x00000000, // version 0, implementation 0
+ .ecc_version = 0x00000000, /* version 0, implementation 0 */
.nvram_machine_id = 0x71,
.machine_id = ss600mp_id,
.iommu_version = 0x01000000,
@@ -1230,7 +1230,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.esp_base = 0xef0800000ULL,
.le_base = 0xef0c00000ULL,
.bpp_base = 0xef4800000ULL,
- .apc_base = 0xefa000000ULL, // XXX should not exist
+ .apc_base = 0xefa000000ULL, /* XXX should not exist */
.aux1_base = 0xff1800000ULL,
.aux2_base = 0xff1a01000ULL,
.dbri_base = 0xee0000000ULL,
@@ -1249,7 +1249,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
}
},
.ecc_base = 0xf00000000ULL,
- .ecc_version = 0x20000000, // version 0, implementation 2
+ .ecc_version = 0x20000000, /* version 0, implementation 2 */
.nvram_machine_id = 0x72,
.machine_id = ss20_id,
.iommu_version = 0x13000000,
@@ -1270,7 +1270,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.dma_base = 0x78400000,
.esp_base = 0x78800000,
.le_base = 0x78c00000,
- .apc_base = 0x71300000, // pmc
+ .apc_base = 0x71300000, /* pmc */
.aux1_base = 0x71900000,
.aux2_base = 0x71910000,
.nvram_machine_id = 0x80,
@@ -1352,7 +1352,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
/* SPARCbook */
{
.iommu_base = 0x10000000,
- .tcx_base = 0x50000000, // XXX
+ .tcx_base = 0x50000000, /* XXX */
.slavio_base = 0x70000000,
.ms_kb_base = 0x71000000,
.serial_base = 0x71100000,
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 06/10] hw/sparc/sun4m: Move each sun4m_hwdef definition in its class_init
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (4 preceding siblings ...)
2021-05-05 7:35 ` [PULL 05/10] hw/sparc/sun4m: Fix code style for checkpatch.pl Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 07/10] hw/sparc: Allow building without the leon3 machine Mark Cave-Ayland
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Remove the sun4m_hwdefs[] array by moving assigning the
structure fields directly in each machine class_init()
function.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20210503171303.822501-7-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/sun4m.c | 248 ++++++++++++++++++++++-------------------------
1 file changed, 118 insertions(+), 130 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 956216591b..263732b904 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -1138,9 +1138,22 @@ enum {
ss600mp_id,
};
-static const struct sun4m_hwdef sun4m_hwdefs[] = {
- /* SS-5 */
- {
+static void sun4m_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->init = sun4m_hw_init;
+ mc->block_default_type = IF_SCSI;
+ mc->default_boot_order = "c";
+ mc->default_display = "tcx";
+ mc->default_ram_id = "sun4m.ram";
+}
+
+static void ss5_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef ss5_hwdef = {
.iommu_base = 0x10000000,
.iommu_pad_base = 0x10004000,
.iommu_pad_len = 0x0fffb000,
@@ -1165,9 +1178,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = ss5_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- },
- /* SS-10 */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCstation 5";
+ mc->is_default = true;
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
+ smc->hwdef = &ss5_hwdef;
+}
+
+static void ss10_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef ss10_hwdef = {
.iommu_base = 0xfe0000000ULL,
.tcx_base = 0xe20000000ULL,
.slavio_base = 0xff0000000ULL,
@@ -1190,9 +1213,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = ss10_id,
.iommu_version = 0x03000000,
.max_mem = 0xf00000000ULL,
- },
- /* SS-600MP */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCstation 10";
+ mc->max_cpus = 4;
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
+ smc->hwdef = &ss10_hwdef;
+}
+
+static void ss600mp_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef ss600mp_hwdef = {
.iommu_base = 0xfe0000000ULL,
.tcx_base = 0xe20000000ULL,
.slavio_base = 0xff0000000ULL,
@@ -1213,9 +1246,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = ss600mp_id,
.iommu_version = 0x01000000,
.max_mem = 0xf00000000ULL,
- },
- /* SS-20 */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCserver 600MP";
+ mc->max_cpus = 4;
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
+ smc->hwdef = &ss600mp_hwdef;
+}
+
+static void ss20_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef ss20_hwdef = {
.iommu_base = 0xfe0000000ULL,
.tcx_base = 0xe20000000ULL,
.slavio_base = 0xff0000000ULL,
@@ -1254,9 +1297,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = ss20_id,
.iommu_version = 0x13000000,
.max_mem = 0xf00000000ULL,
- },
- /* Voyager */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCstation 20";
+ mc->max_cpus = 4;
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
+ smc->hwdef = &ss20_hwdef;
+}
+
+static void voyager_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef voyager_hwdef = {
.iommu_base = 0x10000000,
.tcx_base = 0x50000000,
.slavio_base = 0x70000000,
@@ -1277,9 +1330,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = vger_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- },
- /* LX */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCstation Voyager";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
+ smc->hwdef = &voyager_hwdef;
+}
+
+static void ss_lx_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef ss_lx_hwdef = {
.iommu_base = 0x10000000,
.iommu_pad_base = 0x10004000,
.iommu_pad_len = 0x0fffb000,
@@ -1301,9 +1363,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = lx_id,
.iommu_version = 0x04000000,
.max_mem = 0x10000000,
- },
- /* SS-4 */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCstation LX";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
+ smc->hwdef = &ss_lx_hwdef;
+}
+
+static void ss4_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef ss4_hwdef = {
.iommu_base = 0x10000000,
.tcx_base = 0x50000000,
.cs_base = 0x6c000000,
@@ -1325,9 +1396,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = ss4_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- },
- /* SPARCClassic */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCstation 4";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
+ smc->hwdef = &ss4_hwdef;
+}
+
+static void scls_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef scls_hwdef = {
.iommu_base = 0x10000000,
.tcx_base = 0x50000000,
.slavio_base = 0x70000000,
@@ -1348,9 +1428,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = scls_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- },
- /* SPARCbook */
- {
+ };
+
+ mc->desc = "Sun4m platform, SPARCClassic";
+ mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
+ smc->hwdef = &scls_hwdef;
+}
+
+static void sbook_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ static const struct sun4m_hwdef sbook_hwdef = {
.iommu_base = 0x10000000,
.tcx_base = 0x50000000, /* XXX */
.slavio_base = 0x70000000,
@@ -1371,112 +1460,11 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
.machine_id = sbook_id,
.iommu_version = 0x05000000,
.max_mem = 0x10000000,
- },
-};
-
-static void sun4m_machine_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->init = sun4m_hw_init;
- mc->block_default_type = IF_SCSI;
- mc->default_boot_order = "c";
- mc->default_display = "tcx";
- mc->default_ram_id = "sun4m.ram";
-}
-
-static void ss5_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCstation 5";
- mc->is_default = true;
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
- smc->hwdef = &sun4m_hwdefs[0];
-}
-
-static void ss10_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCstation 10";
- mc->max_cpus = 4;
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
- smc->hwdef = &sun4m_hwdefs[1];
-}
-
-static void ss600mp_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCserver 600MP";
- mc->max_cpus = 4;
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
- smc->hwdef = &sun4m_hwdefs[2];
-}
-
-static void ss20_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCstation 20";
- mc->max_cpus = 4;
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
- smc->hwdef = &sun4m_hwdefs[3];
-}
-
-static void voyager_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCstation Voyager";
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
- smc->hwdef = &sun4m_hwdefs[4];
-}
-
-static void ss_lx_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCstation LX";
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
- smc->hwdef = &sun4m_hwdefs[5];
-}
-
-static void ss4_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCstation 4";
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
- smc->hwdef = &sun4m_hwdefs[6];
-}
-
-static void scls_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
-
- mc->desc = "Sun4m platform, SPARCClassic";
- mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
- smc->hwdef = &sun4m_hwdefs[7];
-}
-
-static void sbook_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
+ };
mc->desc = "Sun4m platform, SPARCbook";
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
- smc->hwdef = &sun4m_hwdefs[8];
+ smc->hwdef = &sbook_hwdef;
}
static const TypeInfo sun4m_machine_types[] = {
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 07/10] hw/sparc: Allow building without the leon3 machine
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (5 preceding siblings ...)
2021-05-05 7:35 ` [PULL 06/10] hw/sparc/sun4m: Move each sun4m_hwdef definition in its class_init Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 08/10] hw/sparc64: Remove unused "hw/char/serial.h" header Mark Cave-Ayland
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
When building without the leon3 machine, we get this link failure:
/usr/bin/ld: target_sparc_int32_helper.c.o: in function `leon3_irq_manager':
target/sparc/int32_helper.c:172: undefined reference to `leon3_irq_ack'
This is because the leon3_irq_ack() is declared in hw/sparc/leon3.c,
which is only build when CONFIG_LEON3 is selected.
Fix by moving the leon3_cache_control_int() / leon3_irq_manager()
(which are specific to the leon3 machine) to hw/sparc/leon3.c.
Move the trace events along (but don't rename them).
leon3_irq_ack() is now locally used, declare it static to reduce
its scope.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20210428141655.387430-2-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/leon3.c | 37 ++++++++++++++++++++++++++++++++++++-
hw/sparc/trace-events | 2 ++
target/sparc/cpu.h | 6 ------
target/sparc/int32_helper.c | 37 -------------------------------------
target/sparc/trace-events | 4 ----
5 files changed, 38 insertions(+), 48 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 7e16eea9e6..98e3789cf8 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -137,7 +137,36 @@ static void main_cpu_reset(void *opaque)
env->regbase[6] = s->sp;
}
-void leon3_irq_ack(void *irq_manager, int intno)
+static void leon3_cache_control_int(CPUSPARCState *env)
+{
+ uint32_t state = 0;
+
+ if (env->cache_control & CACHE_CTRL_IF) {
+ /* Instruction cache state */
+ state = env->cache_control & CACHE_STATE_MASK;
+ if (state == CACHE_ENABLED) {
+ state = CACHE_FROZEN;
+ trace_int_helper_icache_freeze();
+ }
+
+ env->cache_control &= ~CACHE_STATE_MASK;
+ env->cache_control |= state;
+ }
+
+ if (env->cache_control & CACHE_CTRL_DF) {
+ /* Data cache state */
+ state = (env->cache_control >> 2) & CACHE_STATE_MASK;
+ if (state == CACHE_ENABLED) {
+ state = CACHE_FROZEN;
+ trace_int_helper_dcache_freeze();
+ }
+
+ env->cache_control &= ~(CACHE_STATE_MASK << 2);
+ env->cache_control |= (state << 2);
+ }
+}
+
+static void leon3_irq_ack(void *irq_manager, int intno)
{
grlib_irqmp_ack((DeviceState *)irq_manager, intno);
}
@@ -181,6 +210,12 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
}
}
+static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
+{
+ leon3_irq_ack(irq_manager, intno);
+ leon3_cache_control_int(env);
+}
+
static void leon3_generic_hw_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events
index 355b07ae05..dfb53dc1a2 100644
--- a/hw/sparc/trace-events
+++ b/hw/sparc/trace-events
@@ -19,3 +19,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64
# leon3.c
leon3_set_irq(int intno) "Set CPU IRQ %d"
leon3_reset_irq(int intno) "Reset CPU IRQ %d"
+int_helper_icache_freeze(void) "Instruction cache: freeze"
+int_helper_dcache_freeze(void) "Data cache: freeze"
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650b..ff8ae73002 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -615,15 +615,9 @@ int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
-/* int_helper.c */
-void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
-
/* sun4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);
-/* leon3.c */
-void leon3_irq_ack(void *irq_manager, int intno);
-
#if defined (TARGET_SPARC64)
static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index 817a463a17..d008dbdb65 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -136,40 +136,3 @@ void sparc_cpu_do_interrupt(CPUState *cs)
}
#endif
}
-
-#if !defined(CONFIG_USER_ONLY)
-static void leon3_cache_control_int(CPUSPARCState *env)
-{
- uint32_t state = 0;
-
- if (env->cache_control & CACHE_CTRL_IF) {
- /* Instruction cache state */
- state = env->cache_control & CACHE_STATE_MASK;
- if (state == CACHE_ENABLED) {
- state = CACHE_FROZEN;
- trace_int_helper_icache_freeze();
- }
-
- env->cache_control &= ~CACHE_STATE_MASK;
- env->cache_control |= state;
- }
-
- if (env->cache_control & CACHE_CTRL_DF) {
- /* Data cache state */
- state = (env->cache_control >> 2) & CACHE_STATE_MASK;
- if (state == CACHE_ENABLED) {
- state = CACHE_FROZEN;
- trace_int_helper_dcache_freeze();
- }
-
- env->cache_control &= ~(CACHE_STATE_MASK << 2);
- env->cache_control |= (state << 2);
- }
-}
-
-void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
-{
- leon3_irq_ack(irq_manager, intno);
- leon3_cache_control_int(env);
-}
-#endif
diff --git a/target/sparc/trace-events b/target/sparc/trace-events
index 6a064e2327..e925ddd1cc 100644
--- a/target/sparc/trace-events
+++ b/target/sparc/trace-events
@@ -15,10 +15,6 @@ int_helper_set_softint(uint32_t softint) "new 0x%08x"
int_helper_clear_softint(uint32_t softint) "new 0x%08x"
int_helper_write_softint(uint32_t softint) "new 0x%08x"
-# int32_helper.c
-int_helper_icache_freeze(void) "Instruction cache: freeze"
-int_helper_dcache_freeze(void) "Data cache: freeze"
-
# win_helper.c
win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
win_helper_switch_pstate(uint32_t pstate_regs, uint32_t new_pstate_regs) "change_pstate: switching regs old=0x%x new=0x%x"
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 08/10] hw/sparc64: Remove unused "hw/char/serial.h" header
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (6 preceding siblings ...)
2021-05-05 7:35 ` [PULL 07/10] hw/sparc: Allow building without the leon3 machine Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 09/10] hw/sparc64: Fix code style for checkpatch.pl Mark Cave-Ayland
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210428141655.387430-3-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc64/sparc64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index e3f9219a10..cc0b9bd30d 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -26,7 +26,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/boards.h"
-#include "hw/char/serial.h"
#include "hw/sparc/sparc64.h"
#include "qemu/timer.h"
#include "sysemu/reset.h"
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 09/10] hw/sparc64: Fix code style for checkpatch.pl
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (7 preceding siblings ...)
2021-05-05 7:35 ` [PULL 08/10] hw/sparc64: Remove unused "hw/char/serial.h" header Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-05 7:35 ` [PULL 10/10] hw/sparc*: Move cpu_check_irqs() to target/sparc/ Mark Cave-Ayland
2021-05-10 14:29 ` [PULL 00/10] qemu-sparc queue 20210505 Peter Maydell
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210428141655.387430-4-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc64/sparc64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index cc0b9bd30d..fd29a79edc 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env)
return;
}
cs = env_cpu(env);
- /* check if TM or SM in SOFTINT are set
- setting these also causes interrupt 14 */
+ /*
+ * check if TM or SM in SOFTINT are set
+ * setting these also causes interrupt 14
+ */
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
pil |= 1 << 14;
}
- /* The bit corresponding to psrpil is (1<< psrpil), the next bit
- is (2 << psrpil). */
+ /*
+ * The bit corresponding to psrpil is (1<< psrpil),
+ * the next bit is (2 << psrpil).
+ */
if (pil < (2 << env->psrpil)) {
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PULL 10/10] hw/sparc*: Move cpu_check_irqs() to target/sparc/
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (8 preceding siblings ...)
2021-05-05 7:35 ` [PULL 09/10] hw/sparc64: Fix code style for checkpatch.pl Mark Cave-Ayland
@ 2021-05-05 7:35 ` Mark Cave-Ayland
2021-05-10 14:29 ` [PULL 00/10] qemu-sparc queue 20210505 Peter Maydell
10 siblings, 0 replies; 12+ messages in thread
From: Mark Cave-Ayland @ 2021-05-05 7:35 UTC (permalink / raw)
To: peter.maydell, qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Since cpu_check_irqs() doesn't reference to anything outside
of CPUSPARCState, it better belongs to the architectural code
in target/, rather than the hardware specific code in hw/.
Note: while we moved the trace events, we don't rename them.
Remark: this allows us to build the leon3 machine stand alone,
fixing this link failure (because cpu_check_irqs is defined in
hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected):
/usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr':
target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs'
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210428141655.387430-5-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/sparc/sun4m.c | 32 ------------------
hw/sparc/trace-events | 2 --
hw/sparc64/sparc64.c | 66 -------------------------------------
hw/sparc64/trace-events | 4 ---
target/sparc/int32_helper.c | 33 +++++++++++++++++++
target/sparc/int64_helper.c | 66 +++++++++++++++++++++++++++++++++++++
target/sparc/trace-events | 8 +++++
7 files changed, 107 insertions(+), 104 deletions(-)
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 263732b904..42e139849e 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -170,38 +170,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr,
}
}
-void cpu_check_irqs(CPUSPARCState *env)
-{
- CPUState *cs;
-
- /* We should be holding the BQL before we mess with IRQs */
- g_assert(qemu_mutex_iothread_locked());
-
- if (env->pil_in && (env->interrupt_index == 0 ||
- (env->interrupt_index & ~15) == TT_EXTINT)) {
- unsigned int i;
-
- for (i = 15; i > 0; i--) {
- if (env->pil_in & (1 << i)) {
- int old_interrupt = env->interrupt_index;
-
- env->interrupt_index = TT_EXTINT | i;
- if (old_interrupt != env->interrupt_index) {
- cs = env_cpu(env);
- trace_sun4m_cpu_interrupt(i);
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
- }
- break;
- }
- }
- } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
- cs = env_cpu(env);
- trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
- env->interrupt_index = 0;
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- }
-}
-
static void cpu_kick_irq(SPARCCPU *cpu)
{
CPUSPARCState *env = &cpu->env;
diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events
index dfb53dc1a2..d3a30a816a 100644
--- a/hw/sparc/trace-events
+++ b/hw/sparc/trace-events
@@ -1,8 +1,6 @@
# See docs/devel/tracing.txt for syntax documentation.
# sun4m.c
-sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
-sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index fd29a79edc..8654e955eb 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -34,72 +34,6 @@
#define TICK_MAX 0x7fffffffffffffffULL
-void cpu_check_irqs(CPUSPARCState *env)
-{
- CPUState *cs;
- uint32_t pil = env->pil_in |
- (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
-
- /* We should be holding the BQL before we mess with IRQs */
- g_assert(qemu_mutex_iothread_locked());
-
- /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
- if (env->ivec_status & 0x20) {
- return;
- }
- cs = env_cpu(env);
- /*
- * check if TM or SM in SOFTINT are set
- * setting these also causes interrupt 14
- */
- if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
- pil |= 1 << 14;
- }
-
- /*
- * The bit corresponding to psrpil is (1<< psrpil),
- * the next bit is (2 << psrpil).
- */
- if (pil < (2 << env->psrpil)) {
- if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
- trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
- env->interrupt_index = 0;
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- }
- return;
- }
-
- if (cpu_interrupts_enabled(env)) {
-
- unsigned int i;
-
- for (i = 15; i > env->psrpil; i--) {
- if (pil & (1 << i)) {
- int old_interrupt = env->interrupt_index;
- int new_interrupt = TT_EXTINT | i;
-
- if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
- && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
- trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
- cpu_tsptr(env)->tt,
- new_interrupt);
- } else if (old_interrupt != new_interrupt) {
- env->interrupt_index = new_interrupt;
- trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
- new_interrupt);
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
- }
- break;
- }
- }
- } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
- trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
- env->interrupt_index);
- env->interrupt_index = 0;
- cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- }
-}
-
static void cpu_kick_irq(SPARCCPU *cpu)
{
CPUState *cs = CPU(cpu);
diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events
index a0b29987d2..b85d14c30c 100644
--- a/hw/sparc64/trace-events
+++ b/hw/sparc64/trace-events
@@ -9,10 +9,6 @@ sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64"
sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64
# sparc64.c
-sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
-sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
-sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
-sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d"
sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d"
sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled"
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index d008dbdb65..82e8418e46 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "trace.h"
#include "exec/log.h"
@@ -64,6 +65,38 @@ static const char *excp_name_str(int32_t exception_index)
return excp_names[exception_index];
}
+void cpu_check_irqs(CPUSPARCState *env)
+{
+ CPUState *cs;
+
+ /* We should be holding the BQL before we mess with IRQs */
+ g_assert(qemu_mutex_iothread_locked());
+
+ if (env->pil_in && (env->interrupt_index == 0 ||
+ (env->interrupt_index & ~15) == TT_EXTINT)) {
+ unsigned int i;
+
+ for (i = 15; i > 0; i--) {
+ if (env->pil_in & (1 << i)) {
+ int old_interrupt = env->interrupt_index;
+
+ env->interrupt_index = TT_EXTINT | i;
+ if (old_interrupt != env->interrupt_index) {
+ cs = env_cpu(env);
+ trace_sun4m_cpu_interrupt(i);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ break;
+ }
+ }
+ } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
+ cs = env_cpu(env);
+ trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
void sparc_cpu_do_interrupt(CPUState *cs)
{
SPARCCPU *cpu = SPARC_CPU(cs);
diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c
index 7fb8ab211c..793e57c536 100644
--- a/target/sparc/int64_helper.c
+++ b/target/sparc/int64_helper.c
@@ -62,6 +62,72 @@ static const char * const excp_names[0x80] = {
};
#endif
+void cpu_check_irqs(CPUSPARCState *env)
+{
+ CPUState *cs;
+ uint32_t pil = env->pil_in |
+ (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
+
+ /* We should be holding the BQL before we mess with IRQs */
+ g_assert(qemu_mutex_iothread_locked());
+
+ /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
+ if (env->ivec_status & 0x20) {
+ return;
+ }
+ cs = env_cpu(env);
+ /*
+ * check if TM or SM in SOFTINT are set
+ * setting these also causes interrupt 14
+ */
+ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
+ pil |= 1 << 14;
+ }
+
+ /*
+ * The bit corresponding to psrpil is (1<< psrpil),
+ * the next bit is (2 << psrpil).
+ */
+ if (pil < (2 << env->psrpil)) {
+ if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+ trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ return;
+ }
+
+ if (cpu_interrupts_enabled(env)) {
+
+ unsigned int i;
+
+ for (i = 15; i > env->psrpil; i--) {
+ if (pil & (1 << i)) {
+ int old_interrupt = env->interrupt_index;
+ int new_interrupt = TT_EXTINT | i;
+
+ if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
+ && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
+ trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
+ cpu_tsptr(env)->tt,
+ new_interrupt);
+ } else if (old_interrupt != new_interrupt) {
+ env->interrupt_index = new_interrupt;
+ trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
+ new_interrupt);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ break;
+ }
+ }
+ } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+ trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
+ env->interrupt_index);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
void sparc_cpu_do_interrupt(CPUState *cs)
{
SPARCCPU *cpu = SPARC_CPU(cs);
diff --git a/target/sparc/trace-events b/target/sparc/trace-events
index e925ddd1cc..75e7093d5f 100644
--- a/target/sparc/trace-events
+++ b/target/sparc/trace-events
@@ -10,10 +10,18 @@ mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, u
mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64
mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx64" -> 0x%"PRIx64", mmu_idx=%d tl=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64
+# int32_helper.c
+sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
+sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
+
# int64_helper.c
int_helper_set_softint(uint32_t softint) "new 0x%08x"
int_helper_clear_softint(uint32_t softint) "new 0x%08x"
int_helper_write_softint(uint32_t softint) "new 0x%08x"
+sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
+sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
+sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
+sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
# win_helper.c
win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
--
2.20.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PULL 00/10] qemu-sparc queue 20210505
2021-05-05 7:35 [PULL 00/10] qemu-sparc queue 20210505 Mark Cave-Ayland
` (9 preceding siblings ...)
2021-05-05 7:35 ` [PULL 10/10] hw/sparc*: Move cpu_check_irqs() to target/sparc/ Mark Cave-Ayland
@ 2021-05-10 14:29 ` Peter Maydell
10 siblings, 0 replies; 12+ messages in thread
From: Peter Maydell @ 2021-05-10 14:29 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: QEMU Developers
On Wed, 5 May 2021 at 08:35, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> The following changes since commit 3e13d8e34b53d8f9a3421a816ccfbdc5fa874e98:
>
> Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210430' into staging (2021-05-04 10:58:56 +0100)
>
> are available in the Git repository at:
>
> git://github.com/mcayland/qemu.git tags/qemu-sparc-20210505
>
> for you to fetch changes up to 10fb1340b161682d64320a5976f88f68472410bf:
>
> hw/sparc*: Move cpu_check_irqs() to target/sparc/ (2021-05-04 22:45:53 +0100)
>
> ----------------------------------------------------------------
> qemu-sparc queue
>
> ----------------------------------------------------------------
> Philippe Mathieu-Daudé (10):
> hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE
> hw/sparc/sun4m: Introduce Sun4mMachineClass
> hw/sparc/sun4m: Factor out sun4m_machine_class_init()
> hw/sparc/sun4m: Register machine types in sun4m_machine_types[]
> hw/sparc/sun4m: Fix code style for checkpatch.pl
> hw/sparc/sun4m: Move each sun4m_hwdef definition in its class_init
> hw/sparc: Allow building without the leon3 machine
> hw/sparc64: Remove unused "hw/char/serial.h" header
> hw/sparc64: Fix code style for checkpatch.pl
> hw/sparc*: Move cpu_check_irqs() to target/sparc/
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread