From: chun-jie.chen <chun-jie.chen@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Nicolas Boichat <drinkcat@chromium.org>, "Rob Herring" <robh+dt@kernel.org> Cc: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, chun-jie.chen <chun-jie.chen@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com> Subject: [PATCH v8 21/22] clk: mediatek: Add MT8192 vdecsys clock support Date: Wed, 5 May 2021 18:07:13 +0800 [thread overview] Message-ID: <20210505100714.3582-22-chun-jie.chen@mediatek.com> (raw) In-Reply-To: <20210505100714.3582-1-chun-jie.chen@mediatek.com> Add MT8192 vdecsys and vdecsys soc clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-vdec.c | 94 ++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index eb4aa29d8106..31779f2c5c83 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -568,6 +568,12 @@ config COMMON_CLK_MT8192_SCP_ADSP help This driver supports MediaTek MT8192 scp_adsp clocks. +config COMMON_CLK_MT8192_VDECSYS + bool "Clock driver for MediaTek MT8192 vdecsys" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index a336fe753e9a..887dd6bcf7f2 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -78,5 +78,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MFGCFG) += clk-mt8192-mfg.o obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o +obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c new file mode 100644 index 000000000000..a6043c1a99e7 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi.lu@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs vdec0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x4, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs vdec1_cg_regs = { + .set_ofs = 0x200, + .clr_ofs = 0x204, + .sta_ofs = 0x200, +}; + +static const struct mtk_gate_regs vdec2_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x8, +}; + +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate vdec_clks[] = { + /* VDEC0 */ + GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0), + GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4), + /* VDEC1 */ + GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0), + GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4), + /* VDEC2 */ + GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0), +}; + +static const struct mtk_gate vdec_soc_clks[] = { + /* VDEC_SOC0 */ + GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0), + GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4), + /* VDEC_SOC1 */ + GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0), + GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4), + /* VDEC_SOC2 */ + GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0), +}; + +static const struct mtk_clk_desc vdec_desc = { + .clks = vdec_clks, + .num_clks = ARRAY_SIZE(vdec_clks), +}; + +static const struct mtk_clk_desc vdec_soc_desc = { + .clks = vdec_soc_clks, + .num_clks = ARRAY_SIZE(vdec_soc_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_vdec[] = { + { + .compatible = "mediatek,mt8192-vdecsys", + .data = &vdec_desc, + }, { + .compatible = "mediatek,mt8192-vdecsys_soc", + .data = &vdec_soc_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8192_vdec_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8192-vdec", + .of_match_table = of_match_clk_mt8192_vdec, + }, +}; + +builtin_platform_driver(clk_mt8192_vdec_drv); -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: chun-jie.chen <chun-jie.chen@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Nicolas Boichat <drinkcat@chromium.org>, "Rob Herring" <robh+dt@kernel.org> Cc: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, chun-jie.chen <chun-jie.chen@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com> Subject: [PATCH v8 21/22] clk: mediatek: Add MT8192 vdecsys clock support Date: Wed, 5 May 2021 18:07:13 +0800 [thread overview] Message-ID: <20210505100714.3582-22-chun-jie.chen@mediatek.com> (raw) In-Reply-To: <20210505100714.3582-1-chun-jie.chen@mediatek.com> Add MT8192 vdecsys and vdecsys soc clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-vdec.c | 94 ++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index eb4aa29d8106..31779f2c5c83 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -568,6 +568,12 @@ config COMMON_CLK_MT8192_SCP_ADSP help This driver supports MediaTek MT8192 scp_adsp clocks. +config COMMON_CLK_MT8192_VDECSYS + bool "Clock driver for MediaTek MT8192 vdecsys" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index a336fe753e9a..887dd6bcf7f2 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -78,5 +78,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MFGCFG) += clk-mt8192-mfg.o obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o +obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c new file mode 100644 index 000000000000..a6043c1a99e7 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi.lu@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs vdec0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x4, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs vdec1_cg_regs = { + .set_ofs = 0x200, + .clr_ofs = 0x204, + .sta_ofs = 0x200, +}; + +static const struct mtk_gate_regs vdec2_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x8, +}; + +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate vdec_clks[] = { + /* VDEC0 */ + GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0), + GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4), + /* VDEC1 */ + GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0), + GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4), + /* VDEC2 */ + GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0), +}; + +static const struct mtk_gate vdec_soc_clks[] = { + /* VDEC_SOC0 */ + GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0), + GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4), + /* VDEC_SOC1 */ + GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0), + GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4), + /* VDEC_SOC2 */ + GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0), +}; + +static const struct mtk_clk_desc vdec_desc = { + .clks = vdec_clks, + .num_clks = ARRAY_SIZE(vdec_clks), +}; + +static const struct mtk_clk_desc vdec_soc_desc = { + .clks = vdec_soc_clks, + .num_clks = ARRAY_SIZE(vdec_soc_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_vdec[] = { + { + .compatible = "mediatek,mt8192-vdecsys", + .data = &vdec_desc, + }, { + .compatible = "mediatek,mt8192-vdecsys_soc", + .data = &vdec_soc_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8192_vdec_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8192-vdec", + .of_match_table = of_match_clk_mt8192_vdec, + }, +}; + +builtin_platform_driver(clk_mt8192_vdec_drv); -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-05 10:24 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-05 10:06 [PATCH v8 00/22] Mediatek MT8192 clock support chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 10/22] clk: mediatek: Add MT8192 basic clocks support chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 11/22] clk: mediatek: Add MT8192 audio clock support chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 12/22] clk: mediatek: Add MT8192 camsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 13/22] clk: mediatek: Add MT8192 imgsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 14/22] clk: mediatek: Add MT8192 imp i2c wrapper " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 15/22] clk: mediatek: Add MT8192 ipesys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 16/22] clk: mediatek: Add MT8192 mdpsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 17/22] clk: mediatek: Add MT8192 mfgcfg " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 18/22] clk: mediatek: Add MT8192 mmsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 19/22] clk: mediatek: Add MT8192 msdc " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 20/22] clk: mediatek: Add MT8192 scp adsp " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen [this message] 2021-05-05 10:07 ` [PATCH v8 21/22] clk: mediatek: Add MT8192 vdecsys " chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 22/22] clk: mediatek: Add MT8192 vencsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen
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