* [PATCH v6 00/17] support subsets of bitmanip extension
@ 2021-05-05 16:06 frank.chang
2021-05-05 16:06 ` frank.chang
` (17 more replies)
0 siblings, 18 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Frank Chang
From: Frank Chang <frank.chang@sifive.com>
This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and
Zbs subset instructions. Some Zbp instructions are also implemented as
they have similar behavior with their Zba-, Zbb- and Zbs-family
instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
Specification:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf
The port is available here:
https://github.com/sifive/qemu/tree/rvb-upstream-v6
To test rvb implementation, specify cpu argument with 'x-b=true' or
'x-b=true,bext_spec=v0.93'to enable B-extension support.
Changelog:
v6:
* rebase riscv-to-apply.next branch.
* remove all #ifdef TARGET_RISCV64 macros.
v5:
* add bext_spec cpu option, default set to v0.93.
* rebase master branch.
v4:
* Remove 'rd != 0' checks from immediate shift instructions.
v3:
* Convert existing immediate shift instructions to use gen_shifti()
and gen_shiftiw() interfaces.
* Rename *u.w instructions to *.uw.
* Rename sb* instructions to b*.
* Rename pcnt* instructions to cpop*.
v2:
* Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions.
* Remove addwu, subwu and addiwu instructions as they are not longer
exist in latest draft.
* Optimize implementation with cleaner tcg ops.
Frank Chang (6):
target/riscv: rvb: count bits set
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
target/riscv: rvb: single-bit instructions
target/riscv: rvb: generalized reverse
target/riscv: rvb: generalized or-combine
target/riscv: rvb: add b-ext version cpu option
Kito Cheng (11):
target/riscv: reformat @sh format encoding for B-extension
target/riscv: rvb: count leading/trailing zeros
target/riscv: rvb: logic-with-negate
target/riscv: rvb: pack two words into one register
target/riscv: rvb: min/max instructions
target/riscv: rvb: sign-extend instructions
target/riscv: rvb: shift ones
target/riscv: rvb: rotate (left/right)
target/riscv: rvb: address calculation
target/riscv: rvb: add/shift with prefix zero-extend
target/riscv: rvb: support and turn on B-extension from command line
target/riscv/bitmanip_helper.c | 90 +++++
target/riscv/cpu.c | 27 ++
target/riscv/cpu.h | 5 +
target/riscv/helper.h | 6 +
target/riscv/insn32.decode | 87 ++++-
target/riscv/insn_trans/trans_rvb.c.inc | 438 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.c.inc | 54 +--
target/riscv/meson.build | 1 +
target/riscv/translate.c | 306 +++++++++++++++++
9 files changed, 958 insertions(+), 56 deletions(-)
create mode 100644 target/riscv/bitmanip_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Kito Cheng, Bin Meng, Palmer Dabbelt
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8901ba1e1bf..f75642bb0d2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,7 +23,7 @@
%rd 7:5
%sh5 20:5
-%sh10 20:10
+%sh7 20:7
%csr 20:12
%rm 12:3
%nf 29:3 !function=ex_plus_1
@@ -59,7 +59,7 @@
@u .................... ..... ....... &u imm=%imm_u %rd
@j .................... ..... ....... &j imm=%imm_j %rd
-@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@@ -125,9 +125,9 @@ sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
-slli 00.... ...... ..... 001 ..... 0010011 @sh
-srli 00.... ...... ..... 101 ..... 0010011 @sh
-srai 01.... ...... ..... 101 ..... 0010011 @sh
+slli 00000. ...... ..... 001 ..... 0010011 @sh
+srli 00000. ...... ..... 101 ..... 0010011 @sh
+srai 01000. ...... ..... 101 ..... 0010011 @sh
add 0000000 ..... ..... 000 ..... 0110011 @r
sub 0100000 ..... ..... 000 ..... 0110011 @r
sll 0000000 ..... ..... 001 ..... 0110011 @r
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis, Bin Meng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8901ba1e1bf..f75642bb0d2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,7 +23,7 @@
%rd 7:5
%sh5 20:5
-%sh10 20:10
+%sh7 20:7
%csr 20:12
%rm 12:3
%nf 29:3 !function=ex_plus_1
@@ -59,7 +59,7 @@
@u .................... ..... ....... &u imm=%imm_u %rd
@j .................... ..... ....... &j imm=%imm_j %rd
-@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@@ -125,9 +125,9 @@ sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
-slli 00.... ...... ..... 001 ..... 0010011 @sh
-srli 00.... ...... ..... 101 ..... 0010011 @sh
-srai 01.... ...... ..... 101 ..... 0010011 @sh
+slli 00000. ...... ..... 001 ..... 0010011 @sh
+srli 00000. ...... ..... 101 ..... 0010011 @sh
+srai 01000. ...... ..... 101 ..... 0010011 @sh
add 0000000 ..... ..... 000 ..... 0110011 @r
sub 0100000 ..... ..... 000 ..... 0110011 @r
sll 0000000 ..... ..... 001 ..... 0110011 @r
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 11 ++++++-
target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++
target/riscv/translate.c | 38 +++++++++++++++++++++
4 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7e879fb9ca5..f95bcbd8e10 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f75642bb0d2..9a2ffab1504 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -41,6 +41,7 @@
&i imm rs1 rd
&j imm rd
&r rd rs1 rs2
+&r2 rd rs1
&s imm rs1 rs2
&u imm rd
&shift shamt rs1 rd
@@ -68,7 +69,7 @@
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -657,3 +658,11 @@ vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+
+# *** RV32B Standard Extension ***
+clz 011000 000000 ..... 001 ..... 0010011 @r2
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index 00000000000..157b4e3c41d
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -0,0 +1,44 @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_clz);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_ctz);
+}
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_clzw);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_ctzw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e945352bca3..60fac0fe27e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -548,6 +548,19 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
return true;
}
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
+ tcg_gen_ctzi_tl(ret, ret, 64);
+}
+
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(ret, arg1);
+ tcg_gen_clzi_tl(ret, ret, 64);
+ tcg_gen_subi_tl(ret, ret, 32);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -593,6 +606,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
return cpu_ldl_code(env, pc);
}
+static void gen_ctz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static void gen_clz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+ void(*func)(TCGv, TCGv))
+{
+ TCGv source = tcg_temp_new();
+
+ gen_get_gpr(source, a->rs1);
+
+ (*func)(source, source);
+
+ gen_set_gpr(a->rd, source);
+ tcg_temp_free(source);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.c.inc"
#include "insn_trans/trans_rvm.c.inc"
@@ -601,6 +638,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvd.c.inc"
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 11 ++++++-
target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++
target/riscv/translate.c | 38 +++++++++++++++++++++
4 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7e879fb9ca5..f95bcbd8e10 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f75642bb0d2..9a2ffab1504 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -41,6 +41,7 @@
&i imm rs1 rd
&j imm rd
&r rd rs1 rs2
+&r2 rd rs1
&s imm rs1 rs2
&u imm rd
&shift shamt rs1 rd
@@ -68,7 +69,7 @@
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -657,3 +658,11 @@ vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+
+# *** RV32B Standard Extension ***
+clz 011000 000000 ..... 001 ..... 0010011 @r2
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index 00000000000..157b4e3c41d
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -0,0 +1,44 @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_clz);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_ctz);
+}
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_clzw);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_ctzw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e945352bca3..60fac0fe27e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -548,6 +548,19 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
return true;
}
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
+ tcg_gen_ctzi_tl(ret, ret, 64);
+}
+
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(ret, arg1);
+ tcg_gen_clzi_tl(ret, ret, 64);
+ tcg_gen_subi_tl(ret, ret, 32);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -593,6 +606,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
return cpu_ldl_code(env, pc);
}
+static void gen_ctz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static void gen_clz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+ void(*func)(TCGv, TCGv))
+{
+ TCGv source = tcg_temp_new();
+
+ gen_get_gpr(source, a->rs1);
+
+ (*func)(source, source);
+
+ gen_set_gpr(a->rd, source);
+ tcg_temp_free(source);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.c.inc"
#include "insn_trans/trans_rvm.c.inc"
@@ -601,6 +638,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvd.c.inc"
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 03/17] target/riscv: rvb: count bits set
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
target/riscv/translate.c | 6 ++++++
3 files changed, 21 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9a2ffab1504..6f7671872d2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -662,7 +662,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
+cpop 011000 000010 ..... 001 ..... 0010011 @r2
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 157b4e3c41d..4a5d271b438 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
return gen_unary(ctx, a, gen_ctz);
}
+static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ctpop_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -42,3 +48,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_ctzw);
}
+
+static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_cpopw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 60fac0fe27e..c1a30c21723 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -561,6 +561,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
tcg_gen_subi_tl(ret, ret, 32);
}
+static void gen_cpopw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_ctpop_tl(ret, arg1);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 03/17] target/riscv: rvb: count bits set
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Kito Cheng, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
target/riscv/translate.c | 6 ++++++
3 files changed, 21 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9a2ffab1504..6f7671872d2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -662,7 +662,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
+cpop 011000 000010 ..... 001 ..... 0010011 @r2
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 157b4e3c41d..4a5d271b438 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
return gen_unary(ctx, a, gen_ctz);
}
+static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ctpop_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -42,3 +48,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_ctzw);
}
+
+static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, gen_cpopw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 60fac0fe27e..c1a30c21723 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -561,6 +561,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
tcg_gen_subi_tl(ret, ret, 32);
}
+static void gen_cpopw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_ctpop_tl(ret, arg1);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 04/17] target/riscv: rvb: logic-with-negate
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f7671872d2..a4d95ea6217 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -663,6 +663,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+andn 0100000 .......... 111 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+xnor 0100000 .......... 100 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 4a5d271b438..b8676785c6f 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
return gen_unary(ctx, a, tcg_gen_ctpop_tl);
}
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_andc_tl);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_orc_tl);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_eqv_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 04/17] target/riscv: rvb: logic-with-negate
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f7671872d2..a4d95ea6217 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -663,6 +663,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+andn 0100000 .......... 111 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+xnor 0100000 .......... 100 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 4a5d271b438..b8676785c6f 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
return gen_unary(ctx, a, tcg_gen_ctpop_tl);
}
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_andc_tl);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_orc_tl);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_eqv_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 05/17] target/riscv: rvb: pack two words into one register
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++
target/riscv/translate.c | 40 +++++++++++++++++++++++++
3 files changed, 78 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a4d95ea6217..9b2fd4b6fe8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -666,8 +666,14 @@ cpop 011000 000010 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
+pack 0000100 .......... 100 ..... 0110011 @r
+packu 0100100 .......... 100 ..... 0110011 @r
+packh 0000100 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+
+packw 0000100 .......... 100 ..... 0111011 @r
+packuw 0100100 .......... 100 ..... 0111011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b8676785c6f..770205f96f7 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, tcg_gen_eqv_tl);
}
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_pack);
+}
+
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packu);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packh);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -73,3 +91,17 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_cpopw);
}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packw);
+}
+
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packuw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c1a30c21723..5f1a3c694fe 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -548,6 +548,29 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
return true;
}
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_deposit_tl(ret, arg1, arg2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
+ tcg_temp_free(t);
+}
+
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext8u_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -567,6 +590,23 @@ static void gen_cpopw(TCGv ret, TCGv arg1)
tcg_gen_ctpop_tl(ret, arg1);
}
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext16s_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
+ tcg_temp_free(t);
+}
+
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, 16);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
+ tcg_gen_ext32s_tl(ret, ret);
+ tcg_temp_free(t);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 05/17] target/riscv: rvb: pack two words into one register
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++
target/riscv/translate.c | 40 +++++++++++++++++++++++++
3 files changed, 78 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a4d95ea6217..9b2fd4b6fe8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -666,8 +666,14 @@ cpop 011000 000010 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
+pack 0000100 .......... 100 ..... 0110011 @r
+packu 0100100 .......... 100 ..... 0110011 @r
+packh 0000100 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+
+packw 0000100 .......... 100 ..... 0111011 @r
+packuw 0100100 .......... 100 ..... 0111011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b8676785c6f..770205f96f7 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, tcg_gen_eqv_tl);
}
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_pack);
+}
+
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packu);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packh);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -73,3 +91,17 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_cpopw);
}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packw);
+}
+
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packuw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c1a30c21723..5f1a3c694fe 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -548,6 +548,29 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
return true;
}
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_deposit_tl(ret, arg1, arg2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
+ tcg_temp_free(t);
+}
+
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext8u_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -567,6 +590,23 @@ static void gen_cpopw(TCGv ret, TCGv arg1)
tcg_gen_ctpop_tl(ret, arg1);
}
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext16s_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
+ tcg_temp_free(t);
+}
+
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, 16);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
+ tcg_gen_ext32s_tl(ret, ret);
+ tcg_temp_free(t);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 06/17] target/riscv: rvb: min/max instructions
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9b2fd4b6fe8..81dfdfbafdc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -669,6 +669,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
+min 0000101 .......... 100 ..... 0110011 @r
+minu 0000101 .......... 101 ..... 0110011 @r
+max 0000101 .......... 110 ..... 0110011 @r
+maxu 0000101 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 770205f96f7..5a4fc02f705 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
return gen_arith(ctx, a, gen_packh);
}
+static bool trans_min(DisasContext *ctx, arg_min *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_smin_tl);
+}
+
+static bool trans_max(DisasContext *ctx, arg_max *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_smax_tl);
+}
+
+static bool trans_minu(DisasContext *ctx, arg_minu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_umin_tl);
+}
+
+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_umax_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 06/17] target/riscv: rvb: min/max instructions
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9b2fd4b6fe8..81dfdfbafdc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -669,6 +669,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
+min 0000101 .......... 100 ..... 0110011 @r
+minu 0000101 .......... 101 ..... 0110011 @r
+max 0000101 .......... 110 ..... 0110011 @r
+maxu 0000101 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 770205f96f7..5a4fc02f705 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
return gen_arith(ctx, a, gen_packh);
}
+static bool trans_min(DisasContext *ctx, arg_min *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_smin_tl);
+}
+
+static bool trans_max(DisasContext *ctx, arg_max *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_smax_tl);
+}
+
+static bool trans_minu(DisasContext *ctx, arg_minu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_umin_tl);
+}
+
+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_umax_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 81dfdfbafdc..93619846349 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -663,6 +663,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+sext_b 011000 000100 ..... 001 ..... 0010011 @r2
+sext_h 011000 000101 ..... 001 ..... 0010011 @r2
+
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 5a4fc02f705..3d594e8cb40 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -95,6 +95,18 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
return gen_arith(ctx, a, tcg_gen_umax_tl);
}
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ext8s_tl);
+}
+
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ext16s_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 81dfdfbafdc..93619846349 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -663,6 +663,9 @@ vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+sext_b 011000 000100 ..... 001 ..... 0010011 @r2
+sext_h 011000 000101 ..... 001 ..... 0010011 @r2
+
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 5a4fc02f705..3d594e8cb40 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -95,6 +95,18 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
return gen_arith(ctx, a, tcg_gen_umax_tl);
}
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ext8s_tl);
+}
+
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ext16s_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Paolo Bonzini, Palmer Dabbelt
From: Frank Chang <frank.chang@sifive.com>
Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
interfaces for immediate shift instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
target/riscv/translate.c | 39 ++++++++++++++++++
2 files changed, 43 insertions(+), 50 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index bd93f634cf0..6e736c9d0d1 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -268,54 +268,17 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_shli_tl(t, t, a->shamt);
-
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
+ return gen_shifti(ctx, a, tcg_gen_shl_tl);
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_shri_tl(t, t, a->shamt);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
+ return gen_shifti(ctx, a, tcg_gen_shr_tl);
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_sari_tl(t, t, a->shamt);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
+ return gen_shifti(ctx, a, tcg_gen_sar_tl);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -377,16 +340,7 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64BIT(ctx);
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
-
- tcg_gen_shli_tl(source1, source1, a->shamt);
- tcg_gen_ext32s_tl(source1, source1);
- gen_set_gpr(a->rd, source1);
-
- tcg_temp_free(source1);
- return true;
+ return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5f1a3c694fe..292cf09932d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -652,6 +652,45 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
return cpu_ldl_code(env, pc);
}
+static bool gen_shifti(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_movi_tl(source2, a->shamt);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->shamt);
+
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
static void gen_ctz(TCGv ret, TCGv arg1)
{
tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Bin Meng,
Richard Henderson, Paolo Bonzini
From: Frank Chang <frank.chang@sifive.com>
Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
interfaces for immediate shift instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
target/riscv/translate.c | 39 ++++++++++++++++++
2 files changed, 43 insertions(+), 50 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index bd93f634cf0..6e736c9d0d1 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -268,54 +268,17 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_shli_tl(t, t, a->shamt);
-
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
+ return gen_shifti(ctx, a, tcg_gen_shl_tl);
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_shri_tl(t, t, a->shamt);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
+ return gen_shifti(ctx, a, tcg_gen_shr_tl);
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- if (a->shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- if (a->rd != 0) {
- TCGv t = tcg_temp_new();
- gen_get_gpr(t, a->rs1);
-
- tcg_gen_sari_tl(t, t, a->shamt);
- gen_set_gpr(a->rd, t);
- tcg_temp_free(t);
- } /* NOP otherwise */
- return true;
+ return gen_shifti(ctx, a, tcg_gen_sar_tl);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -377,16 +340,7 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64BIT(ctx);
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
-
- tcg_gen_shli_tl(source1, source1, a->shamt);
- tcg_gen_ext32s_tl(source1, source1);
- gen_set_gpr(a->rd, source1);
-
- tcg_temp_free(source1);
- return true;
+ return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5f1a3c694fe..292cf09932d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -652,6 +652,45 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
return cpu_ldl_code(env, pc);
}
+static bool gen_shifti(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_movi_tl(source2, a->shamt);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->shamt);
+
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
static void gen_ctz(TCGv ret, TCGv arg1)
{
tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 09/17] target/riscv: rvb: single-bit instructions
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 17 +++++
target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
target/riscv/translate.c | 61 ++++++++++++++++
3 files changed, 175 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 93619846349..433b601b934 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -676,6 +676,15 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
+bset 0010100 .......... 001 ..... 0110011 @r
+bclr 0100100 .......... 001 ..... 0110011 @r
+binv 0110100 .......... 001 ..... 0110011 @r
+bext 0100100 .......... 101 ..... 0110011 @r
+
+bseti 00101. ........... 001 ..... 0010011 @sh
+bclri 01001. ........... 001 ..... 0010011 @sh
+binvi 01101. ........... 001 ..... 0010011 @sh
+bexti 01001. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -684,3 +693,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
+bsetw 0010100 .......... 001 ..... 0111011 @r
+bclrw 0100100 .......... 001 ..... 0111011 @r
+binvw 0110100 .......... 001 ..... 0111011 @r
+bextw 0100100 .......... 101 ..... 0111011 @r
+
+bsetiw 0010100 .......... 001 ..... 0011011 @sh5
+bclriw 0100100 .......... 001 ..... 0011011 @sh5
+binviw 0110100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 3d594e8cb40..69e5af44a18 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
return gen_unary(ctx, a, tcg_gen_ext16s_tl);
}
+static bool trans_bset(DisasContext *ctx, arg_bset *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_bset);
+}
+
+static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_bset);
+}
+
+static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_bclr);
+}
+
+static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_bclr);
+}
+
+static bool trans_binv(DisasContext *ctx, arg_binv *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_binv);
+}
+
+static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_binv);
+}
+
+static bool trans_bext(DisasContext *ctx, arg_bext *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_bext);
+}
+
+static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_bext);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -141,3 +189,52 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packuw);
}
+
+static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_bset);
+}
+
+static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_bset);
+}
+
+static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_bclr);
+}
+
+static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_bclr);
+}
+
+static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_binv);
+}
+
+static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_binv);
+}
+
+static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_bext);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 292cf09932d..e12240d1255 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -571,6 +571,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_sbop_mask(TCGv ret, TCGv shamt)
+{
+ tcg_gen_movi_tl(ret, 1);
+ tcg_gen_shl_tl(ret, ret, shamt);
+}
+
+static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_or_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_andc_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_xor_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ tcg_gen_shr_tl(ret, arg1, shamt);
+ tcg_gen_andi_tl(ret, ret, 1);
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -673,6 +715,25 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
return true;
}
+static bool gen_shiftw(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 31);
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 09/17] target/riscv: rvb: single-bit instructions
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Kito Cheng, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 17 +++++
target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
target/riscv/translate.c | 61 ++++++++++++++++
3 files changed, 175 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 93619846349..433b601b934 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -676,6 +676,15 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
+bset 0010100 .......... 001 ..... 0110011 @r
+bclr 0100100 .......... 001 ..... 0110011 @r
+binv 0110100 .......... 001 ..... 0110011 @r
+bext 0100100 .......... 101 ..... 0110011 @r
+
+bseti 00101. ........... 001 ..... 0010011 @sh
+bclri 01001. ........... 001 ..... 0010011 @sh
+binvi 01101. ........... 001 ..... 0010011 @sh
+bexti 01001. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -684,3 +693,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
+bsetw 0010100 .......... 001 ..... 0111011 @r
+bclrw 0100100 .......... 001 ..... 0111011 @r
+binvw 0110100 .......... 001 ..... 0111011 @r
+bextw 0100100 .......... 101 ..... 0111011 @r
+
+bsetiw 0010100 .......... 001 ..... 0011011 @sh5
+bclriw 0100100 .......... 001 ..... 0011011 @sh5
+binviw 0110100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 3d594e8cb40..69e5af44a18 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
return gen_unary(ctx, a, tcg_gen_ext16s_tl);
}
+static bool trans_bset(DisasContext *ctx, arg_bset *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_bset);
+}
+
+static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_bset);
+}
+
+static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_bclr);
+}
+
+static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_bclr);
+}
+
+static bool trans_binv(DisasContext *ctx, arg_binv *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_binv);
+}
+
+static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_binv);
+}
+
+static bool trans_bext(DisasContext *ctx, arg_bext *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_bext);
+}
+
+static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_bext);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -141,3 +189,52 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packuw);
}
+
+static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_bset);
+}
+
+static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_bset);
+}
+
+static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_bclr);
+}
+
+static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_bclr);
+}
+
+static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_binv);
+}
+
+static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_binv);
+}
+
+static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_bext);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 292cf09932d..e12240d1255 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -571,6 +571,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_sbop_mask(TCGv ret, TCGv shamt)
+{
+ tcg_gen_movi_tl(ret, 1);
+ tcg_gen_shl_tl(ret, ret, shamt);
+}
+
+static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_or_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_andc_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_xor_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ tcg_gen_shr_tl(ret, arg1, shamt);
+ tcg_gen_andi_tl(ret, ret, 1);
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -673,6 +715,25 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
return true;
}
+static bool gen_shiftw(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 31);
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 10/17] target/riscv: rvb: shift ones
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 8 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++
target/riscv/translate.c | 14 +++++++
3 files changed, 74 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 433b601b934..6bc9bbae9e0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -680,11 +680,15 @@ bset 0010100 .......... 001 ..... 0110011 @r
bclr 0100100 .......... 001 ..... 0110011 @r
binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
+slo 0010000 .......... 001 ..... 0110011 @r
+sro 0010000 .......... 101 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
+sloi 00100. ........... 001 ..... 0010011 @sh
+sroi 00100. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -697,7 +701,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r
bclrw 0100100 .......... 001 ..... 0111011 @r
binvw 0110100 .......... 001 ..... 0111011 @r
bextw 0100100 .......... 101 ..... 0111011 @r
+slow 0010000 .......... 001 ..... 0111011 @r
+srow 0010000 .......... 101 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
binviw 0110100 .......... 001 ..... 0011011 @sh5
+sloiw 0010000 .......... 001 ..... 0011011 @sh5
+sroiw 0010000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 69e5af44a18..28640322c43 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
return gen_shifti(ctx, a, gen_bext);
}
+static bool trans_slo(DisasContext *ctx, arg_slo *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_slo);
+}
+
+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_slo);
+}
+
+static bool trans_sro(DisasContext *ctx, arg_sro *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_sro);
+}
+
+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_sro);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftw(ctx, a, gen_bext);
}
+
+static bool trans_slow(DisasContext *ctx, arg_slow *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_slo);
+}
+
+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_slo);
+}
+
+static bool trans_srow(DisasContext *ctx, arg_srow *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_sro);
+}
+
+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_sro);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e12240d1255..088cf9f7678 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
tcg_gen_andi_tl(ret, ret, 1);
}
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shl_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
+
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shr_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 10/17] target/riscv: rvb: shift ones
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 8 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++
target/riscv/translate.c | 14 +++++++
3 files changed, 74 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 433b601b934..6bc9bbae9e0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -680,11 +680,15 @@ bset 0010100 .......... 001 ..... 0110011 @r
bclr 0100100 .......... 001 ..... 0110011 @r
binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
+slo 0010000 .......... 001 ..... 0110011 @r
+sro 0010000 .......... 101 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
+sloi 00100. ........... 001 ..... 0010011 @sh
+sroi 00100. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -697,7 +701,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r
bclrw 0100100 .......... 001 ..... 0111011 @r
binvw 0110100 .......... 001 ..... 0111011 @r
bextw 0100100 .......... 101 ..... 0111011 @r
+slow 0010000 .......... 001 ..... 0111011 @r
+srow 0010000 .......... 101 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
binviw 0110100 .......... 001 ..... 0011011 @sh5
+sloiw 0010000 .......... 001 ..... 0011011 @sh5
+sroiw 0010000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 69e5af44a18..28640322c43 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
return gen_shifti(ctx, a, gen_bext);
}
+static bool trans_slo(DisasContext *ctx, arg_slo *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_slo);
+}
+
+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_slo);
+}
+
+static bool trans_sro(DisasContext *ctx, arg_sro *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_sro);
+}
+
+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_sro);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftw(ctx, a, gen_bext);
}
+
+static bool trans_slow(DisasContext *ctx, arg_slow *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_slo);
+}
+
+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_slo);
+}
+
+static bool trans_srow(DisasContext *ctx, arg_srow *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_sro);
+}
+
+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_sro);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e12240d1255..088cf9f7678 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
tcg_gen_andi_tl(ret, ret, 1);
}
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shl_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
+
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shr_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
target/riscv/translate.c | 36 +++++++++++++++++++++++
3 files changed, 81 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6bc9bbae9e0..71a9a182c01 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
+rori 01100. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
bextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
+rorw 0110000 .......... 101 ..... 0111011 @r
+rolw 0110000 .......... 001 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
+roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 28640322c43..429738db155 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
return gen_shifti(ctx, a, gen_sro);
}
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotl_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_sro);
}
+
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rolw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 088cf9f7678..c09b93f1b8a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
target/riscv/translate.c | 36 +++++++++++++++++++++++
3 files changed, 81 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6bc9bbae9e0..71a9a182c01 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
+rori 01100. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
bextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
+rorw 0110000 .......... 101 ..... 0111011 @r
+rolw 0110000 .......... 001 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
+roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 28640322c43..429738db155 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
return gen_shifti(ctx, a, gen_sro);
}
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, tcg_gen_rotr_tl);
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, tcg_gen_rotl_tl);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_sro);
}
+
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_rolw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 088cf9f7678..c09b93f1b8a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 12/17] target/riscv: rvb: generalized reverse
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/bitmanip_helper.c | 64 +++++++++++++++++++++++++
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvb.c.inc | 31 ++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 28 +++++++++++
6 files changed, 132 insertions(+)
create mode 100644 target/riscv/bitmanip_helper.c
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index 00000000000..c625adaded5
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -0,0 +1,64 @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg.h"
+
+static const uint64_t adjacent_masks[] = {
+ dup_const(MO_8, 0x55),
+ dup_const(MO_8, 0x33),
+ dup_const(MO_8, 0x0f),
+ dup_const(MO_16, 0xff),
+ dup_const(MO_32, 0xffff),
+ UINT32_MAX
+};
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x = do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c7267593c32..f81b8faf3bf 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -58,6 +58,10 @@ DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 71a9a182c01..6b5e276a9f7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -684,6 +684,7 @@ slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
+grev 0110100 .......... 101 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -692,6 +693,7 @@ bexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
+grevi 01101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -708,6 +710,7 @@ slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
+grevw 0110100 .......... 101 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -715,3 +718,4 @@ binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
+greviw 0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 429738db155..281e0ffae9a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -197,6 +197,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, tcg_gen_rotl_tl);
}
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_helper_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_grevi(ctx, a);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -329,3 +346,17 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftw(ctx, a, gen_rolw);
}
+
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_grevw);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index af6c3416b78..d5e0bc93ea9 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -16,6 +16,7 @@ riscv_ss.add(files(
'gdbstub.c',
'op_helper.c',
'vector_helper.c',
+ 'bitmanip_helper.c',
'translate.c',
))
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c09b93f1b8a..8deb05add42 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -627,6 +627,28 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_not_tl(ret, ret);
}
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2;
+
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt == (TARGET_LONG_BITS - 8)) {
+ /* rev8, byte swaps */
+ tcg_gen_bswap_tl(source1, source1);
+ } else {
+ source2 = tcg_temp_new();
+ tcg_gen_movi_tl(source2, a->shamt);
+ gen_helper_grev(source1, source1, source2);
+ tcg_temp_free(source2);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -699,6 +721,12 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free_i32(t2);
}
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_grev(ret, arg1, arg2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 12/17] target/riscv: rvb: generalized reverse
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Bin Meng,
Richard Henderson, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/bitmanip_helper.c | 64 +++++++++++++++++++++++++
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvb.c.inc | 31 ++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 28 +++++++++++
6 files changed, 132 insertions(+)
create mode 100644 target/riscv/bitmanip_helper.c
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index 00000000000..c625adaded5
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -0,0 +1,64 @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg.h"
+
+static const uint64_t adjacent_masks[] = {
+ dup_const(MO_8, 0x55),
+ dup_const(MO_8, 0x33),
+ dup_const(MO_8, 0x0f),
+ dup_const(MO_16, 0xff),
+ dup_const(MO_32, 0xffff),
+ UINT32_MAX
+};
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x = do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c7267593c32..f81b8faf3bf 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -58,6 +58,10 @@ DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 71a9a182c01..6b5e276a9f7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -684,6 +684,7 @@ slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
+grev 0110100 .......... 101 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -692,6 +693,7 @@ bexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
+grevi 01101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -708,6 +710,7 @@ slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
+grevw 0110100 .......... 101 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -715,3 +718,4 @@ binviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
+greviw 0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 429738db155..281e0ffae9a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -197,6 +197,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, tcg_gen_rotl_tl);
}
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_helper_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_grevi(ctx, a);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -329,3 +346,17 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftw(ctx, a, gen_rolw);
}
+
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_grevw);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index af6c3416b78..d5e0bc93ea9 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -16,6 +16,7 @@ riscv_ss.add(files(
'gdbstub.c',
'op_helper.c',
'vector_helper.c',
+ 'bitmanip_helper.c',
'translate.c',
))
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c09b93f1b8a..8deb05add42 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -627,6 +627,28 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_not_tl(ret, ret);
}
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2;
+
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt == (TARGET_LONG_BITS - 8)) {
+ /* rev8, byte swaps */
+ tcg_gen_bswap_tl(source1, source1);
+ } else {
+ source2 = tcg_temp_new();
+ tcg_gen_movi_tl(source2, a->shamt);
+ gen_helper_grev(source1, source1, source2);
+ tcg_temp_free(source2);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -699,6 +721,12 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free_i32(t2);
}
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_grev(ret, arg1, arg2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 13/17] target/riscv: rvb: generalized or-combine
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/bitmanip_helper.c | 26 +++++++++++++++++++++++++
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
target/riscv/translate.c | 6 ++++++
5 files changed, 64 insertions(+)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index c625adaded5..5b2f795d03a 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -62,3 +62,29 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
{
return do_grev(rs1, rs2, 32);
}
+
+static target_ulong do_gorc(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x |= do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f81b8faf3bf..415e37bc37a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -61,6 +61,8 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6b5e276a9f7..e6dab8dbbc1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -685,6 +685,7 @@ sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
+gorc 0010100 .......... 101 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -694,6 +695,7 @@ sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
+gorci 00101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -711,6 +713,7 @@ srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
+gorcw 0010100 .......... 101 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -719,3 +722,4 @@ sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
+gorciw 0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 281e0ffae9a..ec9f9d2ef24 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -214,6 +214,18 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
return gen_grevi(ctx, a);
}
+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_helper_gorc);
+}
+
+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_helper_gorc);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -360,3 +372,17 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_grevw);
}
+
+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_gorcw);
+}
+
+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_gorcw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8deb05add42..35d4d36eef8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -727,6 +727,12 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_grev(ret, arg1, arg2);
}
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_gorcw(ret, arg1, arg2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 13/17] target/riscv: rvb: generalized or-combine
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Bin Meng,
Richard Henderson, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/bitmanip_helper.c | 26 +++++++++++++++++++++++++
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
target/riscv/translate.c | 6 ++++++
5 files changed, 64 insertions(+)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index c625adaded5..5b2f795d03a 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -62,3 +62,29 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
{
return do_grev(rs1, rs2, 32);
}
+
+static target_ulong do_gorc(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x |= do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f81b8faf3bf..415e37bc37a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -61,6 +61,8 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6b5e276a9f7..e6dab8dbbc1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -685,6 +685,7 @@ sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
+gorc 0010100 .......... 101 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -694,6 +695,7 @@ sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
+gorci 00101. ........... 101 ..... 0010011 @sh
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -711,6 +713,7 @@ srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
+gorcw 0010100 .......... 101 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -719,3 +722,4 @@ sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
+gorciw 0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 281e0ffae9a..ec9f9d2ef24 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -214,6 +214,18 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
return gen_grevi(ctx, a);
}
+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, gen_helper_gorc);
+}
+
+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, gen_helper_gorc);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -360,3 +372,17 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_grevw);
}
+
+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, gen_gorcw);
+}
+
+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, gen_gorcw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8deb05add42..35d4d36eef8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -727,6 +727,12 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_grev(ret, arg1, arg2);
}
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_gorcw(ret, arg1, arg2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 14/17] target/riscv: rvb: address calculation
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 +++++
target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++
target/riscv/translate.c | 32 +++++++++++++++++++++++++
3 files changed, 62 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e6dab8dbbc1..287920ee9bf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -686,6 +686,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -714,6 +717,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index ec9f9d2ef24..b27114a068d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -226,6 +226,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
return gen_shifti(ctx, a, gen_helper_gorc);
}
+#define GEN_TRANS_SHADD(SHAMT) \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, gen_sh##SHAMT##add); \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -386,3 +397,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_gorcw);
}
+
+#define GEN_TRANS_SHADD_UW(SHAMT) \
+static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
+ arg_sh##SHAMT##add_uw *a) \
+{ \
+ REQUIRE_64BIT(ctx); \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
+}
+
+GEN_TRANS_SHADD_UW(1)
+GEN_TRANS_SHADD_UW(2)
+GEN_TRANS_SHADD_UW(3)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 35d4d36eef8..ae9b5f7a2e2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -649,6 +649,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
return true;
}
+#define GEN_SHADD(SHAMT) \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_shli_tl(t, arg1, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -733,6 +748,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_gorcw(ret, arg1, arg2);
}
+#define GEN_SHADD_UW(SHAMT) \
+static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_ext32u_tl(t, arg1); \
+ \
+ tcg_gen_shli_tl(t, t, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD_UW(1)
+GEN_SHADD_UW(2)
+GEN_SHADD_UW(3)
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 14/17] target/riscv: rvb: address calculation
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 +++++
target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++
target/riscv/translate.c | 32 +++++++++++++++++++++++++
3 files changed, 62 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e6dab8dbbc1..287920ee9bf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -686,6 +686,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -714,6 +717,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index ec9f9d2ef24..b27114a068d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -226,6 +226,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
return gen_shifti(ctx, a, gen_helper_gorc);
}
+#define GEN_TRANS_SHADD(SHAMT) \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, gen_sh##SHAMT##add); \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -386,3 +397,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_gorcw);
}
+
+#define GEN_TRANS_SHADD_UW(SHAMT) \
+static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
+ arg_sh##SHAMT##add_uw *a) \
+{ \
+ REQUIRE_64BIT(ctx); \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
+}
+
+GEN_TRANS_SHADD_UW(1)
+GEN_TRANS_SHADD_UW(2)
+GEN_TRANS_SHADD_UW(3)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 35d4d36eef8..ae9b5f7a2e2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -649,6 +649,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
return true;
}
+#define GEN_SHADD(SHAMT) \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_shli_tl(t, arg1, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -733,6 +748,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_gorcw(ret, arg1, arg2);
}
+#define GEN_SHADD_UW(SHAMT) \
+static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_ext32u_tl(t, arg1); \
+ \
+ tcg_gen_shli_tl(t, t, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD_UW(1)
+GEN_SHADD_UW(2)
+GEN_SHADD_UW(3)
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, Alistair Francis,
Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
target/riscv/translate.c | 6 ++++++
3 files changed, 35 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 287920ee9bf..f09f8d5faf7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -720,6 +720,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r
sh1add_uw 0010000 .......... 010 ..... 0111011 @r
sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
+add_uw 0000100 .......... 000 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -729,3 +730,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+
+slli_uw 00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b27114a068d..9e81f6e3de4 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -410,3 +410,29 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
GEN_TRANS_SHADD_UW(1)
GEN_TRANS_SHADD_UW(2)
GEN_TRANS_SHADD_UW(3)
+
+static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_add_uw);
+}
+
+static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+
+ TCGv source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt < 32) {
+ tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
+ } else {
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ae9b5f7a2e2..c6e87396142 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -765,6 +765,12 @@ GEN_SHADD_UW(1)
GEN_SHADD_UW(2)
GEN_SHADD_UW(3)
+static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_add_tl(ret, arg1, arg2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Bin Meng, Richard Henderson
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
target/riscv/translate.c | 6 ++++++
3 files changed, 35 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 287920ee9bf..f09f8d5faf7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -720,6 +720,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r
sh1add_uw 0010000 .......... 010 ..... 0111011 @r
sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
+add_uw 0000100 .......... 000 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -729,3 +730,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+
+slli_uw 00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b27114a068d..9e81f6e3de4 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -410,3 +410,29 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
GEN_TRANS_SHADD_UW(1)
GEN_TRANS_SHADD_UW(2)
GEN_TRANS_SHADD_UW(3)
+
+static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_add_uw);
+}
+
+static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+
+ TCGv source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt < 32) {
+ tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
+ } else {
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ae9b5f7a2e2..c6e87396142 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -765,6 +765,12 @@ GEN_SHADD_UW(1)
GEN_SHADD_UW(2)
GEN_SHADD_UW(3)
+static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_add_tl(ret, arg1, arg2);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Kito Cheng, Bin Meng, Palmer Dabbelt
From: Kito Cheng <kito.cheng@sifive.com>
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3191fd00822..1b3c5ba1480 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -486,6 +486,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_b) {
+ target_misa |= RVB;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -556,6 +559,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f95bcbd8e10..3cea62cd4c4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -284,6 +284,7 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
+ bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis, Bin Meng
From: Kito Cheng <kito.cheng@sifive.com>
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3191fd00822..1b3c5ba1480 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -486,6 +486,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_b) {
+ target_misa |= RVB;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -556,6 +559,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f95bcbd8e10..3cea62cd4c4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -284,6 +284,7 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
+ bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Bin Meng, Palmer Dabbelt
From: Frank Chang <frank.chang@sifive.com>
Default b-ext version is v0.93.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 23 +++++++++++++++++++++++
target/riscv/cpu.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3c5ba1480..32469f7c891 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,6 +127,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
env->priv_ver = priv_ver;
}
+static void set_bext_version(CPURISCVState *env, int bext_ver)
+{
+ env->bext_ver = bext_ver;
+}
+
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
@@ -385,6 +390,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
+ int bext_version = BEXT_VERSION_0_93_0;
int vext_version = VEXT_VERSION_0_07_1;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -409,6 +415,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
set_priv_version(env, priv_version);
+ set_bext_version(env, bext_version);
set_vext_version(env, vext_version);
if (cpu->cfg.mmu) {
@@ -488,6 +495,21 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (cpu->cfg.ext_b) {
target_misa |= RVB;
+
+ if (cpu->cfg.bext_spec) {
+ if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
+ bext_version = BEXT_VERSION_0_93_0;
+ } else {
+ error_setg(errp,
+ "Unsupported bitmanip spec version '%s'",
+ cpu->cfg.bext_spec);
+ return;
+ }
+ } else {
+ qemu_log("bitmanip version is not specified, "
+ "use the default value v0.93\n");
+ }
+ set_bext_version(env, bext_version);
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
@@ -566,6 +588,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3cea62cd4c4..b2cca778526 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -83,6 +83,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
+#define BEXT_VERSION_0_93_0 0x00009300
#define VEXT_VERSION_0_07_1 0x00000701
enum {
@@ -130,6 +131,7 @@ struct CPURISCVState {
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
+ target_ulong bext_ver;
target_ulong vext_ver;
target_ulong misa;
target_ulong misa_mask;
@@ -295,6 +297,7 @@ struct RISCVCPU {
char *priv_spec;
char *user_spec;
+ char *bext_spec;
char *vext_spec;
uint16_t vlen;
uint16_t elen;
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
@ 2021-05-05 16:06 ` frank.chang
0 siblings, 0 replies; 49+ messages in thread
From: frank.chang @ 2021-05-05 16:06 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Bin Meng
From: Frank Chang <frank.chang@sifive.com>
Default b-ext version is v0.93.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 23 +++++++++++++++++++++++
target/riscv/cpu.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3c5ba1480..32469f7c891 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,6 +127,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
env->priv_ver = priv_ver;
}
+static void set_bext_version(CPURISCVState *env, int bext_ver)
+{
+ env->bext_ver = bext_ver;
+}
+
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
@@ -385,6 +390,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
+ int bext_version = BEXT_VERSION_0_93_0;
int vext_version = VEXT_VERSION_0_07_1;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -409,6 +415,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
set_priv_version(env, priv_version);
+ set_bext_version(env, bext_version);
set_vext_version(env, vext_version);
if (cpu->cfg.mmu) {
@@ -488,6 +495,21 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (cpu->cfg.ext_b) {
target_misa |= RVB;
+
+ if (cpu->cfg.bext_spec) {
+ if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
+ bext_version = BEXT_VERSION_0_93_0;
+ } else {
+ error_setg(errp,
+ "Unsupported bitmanip spec version '%s'",
+ cpu->cfg.bext_spec);
+ return;
+ }
+ } else {
+ qemu_log("bitmanip version is not specified, "
+ "use the default value v0.93\n");
+ }
+ set_bext_version(env, bext_version);
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
@@ -566,6 +588,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3cea62cd4c4..b2cca778526 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -83,6 +83,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
+#define BEXT_VERSION_0_93_0 0x00009300
#define VEXT_VERSION_0_07_1 0x00000701
enum {
@@ -130,6 +131,7 @@ struct CPURISCVState {
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
+ target_ulong bext_ver;
target_ulong vext_ver;
target_ulong misa;
target_ulong misa_mask;
@@ -295,6 +297,7 @@ struct RISCVCPU {
char *priv_spec;
char *user_spec;
+ char *bext_spec;
char *vext_spec;
uint16_t vlen;
uint16_t elen;
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros
2021-05-05 16:06 ` frank.chang
@ 2021-05-06 2:04 ` Alistair Francis
-1 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-06 2:04 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:24 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 11 ++++++-
> target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++
> target/riscv/translate.c | 38 +++++++++++++++++++++
> 4 files changed, 93 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..f95bcbd8e10 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -67,6 +67,7 @@
> #define RVS RV('S')
> #define RVU RV('U')
> #define RVH RV('H')
> +#define RVB RV('B')
>
> /* S extension denotes that Supervisor mode exists, however it is possible
> to have a core that support S mode but does not have an MMU and there
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index f75642bb0d2..9a2ffab1504 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -41,6 +41,7 @@
> &i imm rs1 rd
> &j imm rd
> &r rd rs1 rs2
> +&r2 rd rs1
> &s imm rs1 rs2
> &u imm rd
> &shift shamt rs1 rd
> @@ -68,7 +69,7 @@
> @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
> @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
> @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
> +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
> @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
> @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
> @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
> @@ -657,3 +658,11 @@ vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> +
> +# *** RV32B Standard Extension ***
> +clz 011000 000000 ..... 001 ..... 0010011 @r2
> +ctz 011000 000001 ..... 001 ..... 0010011 @r2
> +
> +# *** RV64B Standard Extension (in addition to RV32B) ***
> +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> new file mode 100644
> index 00000000000..157b4e3c41d
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -0,0 +1,44 @@
> +/*
> + * RISC-V translation routines for the RVB Standard Extension.
> + *
> + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_clz(DisasContext *ctx, arg_clz *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_clz);
> +}
> +
> +static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_ctz);
> +}
> +
> +static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_clzw);
> +}
> +
> +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_ctzw);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e945352bca3..60fac0fe27e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -548,6 +548,19 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
> return true;
> }
>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_tl(ret, ret, 64);
> +}
> +
> +static void gen_clzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ext32u_tl(ret, arg1);
> + tcg_gen_clzi_tl(ret, ret, 64);
> + tcg_gen_subi_tl(ret, ret, 32);
> +}
> +
> static bool gen_arith(DisasContext *ctx, arg_r *a,
> void(*func)(TCGv, TCGv, TCGv))
> {
> @@ -593,6 +606,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> return cpu_ldl_code(env, pc);
> }
>
> +static void gen_ctz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static void gen_clz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static bool gen_unary(DisasContext *ctx, arg_r2 *a,
> + void(*func)(TCGv, TCGv))
> +{
> + TCGv source = tcg_temp_new();
> +
> + gen_get_gpr(source, a->rs1);
> +
> + (*func)(source, source);
> +
> + gen_set_gpr(a->rd, source);
> + tcg_temp_free(source);
> + return true;
> +}
> +
> /* Include insn module translation function */
> #include "insn_trans/trans_rvi.c.inc"
> #include "insn_trans/trans_rvm.c.inc"
> @@ -601,6 +638,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvd.c.inc"
> #include "insn_trans/trans_rvh.c.inc"
> #include "insn_trans/trans_rvv.c.inc"
> +#include "insn_trans/trans_rvb.c.inc"
> #include "insn_trans/trans_privileged.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros
@ 2021-05-06 2:04 ` Alistair Francis
0 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-06 2:04 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Richard Henderson, Alistair Francis, Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:24 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 11 ++++++-
> target/riscv/insn_trans/trans_rvb.c.inc | 44 +++++++++++++++++++++++++
> target/riscv/translate.c | 38 +++++++++++++++++++++
> 4 files changed, 93 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..f95bcbd8e10 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -67,6 +67,7 @@
> #define RVS RV('S')
> #define RVU RV('U')
> #define RVH RV('H')
> +#define RVB RV('B')
>
> /* S extension denotes that Supervisor mode exists, however it is possible
> to have a core that support S mode but does not have an MMU and there
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index f75642bb0d2..9a2ffab1504 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -41,6 +41,7 @@
> &i imm rs1 rd
> &j imm rd
> &r rd rs1 rs2
> +&r2 rd rs1
> &s imm rs1 rs2
> &u imm rd
> &shift shamt rs1 rd
> @@ -68,7 +69,7 @@
> @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
> @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
> @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
> -@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
> +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
> @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
> @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
> @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
> @@ -657,3 +658,11 @@ vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> +
> +# *** RV32B Standard Extension ***
> +clz 011000 000000 ..... 001 ..... 0010011 @r2
> +ctz 011000 000001 ..... 001 ..... 0010011 @r2
> +
> +# *** RV64B Standard Extension (in addition to RV32B) ***
> +clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> new file mode 100644
> index 00000000000..157b4e3c41d
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -0,0 +1,44 @@
> +/*
> + * RISC-V translation routines for the RVB Standard Extension.
> + *
> + * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
> + * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_clz(DisasContext *ctx, arg_clz *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_clz);
> +}
> +
> +static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_ctz);
> +}
> +
> +static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_clzw);
> +}
> +
> +static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, gen_ctzw);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e945352bca3..60fac0fe27e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -548,6 +548,19 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
> return true;
> }
>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_tl(ret, ret, 64);
> +}
> +
> +static void gen_clzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ext32u_tl(ret, arg1);
> + tcg_gen_clzi_tl(ret, ret, 64);
> + tcg_gen_subi_tl(ret, ret, 32);
> +}
> +
> static bool gen_arith(DisasContext *ctx, arg_r *a,
> void(*func)(TCGv, TCGv, TCGv))
> {
> @@ -593,6 +606,30 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> return cpu_ldl_code(env, pc);
> }
>
> +static void gen_ctz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static void gen_clz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> +static bool gen_unary(DisasContext *ctx, arg_r2 *a,
> + void(*func)(TCGv, TCGv))
> +{
> + TCGv source = tcg_temp_new();
> +
> + gen_get_gpr(source, a->rs1);
> +
> + (*func)(source, source);
> +
> + gen_set_gpr(a->rd, source);
> + tcg_temp_free(source);
> + return true;
> +}
> +
> /* Include insn module translation function */
> #include "insn_trans/trans_rvi.c.inc"
> #include "insn_trans/trans_rvm.c.inc"
> @@ -601,6 +638,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvd.c.inc"
> #include "insn_trans/trans_rvh.c.inc"
> #include "insn_trans/trans_rvv.c.inc"
> +#include "insn_trans/trans_rvb.c.inc"
> #include "insn_trans/trans_privileged.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
2021-05-05 16:06 ` frank.chang
@ 2021-05-10 7:23 ` Alistair Francis
-1 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-10 7:23 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Alistair Francis,
Paolo Bonzini, Palmer Dabbelt
On Thu, May 6, 2021 at 2:26 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
> interfaces for immediate shift instructions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
> target/riscv/translate.c | 39 ++++++++++++++++++
> 2 files changed, 43 insertions(+), 50 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index bd93f634cf0..6e736c9d0d1 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -268,54 +268,17 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
> }
> static bool trans_slli(DisasContext *ctx, arg_slli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shli_tl(t, t, a->shamt);
> -
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_shl_tl);
> }
>
> static bool trans_srli(DisasContext *ctx, arg_srli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shri_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_shr_tl);
> }
>
> static bool trans_srai(DisasContext *ctx, arg_srai *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_sari_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_sar_tl);
> }
>
> static bool trans_add(DisasContext *ctx, arg_add *a)
> @@ -377,16 +340,7 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
> static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> {
> REQUIRE_64BIT(ctx);
> - TCGv source1;
> - source1 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> -
> - tcg_gen_shli_tl(source1, source1, a->shamt);
> - tcg_gen_ext32s_tl(source1, source1);
> - gen_set_gpr(a->rd, source1);
> -
> - tcg_temp_free(source1);
> - return true;
> + return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
> }
>
> static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5f1a3c694fe..292cf09932d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -652,6 +652,45 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> return cpu_ldl_code(env, pc);
> }
>
> +static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> +
> + tcg_gen_movi_tl(source2, a->shamt);
> + (*func)(source1, source1, source2);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> +static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + (*func)(source1, source1, source2);
> + tcg_gen_ext32s_tl(source1, source1);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> static void gen_ctz(TCGv ret, TCGv arg1)
> {
> tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
@ 2021-05-10 7:23 ` Alistair Francis
0 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-10 7:23 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Richard Henderson, Alistair Francis, Paolo Bonzini,
Palmer Dabbelt
On Thu, May 6, 2021 at 2:26 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
> interfaces for immediate shift instructions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 54 ++-----------------------
> target/riscv/translate.c | 39 ++++++++++++++++++
> 2 files changed, 43 insertions(+), 50 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index bd93f634cf0..6e736c9d0d1 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -268,54 +268,17 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
> }
> static bool trans_slli(DisasContext *ctx, arg_slli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shli_tl(t, t, a->shamt);
> -
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_shl_tl);
> }
>
> static bool trans_srli(DisasContext *ctx, arg_srli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shri_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_shr_tl);
> }
>
> static bool trans_srai(DisasContext *ctx, arg_srai *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> - if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_sari_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> - } /* NOP otherwise */
> - return true;
> + return gen_shifti(ctx, a, tcg_gen_sar_tl);
> }
>
> static bool trans_add(DisasContext *ctx, arg_add *a)
> @@ -377,16 +340,7 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
> static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> {
> REQUIRE_64BIT(ctx);
> - TCGv source1;
> - source1 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> -
> - tcg_gen_shli_tl(source1, source1, a->shamt);
> - tcg_gen_ext32s_tl(source1, source1);
> - gen_set_gpr(a->rd, source1);
> -
> - tcg_temp_free(source1);
> - return true;
> + return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
> }
>
> static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5f1a3c694fe..292cf09932d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -652,6 +652,45 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> return cpu_ldl_code(env, pc);
> }
>
> +static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> +
> + tcg_gen_movi_tl(source2, a->shamt);
> + (*func)(source1, source1, source2);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> +static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + (*func)(source1, source1, source2);
> + tcg_gen_ext32s_tl(source1, source1);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> static void gen_ctz(TCGv ret, TCGv arg1)
> {
> tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 09/17] target/riscv: rvb: single-bit instructions
2021-05-05 16:06 ` frank.chang
@ 2021-05-10 7:24 ` Alistair Francis
-1 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-10 7:24 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:39 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 17 +++++
> target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
> target/riscv/translate.c | 61 ++++++++++++++++
> 3 files changed, 175 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 93619846349..433b601b934 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -676,6 +676,15 @@ min 0000101 .......... 100 ..... 0110011 @r
> minu 0000101 .......... 101 ..... 0110011 @r
> max 0000101 .......... 110 ..... 0110011 @r
> maxu 0000101 .......... 111 ..... 0110011 @r
> +bset 0010100 .......... 001 ..... 0110011 @r
> +bclr 0100100 .......... 001 ..... 0110011 @r
> +binv 0110100 .......... 001 ..... 0110011 @r
> +bext 0100100 .......... 101 ..... 0110011 @r
> +
> +bseti 00101. ........... 001 ..... 0010011 @sh
> +bclri 01001. ........... 001 ..... 0010011 @sh
> +binvi 01101. ........... 001 ..... 0010011 @sh
> +bexti 01001. ........... 101 ..... 0010011 @sh
>
> # *** RV64B Standard Extension (in addition to RV32B) ***
> clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> @@ -684,3 +693,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>
> packw 0000100 .......... 100 ..... 0111011 @r
> packuw 0100100 .......... 100 ..... 0111011 @r
> +bsetw 0010100 .......... 001 ..... 0111011 @r
> +bclrw 0100100 .......... 001 ..... 0111011 @r
> +binvw 0110100 .......... 001 ..... 0111011 @r
> +bextw 0100100 .......... 101 ..... 0111011 @r
> +
> +bsetiw 0010100 .......... 001 ..... 0011011 @sh5
> +bclriw 0100100 .......... 001 ..... 0011011 @sh5
> +binviw 0110100 .......... 001 ..... 0011011 @sh5
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 3d594e8cb40..69e5af44a18 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
> return gen_unary(ctx, a, tcg_gen_ext16s_tl);
> }
>
> +static bool trans_bset(DisasContext *ctx, arg_bset *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_binv(DisasContext *ctx, arg_binv *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_binv);
> +}
> +
> +static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_binv);
> +}
> +
> +static bool trans_bext(DisasContext *ctx, arg_bext *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_bext);
> +}
> +
> +static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_bext);
> +}
> +
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -141,3 +189,52 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
> REQUIRE_EXT(ctx, RVB);
> return gen_arith(ctx, a, gen_packuw);
> }
> +
> +static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_binv);
> +}
> +
> +static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_binv);
> +}
> +
> +static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_bext);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 292cf09932d..e12240d1255 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -571,6 +571,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_temp_free(t);
> }
>
> +static void gen_sbop_mask(TCGv ret, TCGv shamt)
> +{
> + tcg_gen_movi_tl(ret, 1);
> + tcg_gen_shl_tl(ret, ret, shamt);
> +}
> +
> +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_or_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_andc_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_xor_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + tcg_gen_shr_tl(ret, arg1, shamt);
> + tcg_gen_andi_tl(ret, ret, 1);
> +}
> +
> static void gen_ctzw(TCGv ret, TCGv arg1)
> {
> tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> @@ -673,6 +715,25 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> return true;
> }
>
> +static bool gen_shiftw(DisasContext *ctx, arg_r *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + gen_get_gpr(source2, a->rs2);
> +
> + tcg_gen_andi_tl(source2, source2, 31);
> + (*func)(source1, source1, source2);
> + tcg_gen_ext32s_tl(source1, source1);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> void(*func)(TCGv, TCGv, TCGv))
> {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 09/17] target/riscv: rvb: single-bit instructions
@ 2021-05-10 7:24 ` Alistair Francis
0 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-10 7:24 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Richard Henderson, Alistair Francis, Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:39 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 17 +++++
> target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++
> target/riscv/translate.c | 61 ++++++++++++++++
> 3 files changed, 175 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 93619846349..433b601b934 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -676,6 +676,15 @@ min 0000101 .......... 100 ..... 0110011 @r
> minu 0000101 .......... 101 ..... 0110011 @r
> max 0000101 .......... 110 ..... 0110011 @r
> maxu 0000101 .......... 111 ..... 0110011 @r
> +bset 0010100 .......... 001 ..... 0110011 @r
> +bclr 0100100 .......... 001 ..... 0110011 @r
> +binv 0110100 .......... 001 ..... 0110011 @r
> +bext 0100100 .......... 101 ..... 0110011 @r
> +
> +bseti 00101. ........... 001 ..... 0010011 @sh
> +bclri 01001. ........... 001 ..... 0010011 @sh
> +binvi 01101. ........... 001 ..... 0010011 @sh
> +bexti 01001. ........... 101 ..... 0010011 @sh
>
> # *** RV64B Standard Extension (in addition to RV32B) ***
> clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> @@ -684,3 +693,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
>
> packw 0000100 .......... 100 ..... 0111011 @r
> packuw 0100100 .......... 100 ..... 0111011 @r
> +bsetw 0010100 .......... 001 ..... 0111011 @r
> +bclrw 0100100 .......... 001 ..... 0111011 @r
> +binvw 0110100 .......... 001 ..... 0111011 @r
> +bextw 0100100 .......... 101 ..... 0111011 @r
> +
> +bsetiw 0010100 .......... 001 ..... 0011011 @sh5
> +bclriw 0100100 .......... 001 ..... 0011011 @sh5
> +binviw 0110100 .......... 001 ..... 0011011 @sh5
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 3d594e8cb40..69e5af44a18 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
> return gen_unary(ctx, a, tcg_gen_ext16s_tl);
> }
>
> +static bool trans_bset(DisasContext *ctx, arg_bset *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_binv(DisasContext *ctx, arg_binv *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_binv);
> +}
> +
> +static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_binv);
> +}
> +
> +static bool trans_bext(DisasContext *ctx, arg_bext *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_bext);
> +}
> +
> +static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_bext);
> +}
> +
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -141,3 +189,52 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
> REQUIRE_EXT(ctx, RVB);
> return gen_arith(ctx, a, gen_packuw);
> }
> +
> +static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_bset);
> +}
> +
> +static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_bclr);
> +}
> +
> +static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_binv);
> +}
> +
> +static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_binv);
> +}
> +
> +static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_bext);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 292cf09932d..e12240d1255 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -571,6 +571,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_temp_free(t);
> }
>
> +static void gen_sbop_mask(TCGv ret, TCGv shamt)
> +{
> + tcg_gen_movi_tl(ret, 1);
> + tcg_gen_shl_tl(ret, ret, shamt);
> +}
> +
> +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_or_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_andc_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_xor_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + tcg_gen_shr_tl(ret, arg1, shamt);
> + tcg_gen_andi_tl(ret, ret, 1);
> +}
> +
> static void gen_ctzw(TCGv ret, TCGv arg1)
> {
> tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> @@ -673,6 +715,25 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> return true;
> }
>
> +static bool gen_shiftw(DisasContext *ctx, arg_r *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + gen_get_gpr(source2, a->rs2);
> +
> + tcg_gen_andi_tl(source2, source2, 31);
> + (*func)(source1, source1, source2);
> + tcg_gen_ext32s_tl(source1, source1);
> +
> + gen_set_gpr(a->rd, source1);
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> + return true;
> +}
> +
> static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> void(*func)(TCGv, TCGv, TCGv))
> {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 10/17] target/riscv: rvb: shift ones
2021-05-05 16:06 ` frank.chang
@ 2021-05-10 7:26 ` Alistair Francis
-1 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-10 7:26 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:08 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 8 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++
> target/riscv/translate.c | 14 +++++++
> 3 files changed, 74 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 433b601b934..6bc9bbae9e0 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -680,11 +680,15 @@ bset 0010100 .......... 001 ..... 0110011 @r
> bclr 0100100 .......... 001 ..... 0110011 @r
> binv 0110100 .......... 001 ..... 0110011 @r
> bext 0100100 .......... 101 ..... 0110011 @r
> +slo 0010000 .......... 001 ..... 0110011 @r
> +sro 0010000 .......... 101 ..... 0110011 @r
>
> bseti 00101. ........... 001 ..... 0010011 @sh
> bclri 01001. ........... 001 ..... 0010011 @sh
> binvi 01101. ........... 001 ..... 0010011 @sh
> bexti 01001. ........... 101 ..... 0010011 @sh
> +sloi 00100. ........... 001 ..... 0010011 @sh
> +sroi 00100. ........... 101 ..... 0010011 @sh
>
> # *** RV64B Standard Extension (in addition to RV32B) ***
> clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> @@ -697,7 +701,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r
> bclrw 0100100 .......... 001 ..... 0111011 @r
> binvw 0110100 .......... 001 ..... 0111011 @r
> bextw 0100100 .......... 101 ..... 0111011 @r
> +slow 0010000 .......... 001 ..... 0111011 @r
> +srow 0010000 .......... 101 ..... 0111011 @r
>
> bsetiw 0010100 .......... 001 ..... 0011011 @sh5
> bclriw 0100100 .......... 001 ..... 0011011 @sh5
> binviw 0110100 .......... 001 ..... 0011011 @sh5
> +sloiw 0010000 .......... 001 ..... 0011011 @sh5
> +sroiw 0010000 .......... 101 ..... 0011011 @sh5
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 69e5af44a18..28640322c43 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
> return gen_shifti(ctx, a, gen_bext);
> }
>
> +static bool trans_slo(DisasContext *ctx, arg_slo *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_slo);
> +}
> +
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_slo);
> +}
> +
> +static bool trans_sro(DisasContext *ctx, arg_sro *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_sro);
> +}
> +
> +static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_sro);
> +}
> +
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
> REQUIRE_EXT(ctx, RVB);
> return gen_shiftw(ctx, a, gen_bext);
> }
> +
> +static bool trans_slow(DisasContext *ctx, arg_slow *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_slo);
> +}
> +
> +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_slo);
> +}
> +
> +static bool trans_srow(DisasContext *ctx, arg_srow *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_sro);
> +}
> +
> +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_sro);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e12240d1255..088cf9f7678 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
> tcg_gen_andi_tl(ret, ret, 1);
> }
>
> +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_not_tl(ret, arg1);
> + tcg_gen_shl_tl(ret, ret, arg2);
> + tcg_gen_not_tl(ret, ret);
> +}
> +
> +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_not_tl(ret, arg1);
> + tcg_gen_shr_tl(ret, ret, arg2);
> + tcg_gen_not_tl(ret, ret);
> +}
> +
> static void gen_ctzw(TCGv ret, TCGv arg1)
> {
> tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 10/17] target/riscv: rvb: shift ones
@ 2021-05-10 7:26 ` Alistair Francis
0 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-10 7:26 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Richard Henderson, Alistair Francis, Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:08 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 8 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 52 +++++++++++++++++++++++++
> target/riscv/translate.c | 14 +++++++
> 3 files changed, 74 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 433b601b934..6bc9bbae9e0 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -680,11 +680,15 @@ bset 0010100 .......... 001 ..... 0110011 @r
> bclr 0100100 .......... 001 ..... 0110011 @r
> binv 0110100 .......... 001 ..... 0110011 @r
> bext 0100100 .......... 101 ..... 0110011 @r
> +slo 0010000 .......... 001 ..... 0110011 @r
> +sro 0010000 .......... 101 ..... 0110011 @r
>
> bseti 00101. ........... 001 ..... 0010011 @sh
> bclri 01001. ........... 001 ..... 0010011 @sh
> binvi 01101. ........... 001 ..... 0010011 @sh
> bexti 01001. ........... 101 ..... 0010011 @sh
> +sloi 00100. ........... 001 ..... 0010011 @sh
> +sroi 00100. ........... 101 ..... 0010011 @sh
>
> # *** RV64B Standard Extension (in addition to RV32B) ***
> clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> @@ -697,7 +701,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r
> bclrw 0100100 .......... 001 ..... 0111011 @r
> binvw 0110100 .......... 001 ..... 0111011 @r
> bextw 0100100 .......... 101 ..... 0111011 @r
> +slow 0010000 .......... 001 ..... 0111011 @r
> +srow 0010000 .......... 101 ..... 0111011 @r
>
> bsetiw 0010100 .......... 001 ..... 0011011 @sh5
> bclriw 0100100 .......... 001 ..... 0011011 @sh5
> binviw 0110100 .......... 001 ..... 0011011 @sh5
> +sloiw 0010000 .......... 001 ..... 0011011 @sh5
> +sroiw 0010000 .......... 101 ..... 0011011 @sh5
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 69e5af44a18..28640322c43 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
> return gen_shifti(ctx, a, gen_bext);
> }
>
> +static bool trans_slo(DisasContext *ctx, arg_slo *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_slo);
> +}
> +
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_slo);
> +}
> +
> +static bool trans_sro(DisasContext *ctx, arg_sro *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, gen_sro);
> +}
> +
> +static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, gen_sro);
> +}
> +
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
> REQUIRE_EXT(ctx, RVB);
> return gen_shiftw(ctx, a, gen_bext);
> }
> +
> +static bool trans_slow(DisasContext *ctx, arg_slow *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_slo);
> +}
> +
> +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_slo);
> +}
> +
> +static bool trans_srow(DisasContext *ctx, arg_srow *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_sro);
> +}
> +
> +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_sro);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e12240d1255..088cf9f7678 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
> tcg_gen_andi_tl(ret, ret, 1);
> }
>
> +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_not_tl(ret, arg1);
> + tcg_gen_shl_tl(ret, ret, arg2);
> + tcg_gen_not_tl(ret, ret);
> +}
> +
> +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_not_tl(ret, arg1);
> + tcg_gen_shr_tl(ret, ret, arg2);
> + tcg_gen_not_tl(ret, ret);
> +}
> +
> static void gen_ctzw(TCGv ret, TCGv arg1)
> {
> tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
2021-05-05 16:06 ` frank.chang
@ 2021-05-20 7:11 ` Alistair Francis
-1 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-20 7:11 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:17 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 6 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
> target/riscv/translate.c | 36 +++++++++++++++++++++++
> 3 files changed, 81 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6bc9bbae9e0..71a9a182c01 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
> bext 0100100 .......... 101 ..... 0110011 @r
> slo 0010000 .......... 001 ..... 0110011 @r
> sro 0010000 .......... 101 ..... 0110011 @r
> +ror 0110000 .......... 101 ..... 0110011 @r
> +rol 0110000 .......... 001 ..... 0110011 @r
>
> bseti 00101. ........... 001 ..... 0010011 @sh
> bclri 01001. ........... 001 ..... 0010011 @sh
> @@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh
> bexti 01001. ........... 101 ..... 0010011 @sh
> sloi 00100. ........... 001 ..... 0010011 @sh
> sroi 00100. ........... 101 ..... 0010011 @sh
> +rori 01100. ........... 101 ..... 0010011 @sh
>
> # *** RV64B Standard Extension (in addition to RV32B) ***
> clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> @@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
> bextw 0100100 .......... 101 ..... 0111011 @r
> slow 0010000 .......... 001 ..... 0111011 @r
> srow 0010000 .......... 101 ..... 0111011 @r
> +rorw 0110000 .......... 101 ..... 0111011 @r
> +rolw 0110000 .......... 001 ..... 0111011 @r
>
> bsetiw 0010100 .......... 001 ..... 0011011 @sh5
> bclriw 0100100 .......... 001 ..... 0011011 @sh5
> binviw 0110100 .......... 001 ..... 0011011 @sh5
> sloiw 0010000 .......... 001 ..... 0011011 @sh5
> sroiw 0010000 .......... 101 ..... 0011011 @sh5
> +roriw 0110000 .......... 101 ..... 0011011 @sh5
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 28640322c43..429738db155 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
> return gen_shifti(ctx, a, gen_sro);
> }
>
> +static bool trans_ror(DisasContext *ctx, arg_ror *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, tcg_gen_rotr_tl);
> +}
> +
> +static bool trans_rori(DisasContext *ctx, arg_rori *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, tcg_gen_rotr_tl);
> +}
> +
> +static bool trans_rol(DisasContext *ctx, arg_rol *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, tcg_gen_rotl_tl);
> +}
> +
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
> REQUIRE_EXT(ctx, RVB);
> return gen_shiftiw(ctx, a, gen_sro);
> }
> +
> +static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_rorw);
> +}
> +
> +static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_rorw);
> +}
> +
> +static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_rolw);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 088cf9f7678..c09b93f1b8a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_temp_free(t);
> }
>
> +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + /* truncate to 32-bits */
> + tcg_gen_trunc_tl_i32(t1, arg1);
> + tcg_gen_trunc_tl_i32(t2, arg2);
> +
> + tcg_gen_rotr_i32(t1, t1, t2);
> +
> + /* sign-extend 64-bits */
> + tcg_gen_ext_i32_tl(ret, t1);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(t2);
> +}
> +
> +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + /* truncate to 32-bits */
> + tcg_gen_trunc_tl_i32(t1, arg1);
> + tcg_gen_trunc_tl_i32(t2, arg2);
> +
> + tcg_gen_rotl_i32(t1, t1, t2);
> +
> + /* sign-extend 64-bits */
> + tcg_gen_ext_i32_tl(ret, t1);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(t2);
> +}
> +
> static bool gen_arith(DisasContext *ctx, arg_r *a,
> void(*func)(TCGv, TCGv, TCGv))
> {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 11/17] target/riscv: rvb: rotate (left/right)
@ 2021-05-20 7:11 ` Alistair Francis
0 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-20 7:11 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Richard Henderson, Alistair Francis, Palmer Dabbelt, Kito Cheng
On Thu, May 6, 2021 at 2:17 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 6 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++++++++++++++++
> target/riscv/translate.c | 36 +++++++++++++++++++++++
> 3 files changed, 81 insertions(+)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6bc9bbae9e0..71a9a182c01 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -682,6 +682,8 @@ binv 0110100 .......... 001 ..... 0110011 @r
> bext 0100100 .......... 101 ..... 0110011 @r
> slo 0010000 .......... 001 ..... 0110011 @r
> sro 0010000 .......... 101 ..... 0110011 @r
> +ror 0110000 .......... 101 ..... 0110011 @r
> +rol 0110000 .......... 001 ..... 0110011 @r
>
> bseti 00101. ........... 001 ..... 0010011 @sh
> bclri 01001. ........... 001 ..... 0010011 @sh
> @@ -689,6 +691,7 @@ binvi 01101. ........... 001 ..... 0010011 @sh
> bexti 01001. ........... 101 ..... 0010011 @sh
> sloi 00100. ........... 001 ..... 0010011 @sh
> sroi 00100. ........... 101 ..... 0010011 @sh
> +rori 01100. ........... 101 ..... 0010011 @sh
>
> # *** RV64B Standard Extension (in addition to RV32B) ***
> clzw 0110000 00000 ..... 001 ..... 0011011 @r2
> @@ -703,9 +706,12 @@ binvw 0110100 .......... 001 ..... 0111011 @r
> bextw 0100100 .......... 101 ..... 0111011 @r
> slow 0010000 .......... 001 ..... 0111011 @r
> srow 0010000 .......... 101 ..... 0111011 @r
> +rorw 0110000 .......... 101 ..... 0111011 @r
> +rolw 0110000 .......... 001 ..... 0111011 @r
>
> bsetiw 0010100 .......... 001 ..... 0011011 @sh5
> bclriw 0100100 .......... 001 ..... 0011011 @sh5
> binviw 0110100 .......... 001 ..... 0011011 @sh5
> sloiw 0010000 .......... 001 ..... 0011011 @sh5
> sroiw 0010000 .......... 101 ..... 0011011 @sh5
> +roriw 0110000 .......... 101 ..... 0011011 @sh5
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 28640322c43..429738db155 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
> return gen_shifti(ctx, a, gen_sro);
> }
>
> +static bool trans_ror(DisasContext *ctx, arg_ror *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, tcg_gen_rotr_tl);
> +}
> +
> +static bool trans_rori(DisasContext *ctx, arg_rori *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shifti(ctx, a, tcg_gen_rotr_tl);
> +}
> +
> +static bool trans_rol(DisasContext *ctx, arg_rol *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shift(ctx, a, tcg_gen_rotl_tl);
> +}
> +
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
> REQUIRE_EXT(ctx, RVB);
> return gen_shiftiw(ctx, a, gen_sro);
> }
> +
> +static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_rorw);
> +}
> +
> +static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftiw(ctx, a, gen_rorw);
> +}
> +
> +static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, gen_rolw);
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 088cf9f7678..c09b93f1b8a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -663,6 +663,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> tcg_temp_free(t);
> }
>
> +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + /* truncate to 32-bits */
> + tcg_gen_trunc_tl_i32(t1, arg1);
> + tcg_gen_trunc_tl_i32(t2, arg2);
> +
> + tcg_gen_rotr_i32(t1, t1, t2);
> +
> + /* sign-extend 64-bits */
> + tcg_gen_ext_i32_tl(ret, t1);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(t2);
> +}
> +
> +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + /* truncate to 32-bits */
> + tcg_gen_trunc_tl_i32(t1, arg1);
> + tcg_gen_trunc_tl_i32(t2, arg2);
> +
> + tcg_gen_rotl_i32(t1, t1, t2);
> +
> + /* sign-extend 64-bits */
> + tcg_gen_ext_i32_tl(ret, t1);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(t2);
> +}
> +
> static bool gen_arith(DisasContext *ctx, arg_r *a,
> void(*func)(TCGv, TCGv, TCGv))
> {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
2021-05-05 16:06 ` frank.chang
@ 2021-05-27 22:05 ` Alistair Francis
-1 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-27 22:05 UTC (permalink / raw)
To: Frank Chang
Cc: Alistair Francis, Palmer Dabbelt, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Thu, May 6, 2021 at 2:27 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Default b-ext version is v0.93.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 23 +++++++++++++++++++++++
> target/riscv/cpu.h | 3 +++
> 2 files changed, 26 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1b3c5ba1480..32469f7c891 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -127,6 +127,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
> env->priv_ver = priv_ver;
> }
>
> +static void set_bext_version(CPURISCVState *env, int bext_ver)
> +{
> + env->bext_ver = bext_ver;
> +}
> +
> static void set_vext_version(CPURISCVState *env, int vext_ver)
> {
> env->vext_ver = vext_ver;
> @@ -385,6 +390,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> int priv_version = PRIV_VERSION_1_11_0;
> + int bext_version = BEXT_VERSION_0_93_0;
> int vext_version = VEXT_VERSION_0_07_1;
> target_ulong target_misa = env->misa;
> Error *local_err = NULL;
> @@ -409,6 +415,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
>
> set_priv_version(env, priv_version);
> + set_bext_version(env, bext_version);
> set_vext_version(env, vext_version);
>
> if (cpu->cfg.mmu) {
> @@ -488,6 +495,21 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
> if (cpu->cfg.ext_b) {
> target_misa |= RVB;
> +
> + if (cpu->cfg.bext_spec) {
> + if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
> + bext_version = BEXT_VERSION_0_93_0;
> + } else {
> + error_setg(errp,
> + "Unsupported bitmanip spec version '%s'",
> + cpu->cfg.bext_spec);
> + return;
> + }
> + } else {
> + qemu_log("bitmanip version is not specified, "
> + "use the default value v0.93\n");
> + }
> + set_bext_version(env, bext_version);
> }
> if (cpu->cfg.ext_v) {
> target_misa |= RVV;
> @@ -566,6 +588,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> + DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3cea62cd4c4..b2cca778526 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -83,6 +83,7 @@ enum {
> #define PRIV_VERSION_1_10_0 0x00011000
> #define PRIV_VERSION_1_11_0 0x00011100
>
> +#define BEXT_VERSION_0_93_0 0x00009300
> #define VEXT_VERSION_0_07_1 0x00000701
>
> enum {
> @@ -130,6 +131,7 @@ struct CPURISCVState {
> target_ulong guest_phys_fault_addr;
>
> target_ulong priv_ver;
> + target_ulong bext_ver;
> target_ulong vext_ver;
> target_ulong misa;
> target_ulong misa_mask;
> @@ -295,6 +297,7 @@ struct RISCVCPU {
>
> char *priv_spec;
> char *user_spec;
> + char *bext_spec;
> char *vext_spec;
> uint16_t vlen;
> uint16_t elen;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
@ 2021-05-27 22:05 ` Alistair Francis
0 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-27 22:05 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Bin Meng, Palmer Dabbelt
On Thu, May 6, 2021 at 2:27 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Default b-ext version is v0.93.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 23 +++++++++++++++++++++++
> target/riscv/cpu.h | 3 +++
> 2 files changed, 26 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1b3c5ba1480..32469f7c891 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -127,6 +127,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
> env->priv_ver = priv_ver;
> }
>
> +static void set_bext_version(CPURISCVState *env, int bext_ver)
> +{
> + env->bext_ver = bext_ver;
> +}
> +
> static void set_vext_version(CPURISCVState *env, int vext_ver)
> {
> env->vext_ver = vext_ver;
> @@ -385,6 +390,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> int priv_version = PRIV_VERSION_1_11_0;
> + int bext_version = BEXT_VERSION_0_93_0;
> int vext_version = VEXT_VERSION_0_07_1;
> target_ulong target_misa = env->misa;
> Error *local_err = NULL;
> @@ -409,6 +415,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
>
> set_priv_version(env, priv_version);
> + set_bext_version(env, bext_version);
> set_vext_version(env, vext_version);
>
> if (cpu->cfg.mmu) {
> @@ -488,6 +495,21 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
> if (cpu->cfg.ext_b) {
> target_misa |= RVB;
> +
> + if (cpu->cfg.bext_spec) {
> + if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
> + bext_version = BEXT_VERSION_0_93_0;
> + } else {
> + error_setg(errp,
> + "Unsupported bitmanip spec version '%s'",
> + cpu->cfg.bext_spec);
> + return;
> + }
> + } else {
> + qemu_log("bitmanip version is not specified, "
> + "use the default value v0.93\n");
> + }
> + set_bext_version(env, bext_version);
> }
> if (cpu->cfg.ext_v) {
> target_misa |= RVV;
> @@ -566,6 +588,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> + DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3cea62cd4c4..b2cca778526 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -83,6 +83,7 @@ enum {
> #define PRIV_VERSION_1_10_0 0x00011000
> #define PRIV_VERSION_1_11_0 0x00011100
>
> +#define BEXT_VERSION_0_93_0 0x00009300
> #define VEXT_VERSION_0_07_1 0x00000701
>
> enum {
> @@ -130,6 +131,7 @@ struct CPURISCVState {
> target_ulong guest_phys_fault_addr;
>
> target_ulong priv_ver;
> + target_ulong bext_ver;
> target_ulong vext_ver;
> target_ulong misa;
> target_ulong misa_mask;
> @@ -295,6 +297,7 @@ struct RISCVCPU {
>
> char *priv_spec;
> char *user_spec;
> + char *bext_spec;
> char *vext_spec;
> uint16_t vlen;
> uint16_t elen;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 00/17] support subsets of bitmanip extension
2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
@ 2021-05-27 22:08 ` Alistair Francis
2021-05-05 16:06 ` frank.chang
` (16 subsequent siblings)
17 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-27 22:08 UTC (permalink / raw)
To: Frank Chang; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Thu, May 6, 2021 at 2:11 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and
> Zbs subset instructions. Some Zbp instructions are also implemented as
> they have similar behavior with their Zba-, Zbb- and Zbs-family
> instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
>
> Specification:
> https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf
>
> The port is available here:
> https://github.com/sifive/qemu/tree/rvb-upstream-v6
>
> To test rvb implementation, specify cpu argument with 'x-b=true' or
> 'x-b=true,bext_spec=v0.93'to enable B-extension support.
>
> Changelog:
>
> v6:
> * rebase riscv-to-apply.next branch.
> * remove all #ifdef TARGET_RISCV64 macros.
>
> v5:
> * add bext_spec cpu option, default set to v0.93.
> * rebase master branch.
>
> v4:
> * Remove 'rd != 0' checks from immediate shift instructions.
>
> v3:
> * Convert existing immediate shift instructions to use gen_shifti()
> and gen_shiftiw() interfaces.
> * Rename *u.w instructions to *.uw.
> * Rename sb* instructions to b*.
> * Rename pcnt* instructions to cpop*.
>
> v2:
> * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions.
> * Remove addwu, subwu and addiwu instructions as they are not longer
> exist in latest draft.
> * Optimize implementation with cleaner tcg ops.
>
> Frank Chang (6):
> target/riscv: rvb: count bits set
> target/riscv: add gen_shifti() and gen_shiftiw() helper functions
> target/riscv: rvb: single-bit instructions
> target/riscv: rvb: generalized reverse
> target/riscv: rvb: generalized or-combine
> target/riscv: rvb: add b-ext version cpu option
>
> Kito Cheng (11):
> target/riscv: reformat @sh format encoding for B-extension
> target/riscv: rvb: count leading/trailing zeros
> target/riscv: rvb: logic-with-negate
> target/riscv: rvb: pack two words into one register
> target/riscv: rvb: min/max instructions
> target/riscv: rvb: sign-extend instructions
> target/riscv: rvb: shift ones
> target/riscv: rvb: rotate (left/right)
> target/riscv: rvb: address calculation
> target/riscv: rvb: add/shift with prefix zero-extend
> target/riscv: rvb: support and turn on B-extension from command line
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/bitmanip_helper.c | 90 +++++
> target/riscv/cpu.c | 27 ++
> target/riscv/cpu.h | 5 +
> target/riscv/helper.h | 6 +
> target/riscv/insn32.decode | 87 ++++-
> target/riscv/insn_trans/trans_rvb.c.inc | 438 ++++++++++++++++++++++++
> target/riscv/insn_trans/trans_rvi.c.inc | 54 +--
> target/riscv/meson.build | 1 +
> target/riscv/translate.c | 306 +++++++++++++++++
> 9 files changed, 958 insertions(+), 56 deletions(-)
> create mode 100644 target/riscv/bitmanip_helper.c
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v6 00/17] support subsets of bitmanip extension
@ 2021-05-27 22:08 ` Alistair Francis
0 siblings, 0 replies; 49+ messages in thread
From: Alistair Francis @ 2021-05-27 22:08 UTC (permalink / raw)
To: Frank Chang; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Thu, May 6, 2021 at 2:11 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and
> Zbs subset instructions. Some Zbp instructions are also implemented as
> they have similar behavior with their Zba-, Zbb- and Zbs-family
> instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
>
> Specification:
> https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf
>
> The port is available here:
> https://github.com/sifive/qemu/tree/rvb-upstream-v6
>
> To test rvb implementation, specify cpu argument with 'x-b=true' or
> 'x-b=true,bext_spec=v0.93'to enable B-extension support.
>
> Changelog:
>
> v6:
> * rebase riscv-to-apply.next branch.
> * remove all #ifdef TARGET_RISCV64 macros.
>
> v5:
> * add bext_spec cpu option, default set to v0.93.
> * rebase master branch.
>
> v4:
> * Remove 'rd != 0' checks from immediate shift instructions.
>
> v3:
> * Convert existing immediate shift instructions to use gen_shifti()
> and gen_shiftiw() interfaces.
> * Rename *u.w instructions to *.uw.
> * Rename sb* instructions to b*.
> * Rename pcnt* instructions to cpop*.
>
> v2:
> * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions.
> * Remove addwu, subwu and addiwu instructions as they are not longer
> exist in latest draft.
> * Optimize implementation with cleaner tcg ops.
>
> Frank Chang (6):
> target/riscv: rvb: count bits set
> target/riscv: add gen_shifti() and gen_shiftiw() helper functions
> target/riscv: rvb: single-bit instructions
> target/riscv: rvb: generalized reverse
> target/riscv: rvb: generalized or-combine
> target/riscv: rvb: add b-ext version cpu option
>
> Kito Cheng (11):
> target/riscv: reformat @sh format encoding for B-extension
> target/riscv: rvb: count leading/trailing zeros
> target/riscv: rvb: logic-with-negate
> target/riscv: rvb: pack two words into one register
> target/riscv: rvb: min/max instructions
> target/riscv: rvb: sign-extend instructions
> target/riscv: rvb: shift ones
> target/riscv: rvb: rotate (left/right)
> target/riscv: rvb: address calculation
> target/riscv: rvb: add/shift with prefix zero-extend
> target/riscv: rvb: support and turn on B-extension from command line
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/bitmanip_helper.c | 90 +++++
> target/riscv/cpu.c | 27 ++
> target/riscv/cpu.h | 5 +
> target/riscv/helper.h | 6 +
> target/riscv/insn32.decode | 87 ++++-
> target/riscv/insn_trans/trans_rvb.c.inc | 438 ++++++++++++++++++++++++
> target/riscv/insn_trans/trans_rvi.c.inc | 54 +--
> target/riscv/meson.build | 1 +
> target/riscv/translate.c | 306 +++++++++++++++++
> 9 files changed, 958 insertions(+), 56 deletions(-)
> create mode 100644 target/riscv/bitmanip_helper.c
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2021-05-27 22:10 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
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2021-05-05 16:06 [PATCH v6 00/17] support subsets of bitmanip extension frank.chang
2021-05-05 16:06 ` [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-06 2:04 ` Alistair Francis
2021-05-06 2:04 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 03/17] target/riscv: rvb: count bits set frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 04/17] target/riscv: rvb: logic-with-negate frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 05/17] target/riscv: rvb: pack two words into one register frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 06/17] target/riscv: rvb: min/max instructions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-10 7:23 ` Alistair Francis
2021-05-10 7:23 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 09/17] target/riscv: rvb: single-bit instructions frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-10 7:24 ` Alistair Francis
2021-05-10 7:24 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 10/17] target/riscv: rvb: shift ones frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-10 7:26 ` Alistair Francis
2021-05-10 7:26 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 11/17] target/riscv: rvb: rotate (left/right) frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-20 7:11 ` Alistair Francis
2021-05-20 7:11 ` Alistair Francis
2021-05-05 16:06 ` [PATCH v6 12/17] target/riscv: rvb: generalized reverse frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 13/17] target/riscv: rvb: generalized or-combine frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 14/17] target/riscv: rvb: address calculation frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-05 16:06 ` [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang
2021-05-05 16:06 ` frank.chang
2021-05-27 22:05 ` Alistair Francis
2021-05-27 22:05 ` Alistair Francis
2021-05-27 22:08 ` [PATCH v6 00/17] support subsets of bitmanip extension Alistair Francis
2021-05-27 22:08 ` Alistair Francis
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