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From: Vignesh Raghavendra <vigneshr@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>
Cc: "Rob Herring" <robh+dt@kernel.org>,
	"Péter Ujfalusi" <peter.ujfalusi@gmail.com>,
	devicetree@vger.kernel.org,
	"Linux ARM Mailing List" <linux-arm-kernel@lists.infradead.org>,
	linux-kernel@vger.kernel.org,
	"Vignesh Raghavendra" <vigneshr@ti.com>
Subject: [PATCH v2] arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent
Date: Mon, 10 May 2021 23:36:01 +0530	[thread overview]
Message-ID: <20210510180601.19458-1-vigneshr@ti.com> (raw)

Traffic through main NAVSS interconnect is coherent wrt ARM caches on
J7200 SoC.  Add missing dma-coherent property to main_navss node.

Also add dma-ranges to be consistent with mcu_navss node
and with AM65/J721e main_navss and mcu_navss nodes.

Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
---

v2:
Pick up Reviewed-by and update commit msg as suggested by Peter
v1: https://lore.kernel.org/r/20210427175130.29451-1-vigneshr@ti.com

 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index f86c493a44f1..a6826f1888ef 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -85,6 +85,8 @@ main_navss: bus@30000000 {
 		#size-cells = <2>;
 		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 		ti,sci-dev-id = <199>;
+		dma-coherent;
+		dma-ranges;
 
 		main_navss_intr: interrupt-controller1 {
 			compatible = "ti,sci-intr";
-- 
2.31.1


WARNING: multiple messages have this Message-ID (diff)
From: Vignesh Raghavendra <vigneshr@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>
Cc: "Rob Herring" <robh+dt@kernel.org>,
	"Péter Ujfalusi" <peter.ujfalusi@gmail.com>,
	devicetree@vger.kernel.org,
	"Linux ARM Mailing List" <linux-arm-kernel@lists.infradead.org>,
	linux-kernel@vger.kernel.org,
	"Vignesh Raghavendra" <vigneshr@ti.com>
Subject: [PATCH v2] arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent
Date: Mon, 10 May 2021 23:36:01 +0530	[thread overview]
Message-ID: <20210510180601.19458-1-vigneshr@ti.com> (raw)

Traffic through main NAVSS interconnect is coherent wrt ARM caches on
J7200 SoC.  Add missing dma-coherent property to main_navss node.

Also add dma-ranges to be consistent with mcu_navss node
and with AM65/J721e main_navss and mcu_navss nodes.

Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
---

v2:
Pick up Reviewed-by and update commit msg as suggested by Peter
v1: https://lore.kernel.org/r/20210427175130.29451-1-vigneshr@ti.com

 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index f86c493a44f1..a6826f1888ef 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -85,6 +85,8 @@ main_navss: bus@30000000 {
 		#size-cells = <2>;
 		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 		ti,sci-dev-id = <199>;
+		dma-coherent;
+		dma-ranges;
 
 		main_navss_intr: interrupt-controller1 {
 			compatible = "ti,sci-intr";
-- 
2.31.1


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             reply	other threads:[~2021-05-10 18:06 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-10 18:06 Vignesh Raghavendra [this message]
2021-05-10 18:06 ` [PATCH v2] arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent Vignesh Raghavendra
2021-05-14 17:51 ` Nishanth Menon
2021-05-14 17:51   ` Nishanth Menon

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