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From: Andrew Morton <akpm@linux-foundation.org>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: linux-mm@kvack.org, mpe@ellerman.id.au,
	linuxppc-dev@lists.ozlabs.org, kaleshsingh@google.com,
	npiggin@gmail.com, joel@joelfernandes.org,
	Christophe Leroy <christophe.leroy@csgroup.eu>
Subject: Re: [PATCH v5 9/9] powerpc/mm: Enable move pmd/pud
Date: Tue, 11 May 2021 15:19:49 -0700	[thread overview]
Message-ID: <20210511151949.fa1973124f3aba1ea7abceb9@linux-foundation.org> (raw)
In-Reply-To: <20210422054323.150993-10-aneesh.kumar@linux.ibm.com>

On Thu, 22 Apr 2021 11:13:23 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> wrote:

> mremap HAVE_MOVE_PMD/PUD optimization time comparison for 1GB region:
> 1GB mremap - Source PTE-aligned, Destination PTE-aligned
>   mremap time:      1127034ns
> 1GB mremap - Source PMD-aligned, Destination PMD-aligned
>   mremap time:       508817ns
> 1GB mremap - Source PUD-aligned, Destination PUD-aligned
>   mremap time:        23046ns

Well that's nice.

How significant is this in practice?  How common is it for applications
to successfully align the region?  Do real-world applications actually
benefit from this?

Are there userspace libraries (malloc() etc) which should be reworked
to fully exploit this?


WARNING: multiple messages have this Message-ID (diff)
From: Andrew Morton <akpm@linux-foundation.org>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: npiggin@gmail.com, linux-mm@kvack.org, kaleshsingh@google.com,
	joel@joelfernandes.org, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v5 9/9] powerpc/mm: Enable move pmd/pud
Date: Tue, 11 May 2021 15:19:49 -0700	[thread overview]
Message-ID: <20210511151949.fa1973124f3aba1ea7abceb9@linux-foundation.org> (raw)
In-Reply-To: <20210422054323.150993-10-aneesh.kumar@linux.ibm.com>

On Thu, 22 Apr 2021 11:13:23 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> wrote:

> mremap HAVE_MOVE_PMD/PUD optimization time comparison for 1GB region:
> 1GB mremap - Source PTE-aligned, Destination PTE-aligned
>   mremap time:      1127034ns
> 1GB mremap - Source PMD-aligned, Destination PMD-aligned
>   mremap time:       508817ns
> 1GB mremap - Source PUD-aligned, Destination PUD-aligned
>   mremap time:        23046ns

Well that's nice.

How significant is this in practice?  How common is it for applications
to successfully align the region?  Do real-world applications actually
benefit from this?

Are there userspace libraries (malloc() etc) which should be reworked
to fully exploit this?

  reply	other threads:[~2021-05-11 22:19 UTC|newest]

Thread overview: 106+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-22  5:43 [PATCH v5 0/9] Speedup mremap on ppc64 Aneesh Kumar K.V
2021-04-22  5:43 ` Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 1/9] selftest/mremap_test: Update the test to handle pagesize other than 4K Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 2/9] selftest/mremap_test: Avoid crash with static build Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 3/9] mm/mremap: Use pmd/pud_poplulate to update page table entries Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-05-18 20:04   ` Nathan Chancellor
2021-05-18 20:04     ` Nathan Chancellor
2021-05-19  4:46     ` Aneesh Kumar K.V
2021-05-19  4:46       ` Aneesh Kumar K.V
2021-05-19 18:02       ` Nathan Chancellor
2021-05-19 18:02         ` Nathan Chancellor
2021-05-20  2:18       ` Peter Xu
2021-05-20  2:18         ` Peter Xu
2021-05-20  8:26         ` Aneesh Kumar K.V
2021-05-20  8:26           ` Aneesh Kumar K.V
2021-05-20 12:46           ` Peter Xu
2021-05-20 12:46             ` Peter Xu
2021-05-20 13:23             ` Aneesh Kumar K.V
2021-05-20 13:23               ` Aneesh Kumar K.V
2021-05-20 13:37               ` Aneesh Kumar K.V
2021-05-20 13:37                 ` Aneesh Kumar K.V
2021-05-20 14:57                 ` Peter Xu
2021-05-20 14:57                   ` Peter Xu
2021-05-20 19:06                   ` Zi Yan
2021-05-20 19:06                     ` Zi Yan
2021-05-20 20:01                     ` Peter Xu
2021-05-20 20:01                       ` Peter Xu
2021-05-20 20:25                       ` Kalesh Singh
2021-05-20 20:25                         ` Kalesh Singh
2021-04-22  5:43 ` [PATCH v5 4/9] powerpc/mm/book3s64: Fix possible build error Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-05-15 16:35   ` Guenter Roeck
2021-05-15 16:35     ` Guenter Roeck
2021-05-15 20:41     ` Andrew Morton
2021-05-15 20:41       ` Andrew Morton
2021-05-15 23:05       ` Guenter Roeck
2021-05-15 23:05         ` Guenter Roeck
2021-05-17  8:40     ` Aneesh Kumar K.V
2021-05-17  8:40       ` Aneesh Kumar K.V
2021-05-17 13:38       ` Guenter Roeck
2021-05-17 13:38         ` Guenter Roeck
2021-05-17 13:55         ` Aneesh Kumar K.V
2021-05-17 13:55           ` Aneesh Kumar K.V
2021-05-17 14:18           ` Guenter Roeck
2021-05-17 14:18             ` Guenter Roeck
2021-05-19  0:26             ` Michael Ellerman
2021-05-19  0:26               ` Michael Ellerman
2021-05-19  0:45               ` Segher Boessenkool
2021-05-19  0:45                 ` Segher Boessenkool
2021-05-19 12:03                 ` Segher Boessenkool
2021-05-19 13:37                   ` Guenter Roeck
2021-05-19 14:20                     ` Segher Boessenkool
2021-05-19 14:20                       ` Segher Boessenkool
2021-05-19 15:28                       ` Guenter Roeck
2021-05-19 15:28                         ` Guenter Roeck
2021-05-20  7:37                   ` Michael Ellerman
2021-05-20 12:17                     ` Segher Boessenkool
2021-05-19  1:08               ` Guenter Roeck
2021-05-19  1:08                 ` Guenter Roeck
2021-05-20 11:38                 ` Michael Ellerman
2021-05-20 11:38                   ` Michael Ellerman
2021-05-20 11:56                   ` Guenter Roeck
2021-05-20 11:56                     ` Guenter Roeck
2021-04-22  5:43 ` [PATCH v5 6/9] mm/mremap: Use range flush that does TLB and page walk cache flush Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 7/9] mm/mremap: Move TLB flush outside page table lock Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-05-20 15:26   ` Aneesh Kumar K.V
2021-05-20 15:26     ` Aneesh Kumar K.V
2021-05-20 16:57     ` Aneesh Kumar K.V
2021-05-20 16:57       ` Aneesh Kumar K.V
2021-05-21  2:40       ` Linus Torvalds
2021-05-21  2:40         ` Linus Torvalds
2021-05-21  3:03         ` Aneesh Kumar K.V
2021-05-21  3:03           ` Aneesh Kumar K.V
2021-05-21  3:28           ` Aneesh Kumar K.V
2021-05-21  3:28             ` Aneesh Kumar K.V
2021-05-21  6:13           ` Linus Torvalds
2021-05-21  6:13             ` Linus Torvalds
2021-05-21 12:50             ` Aneesh Kumar K.V
2021-05-21 12:50               ` Aneesh Kumar K.V
2021-05-21 13:03               ` Aneesh Kumar K.V
2021-05-21 13:03                 ` Aneesh Kumar K.V
2021-05-21 16:03                 ` Linus Torvalds
2021-05-21 16:03                   ` Linus Torvalds
2021-05-21 16:29                   ` Aneesh Kumar K.V
2021-05-21 16:29                     ` Aneesh Kumar K.V
2021-05-24 14:24                   ` Aneesh Kumar K.V
2021-05-24 14:24                     ` Aneesh Kumar K.V
2021-05-21 15:24               ` Liam Howlett
2021-05-21 15:24                 ` Liam Howlett
2021-05-21 16:02                 ` Aneesh Kumar K.V
2021-05-21 16:02                   ` Aneesh Kumar K.V
2021-05-21 16:05                 ` Linus Torvalds
2021-05-21 16:05                   ` Linus Torvalds
2021-04-22  5:43 ` [PATCH v5 8/9] mm/mremap: Allow arch runtime override Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-04-22  5:43 ` [PATCH v5 9/9] powerpc/mm: Enable move pmd/pud Aneesh Kumar K.V
2021-04-22  5:43   ` Aneesh Kumar K.V
2021-05-11 22:19   ` Andrew Morton [this message]
2021-05-11 22:19     ` Andrew Morton

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