* [igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations @ 2021-05-13 5:09 Andrzej Turko 2021-05-13 5:09 ` [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens " Andrzej Turko ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Andrzej Turko @ 2021-05-13 5:09 UTC (permalink / raw) To: igt-dev With relocations disabled for newer generations the addresses of buffer objects in memory need to be known in advance and, hence, assigned in userspace. If relocations are not supported, the tests now use the intel allocator to find offsets and update the contents of batches correspondingly. Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Andrzej Turko (2): tests/i915/gem_exec_gttfill: Support gens without relocations tests/i915/gem_exec_store: Support gens without relocations tests/i915/gem_exec_gttfill.c | 75 +++++++++++-- tests/i915/gem_exec_store.c | 194 +++++++++++++++++++++++++--------- 2 files changed, 209 insertions(+), 60 deletions(-) -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens without relocations 2021-05-13 5:09 [igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations Andrzej Turko @ 2021-05-13 5:09 ` Andrzej Turko 2021-05-13 5:09 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_exec_store: " Andrzej Turko ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Andrzej Turko @ 2021-05-13 5:09 UTC (permalink / raw) To: igt-dev With relocations disabled for newer generations addresses of objects need to be assigned by the test. As all the objects won't fit in the gtt, using the allocator does not guarantee that submitted batches won't overlap. It only reduces the number of overlapping objects while ensuring that evictions happen at different offsets. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- tests/i915/gem_exec_gttfill.c | 75 ++++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c index c0e27c9bb..091c74ebb 100644 --- a/tests/i915/gem_exec_gttfill.c +++ b/tests/i915/gem_exec_gttfill.c @@ -28,6 +28,8 @@ IGT_TEST_DESCRIPTION("Fill the GTT with batches."); #define BATCH_SIZE (4096<<10) +/* We don't have alignment detection yet, so assume the worst-case scenario. */ +#define BATCH_ALIGNMENT (1 << 21) struct batch { uint32_t handle; @@ -47,15 +49,21 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) static void submit(int fd, int gen, struct drm_i915_gem_execbuffer2 *eb, struct drm_i915_gem_relocation_entry *reloc, - struct batch *batches, unsigned int count) + struct batch *batches, unsigned int count, + uint64_t ahnd, bool do_relocs) { struct drm_i915_gem_exec_object2 obj; uint32_t batch[16]; - unsigned n; + uint64_t address, value; + unsigned n, j; memset(&obj, 0, sizeof(obj)); - obj.relocs_ptr = to_user_pointer(reloc); - obj.relocation_count = 2; + if (do_relocs) { + obj.relocs_ptr = to_user_pointer(reloc); + obj.relocation_count = 2; + } else { + obj.flags |= EXEC_OBJECT_PINNED; + } memset(reloc, 0, 2*sizeof(*reloc)); reloc[0].offset = eb->batch_start_offset; @@ -85,16 +93,40 @@ static void submit(int fd, int gen, batch[++n] = 0; /* lower_32_bits(value) */ batch[++n] = 0; /* upper_32_bits(value) / nop */ batch[++n] = MI_BATCH_BUFFER_END; - eb->buffers_ptr = to_user_pointer(&obj); + j = 0; for (unsigned i = 0; i < count; i++) { obj.handle = batches[i].handle; reloc[0].target_handle = obj.handle; reloc[1].target_handle = obj.handle; - obj.offset = 0; - reloc[0].presumed_offset = obj.offset; - reloc[1].presumed_offset = obj.offset; + if (do_relocs) { + obj.offset = 0; + } else { + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, + BATCH_SIZE, + BATCH_ALIGNMENT, + ALLOC_STRATEGY_HIGH_TO_LOW); + for (; obj.offset == -1; j = ((++j) == count ? 0 : j)) { + if (i != j) + intel_allocator_free(ahnd, batches[j].handle); + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, + BATCH_SIZE, + BATCH_ALIGNMENT, + ALLOC_STRATEGY_HIGH_TO_LOW); + } + + /* If there is no relocation support, we assume gen >= 8. */ + reloc[0].presumed_offset = obj.offset; + address = obj.offset + reloc[0].delta; + batch[1] = address; + batch[2] = address >> 32; + + reloc[1].presumed_offset = obj.offset; + value = obj.offset + reloc[1].delta; + batch[3] = value; + batch[4] = value >> 32; + } memcpy(batches[i].ptr + eb->batch_start_offset, batch, sizeof(batch)); @@ -116,7 +148,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) struct batch *batches; unsigned nengine; unsigned count; - uint64_t size; + uint64_t size, ahnd; + bool do_relocs = gem_has_relocations(fd); shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); igt_assert(shared != MAP_FAILED); @@ -138,6 +171,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) igt_assert(nengine * 64 <= BATCH_SIZE); size = gem_aperture_size(fd); + if (!gem_uses_full_ppgtt(fd)) + size /= 2; if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */ size = 1ull << 32; igt_require(size < (1ull<<32) * BATCH_SIZE); @@ -145,6 +180,12 @@ static void fillgtt(int fd, unsigned ring, int timeout) count = size / BATCH_SIZE + 1; igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n", count, (long long)size, nengine); + + intel_allocator_multiprocess_start(); + /* Avoid allocating on the last page */ + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_HIGH_TO_LOW); intel_require_memory(count, BATCH_SIZE, CHECK_RAM); intel_detect_and_clear_missed_interrupts(fd); @@ -165,7 +206,7 @@ static void fillgtt(int fd, unsigned ring, int timeout) } /* Flush all memory before we start the timer */ - submit(fd, gen, &execbuf, reloc, batches, count); + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); igt_info("Setup %u batches in %.2fms\n", count, 1e-6 * igt_nsec_elapsed(&tv)); @@ -176,8 +217,14 @@ static void fillgtt(int fd, unsigned ring, int timeout) igt_permute_array(batches, count, xchg_batch); execbuf.batch_start_offset = child*64; execbuf.flags |= engines[child]; + + /* We need to open the allocator again in the new process */ + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_HIGH_TO_LOW); + igt_until_timeout(timeout) { - submit(fd, gen, &execbuf, reloc, batches, count); + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); for (unsigned i = 0; i < count; i++) { uint64_t offset, delta; @@ -189,13 +236,18 @@ static void fillgtt(int fd, unsigned ring, int timeout) } shared[child] = cycles; igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles); + intel_allocator_close(ahnd); } igt_waitchildren(); + intel_allocator_close(ahnd); + intel_allocator_multiprocess_stop(); + for (unsigned i = 0; i < count; i++) { munmap(batches[i].ptr, BATCH_SIZE); gem_close(fd, batches[i].handle); } + free(batches); shared[nengine] = 0; for (unsigned i = 0; i < nengine; i++) @@ -216,6 +268,7 @@ igt_main igt_fork_hang_detector(i915); } + igt_subtest("basic") /* just enough to run a single pass */ fillgtt(i915, ALL_ENGINES, 1); -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_exec_store: Support gens without relocations 2021-05-13 5:09 [igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations Andrzej Turko 2021-05-13 5:09 ` [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens " Andrzej Turko @ 2021-05-13 5:09 ` Andrzej Turko 2021-05-13 5:56 ` [igt-dev] ✓ Fi.CI.BAT: success for Keep tests working without relocations (rev2) Patchwork 2021-05-13 8:12 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 0 replies; 9+ messages in thread From: Andrzej Turko @ 2021-05-13 5:09 UTC (permalink / raw) To: igt-dev With relocations disabled on newer generations tests must assign addresses to objects by themselves instead of relying on the driver. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- tests/i915/gem_exec_store.c | 194 +++++++++++++++++++++++++++--------- 1 file changed, 145 insertions(+), 49 deletions(-) diff --git a/tests/i915/gem_exec_store.c b/tests/i915/gem_exec_store.c index 771ee1690..677cf8b9f 100644 --- a/tests/i915/gem_exec_store.c +++ b/tests/i915/gem_exec_store.c @@ -36,6 +36,9 @@ #define ENGINE_MASK (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK) +/* Without alignment detection we assume the worst-case scenario. */ +#define ALIGNMENT (1 << 21) + static void store_dword(int fd, const struct intel_execution_engine2 *e) { const unsigned int gen = intel_gen(intel_get_drm_devid(fd)); @@ -43,7 +46,9 @@ static void store_dword(int fd, const struct intel_execution_engine2 *e) struct drm_i915_gem_relocation_entry reloc; struct drm_i915_gem_execbuffer2 execbuf; uint32_t batch[16]; + uint64_t ahnd; int i; + bool do_relocs = gem_has_relocations(fd); intel_detect_and_clear_missed_interrupts(fd); memset(&execbuf, 0, sizeof(execbuf)); @@ -53,43 +58,64 @@ static void store_dword(int fd, const struct intel_execution_engine2 *e) if (gen > 3 && gen < 6) execbuf.flags |= I915_EXEC_SECURE; + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE); + memset(obj, 0, sizeof(obj)); obj[0].handle = gem_create(fd, 4096); obj[1].handle = gem_create(fd, 4096); - memset(&reloc, 0, sizeof(reloc)); - reloc.target_handle = obj[0].handle; - reloc.presumed_offset = 0; - reloc.offset = sizeof(uint32_t); - reloc.delta = 0; - reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION; - obj[1].relocs_ptr = to_user_pointer(&reloc); - obj[1].relocation_count = 1; + if (do_relocs) { + memset(&reloc, 0, sizeof(reloc)); + reloc.target_handle = obj[0].handle; + reloc.presumed_offset = obj[0].offset; + reloc.offset = sizeof(uint32_t); + reloc.delta = 0; + reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION; + reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION; + obj[1].relocs_ptr = to_user_pointer(&reloc); + obj[1].relocation_count = 1; + } else { + obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle, + 4096, ALIGNMENT); + obj[0].offset = CANONICAL(obj[0].offset); + obj[0].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS | + EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE; + + obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle, + 4096, ALIGNMENT); + obj[1].offset = CANONICAL(obj[1].offset); + obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS | + EXEC_OBJECT_PINNED; + } i = 0; batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); if (gen >= 8) { - batch[++i] = 0; - batch[++i] = 0; + batch[++i] = obj[0].offset; + batch[++i] = obj[0].offset >> 32; } else if (gen >= 4) { batch[++i] = 0; - batch[++i] = 0; + batch[++i] = obj[0].offset; reloc.offset += sizeof(uint32_t); } else { batch[i]--; - batch[++i] = 0; + batch[++i] = obj[0].offset; } batch[++i] = 0xc0ffee; batch[++i] = MI_BATCH_BUFFER_END; gem_write(fd, obj[1].handle, 0, batch, sizeof(batch)); + gem_execbuf(fd, &execbuf); + gem_close(fd, obj[1].handle); + intel_allocator_free(ahnd, obj[1].handle); gem_read(fd, obj[0].handle, 0, batch, sizeof(batch)); gem_close(fd, obj[0].handle); + intel_allocator_free(ahnd, obj[0].handle); igt_assert_eq(*batch, 0xc0ffee); igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); + intel_allocator_close(ahnd); } #define PAGES 1 @@ -102,7 +128,9 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e, struct drm_i915_gem_execbuffer2 execbuf; #define NCACHELINES (4096/64) uint32_t *batch; + uint64_t ahnd, reloc_value; int i; + bool do_relocs = gem_has_relocations(fd); reloc = calloc(NCACHELINES, sizeof(*reloc)); igt_assert(reloc); @@ -114,36 +142,58 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e, if (gen > 3 && gen < 6) execbuf.flags |= I915_EXEC_SECURE; + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE); obj = calloc(execbuf.buffer_count, sizeof(*obj)); igt_assert(obj); - for (i = 0; i < execbuf.buffer_count; i++) + for (i = 0; i < execbuf.buffer_count; i++) { obj[i].handle = gem_create(fd, 4096); - obj[i-1].relocs_ptr = to_user_pointer(reloc); - obj[i-1].relocation_count = NCACHELINES; + + if (!do_relocs) { + obj[i].offset = intel_allocator_alloc(ahnd, obj[i].handle, + 4096, ALIGNMENT); + obj[i].offset = CANONICAL(obj[i].offset); + obj[i].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | + EXEC_OBJECT_PINNED; + if (i + 1 < execbuf.buffer_count) + obj[i].flags |= EXEC_OBJECT_WRITE; + } + } + if (do_relocs) { + obj[i-1].relocs_ptr = to_user_pointer(reloc); + obj[i-1].relocation_count = NCACHELINES; + } execbuf.buffers_ptr = to_user_pointer(obj); batch = gem_mmap__cpu(fd, obj[i-1].handle, 0, 4096, PROT_WRITE); i = 0; for (unsigned n = 0; n < NCACHELINES; n++) { + reloc[n].target_handle = obj[n % (execbuf.buffer_count-1)].handle; - reloc[n].presumed_offset = -1; - reloc[n].offset = (i + 1)*sizeof(uint32_t); reloc[n].delta = 4 * (n * 16 + n % 16); - reloc[n].read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION; + + if (do_relocs) { + reloc[n].presumed_offset = -1; + reloc[n].offset = (i + 1)*sizeof(uint32_t); + reloc[n].read_domains = I915_GEM_DOMAIN_INSTRUCTION; + reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION; + reloc_value = 0; + } else { + reloc_value = obj[n % (execbuf.buffer_count-1)].offset + + reloc[n].delta; + } batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); if (gen >= 8) { - batch[++i] = 0; - batch[++i] = 0; + batch[++i] = reloc_value; + batch[++i] = reloc_value >> 32; } else if (gen >= 4) { batch[++i] = 0; - batch[++i] = 0; + batch[++i] = reloc_value; reloc[n].offset += sizeof(uint32_t); } else { batch[i]--; - batch[++i] = 0; + batch[++i] = reloc_value; } batch[++i] = n | ~n << 16; i++; @@ -163,11 +213,14 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e, } free(reloc); - for (unsigned n = 0; n < execbuf.buffer_count; n++) + for (unsigned n = 0; n < execbuf.buffer_count; n++) { gem_close(fd, obj[n].handle); + intel_allocator_free(ahnd, obj[n].handle); + } free(obj); igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); + intel_allocator_close(ahnd); } static void store_all(int fd) @@ -179,10 +232,11 @@ static void store_all(int fd) struct drm_i915_gem_execbuffer2 execbuf; unsigned *engines, *permuted; uint32_t batch[16]; - uint64_t offset; + uint64_t offset, ahnd, reloc_value; unsigned nengine; - int value; + int value, address; int i, j; + bool do_relocs = gem_has_relocations(fd); nengine = 0; __for_each_physical_engine(fd, engine) { @@ -207,24 +261,43 @@ static void store_all(int fd) if (gen < 6) execbuf.flags |= I915_EXEC_SECURE; + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE); + memset(obj, 0, sizeof(obj)); obj[0].handle = gem_create(fd, nengine*sizeof(uint32_t)); obj[1].handle = gem_create(fd, 2*nengine*sizeof(batch)); - obj[1].relocation_count = 1; + + if (do_relocs) { + obj[1].relocation_count = 1; + } else { + obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle, + nengine*sizeof(uint32_t), + ALIGNMENT); + obj[0].offset = CANONICAL(obj[0].offset); + obj[0].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS | + EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE; + + obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle, + 2*nengine*sizeof(batch), + ALIGNMENT); + obj[1].offset = CANONICAL(obj[1].offset); + obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS | + EXEC_OBJECT_PINNED; + } offset = sizeof(uint32_t); i = 0; batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); if (gen >= 8) { - batch[++i] = 0; + batch[address = ++i] = 0; batch[++i] = 0; } else if (gen >= 4) { batch[++i] = 0; - batch[++i] = 0; + batch[address = ++i] = 0; offset += sizeof(uint32_t); } else { batch[i]--; - batch[++i] = 0; + batch[address = ++i] = 0; } batch[value = ++i] = 0xc0ffee; batch[++i] = MI_BATCH_BUFFER_END; @@ -239,30 +312,45 @@ static void store_all(int fd) execbuf.flags |= engine->flags; j = 2*nengine; - reloc[j].target_handle = obj[0].handle; - reloc[j].presumed_offset = ~0; - reloc[j].offset = j*sizeof(batch) + offset; - reloc[j].delta = nengine*sizeof(uint32_t); - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; - obj[1].relocs_ptr = to_user_pointer(&reloc[j]); - + if (do_relocs) { + reloc[j].target_handle = obj[0].handle; + reloc[j].presumed_offset = ~0; + reloc[j].offset = j*sizeof(batch) + offset; + reloc[j].delta = nengine*sizeof(uint32_t); + reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; + reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; + obj[1].relocs_ptr = to_user_pointer(&reloc[j]); + } else { + reloc_value = obj[0].offset + nengine*sizeof(uint32_t); + /* If there is no relocation support, we assume gen >= 8. */ + batch[address] = reloc_value; + batch[address + 1] = reloc_value >> 32; + } batch[value] = 0xdeadbeef; + gem_write(fd, obj[1].handle, j*sizeof(batch), batch, sizeof(batch)); execbuf.batch_start_offset = j*sizeof(batch); gem_execbuf(fd, &execbuf); j = 2*nengine + 1; - reloc[j].target_handle = obj[0].handle; - reloc[j].presumed_offset = ~0; - reloc[j].offset = j*sizeof(batch) + offset; - reloc[j].delta = nengine*sizeof(uint32_t); - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; - obj[1].relocs_ptr = to_user_pointer(&reloc[j]); - + if (do_relocs) { + reloc[j].target_handle = obj[0].handle; + reloc[j].presumed_offset = ~0; + reloc[j].offset = j*sizeof(batch) + offset; + reloc[j].delta = nengine*sizeof(uint32_t); + reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; + reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; + obj[1].relocs_ptr = to_user_pointer(&reloc[j]); + } else { + reloc_value = obj[0].offset + nengine*sizeof(uint32_t); + batch[address] = reloc_value; + /* If there is no relocation support, we assume gen >= 8. */ + batch[address] = reloc_value; + batch[address + 1] = reloc_value >> 32; + } batch[value] = nengine; + gem_write(fd, obj[1].handle, j*sizeof(batch), batch, sizeof(batch)); execbuf.batch_start_offset = j*sizeof(batch); @@ -273,30 +361,38 @@ static void store_all(int fd) gem_sync(fd, obj[1].handle); for (i = 0; i < nengine; i++) { - obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]); execbuf.batch_start_offset = 2*i*sizeof(batch); memcpy(permuted, engines, nengine*sizeof(engines[0])); igt_permute_array(permuted, nengine, igt_exchange_int); + if (do_relocs) + obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]); + for (j = 0; j < nengine; j++) { execbuf.flags &= ~ENGINE_MASK; execbuf.flags |= permuted[j]; gem_execbuf(fd, &execbuf); } - obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]); + execbuf.batch_start_offset = (2*i+1)*sizeof(batch); execbuf.flags &= ~ENGINE_MASK; execbuf.flags |= engines[i]; + if (do_relocs) + obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]); + gem_execbuf(fd, &execbuf); } gem_close(fd, obj[1].handle); + intel_allocator_free(ahnd, obj[1].handle); gem_read(fd, obj[0].handle, 0, engines, nengine*sizeof(engines[0])); gem_close(fd, obj[0].handle); + intel_allocator_free(ahnd, obj[0].handle); for (i = 0; i < nengine; i++) igt_assert_eq_u32(engines[i], i); igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); + intel_allocator_close(ahnd); free(permuted); free(engines); free(reloc); -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Keep tests working without relocations (rev2) 2021-05-13 5:09 [igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations Andrzej Turko 2021-05-13 5:09 ` [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens " Andrzej Turko 2021-05-13 5:09 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_exec_store: " Andrzej Turko @ 2021-05-13 5:56 ` Patchwork 2021-05-13 8:12 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-05-13 5:56 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 13680 bytes --] == Series Details == Series: Keep tests working without relocations (rev2) URL : https://patchwork.freedesktop.org/series/90049/ State : success == Summary == CI Bug Log - changes from CI_DRM_10074 -> IGTPW_5807 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_5807: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@runner@aborted: - {fi-rkl-11500t}: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-rkl-11500t/igt@runner@aborted.html Known issues ------------ Here are the changes found in IGTPW_5807 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fence@basic-await@vecs0: - fi-bsw-nick: [PASS][2] -> [FAIL][3] ([i915#3457]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-nick/igt@gem_exec_fence@basic-await@vecs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bsw-nick/igt@gem_exec_fence@basic-await@vecs0.html - fi-bxt-dsi: [PASS][4] -> [FAIL][5] ([i915#3457]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bxt-dsi/igt@gem_exec_fence@basic-await@vecs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bxt-dsi/igt@gem_exec_fence@basic-await@vecs0.html - fi-glk-dsi: [PASS][6] -> [FAIL][7] ([i915#3457]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-glk-dsi/igt@gem_exec_fence@basic-await@vecs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-glk-dsi/igt@gem_exec_fence@basic-await@vecs0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271]) +6 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html * igt@gem_exec_fence@nb-await@vecs0: - fi-bsw-kefka: [PASS][9] -> [FAIL][10] ([i915#3457]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html * igt@gem_wait@busy@all: - fi-bsw-nick: [PASS][12] -> [FAIL][13] ([i915#3177] / [i915#3457]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-nick/igt@gem_wait@busy@all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bsw-nick/igt@gem_wait@busy@all.html * igt@gem_wait@wait@all: - fi-bwr-2160: [PASS][14] -> [FAIL][15] ([i915#3457]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bwr-2160/igt@gem_wait@wait@all.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bwr-2160/igt@gem_wait@wait@all.html * igt@i915_module_load@reload: - fi-kbl-soraka: NOTRUN -> [DMESG-WARN][16] ([i915#1982] / [i915#3457]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@i915_module_load@reload.html * igt@i915_selftest@live@execlists: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][17] ([i915#2782] / [i915#3462] / [i915#794]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][18] ([i915#1886] / [i915#2291]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@mman: - fi-kbl-soraka: NOTRUN -> [DMESG-WARN][19] ([i915#3457]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@i915_selftest@live@mman.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a: - fi-bwr-2160: [PASS][21] -> [FAIL][22] ([i915#53]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bwr-2160/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bwr-2160/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#533]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-elk-e7500: [PASS][24] -> [FAIL][25] ([i915#53]) +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a.html * igt@runner@aborted: - fi-kbl-soraka: NOTRUN -> [FAIL][26] ([i915#1436] / [i915#3363]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-kbl-soraka/igt@runner@aborted.html #### Possible fixes #### * igt@gem_exec_fence@basic-await@rcs0: - fi-elk-e7500: [FAIL][27] ([i915#3457]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-elk-e7500/igt@gem_exec_fence@basic-await@rcs0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-elk-e7500/igt@gem_exec_fence@basic-await@rcs0.html * igt@gem_exec_fence@basic-await@vcs0: - fi-bsw-kefka: [FAIL][29] ([i915#3457]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vcs0.html * igt@gem_exec_fence@nb-await@bcs0: - fi-bsw-nick: [FAIL][31] ([i915#3457]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-nick/igt@gem_exec_fence@nb-await@bcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bsw-nick/igt@gem_exec_fence@nb-await@bcs0.html * igt@gem_wait@busy@all: - fi-glk-dsi: [FAIL][33] ([i915#3457]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-glk-dsi/igt@gem_wait@busy@all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-glk-dsi/igt@gem_wait@busy@all.html * igt@gem_wait@wait@all: - fi-pnv-d510: [FAIL][35] ([i915#3457]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-pnv-d510/igt@gem_wait@wait@all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-pnv-d510/igt@gem_wait@wait@all.html * igt@i915_selftest@live@gt_heartbeat: - {fi-jsl-1}: [DMESG-WARN][37] ([i915#1222]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-ilk-650: [FAIL][39] ([i915#53]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html #### Warnings #### * igt@gem_exec_gttfill@basic: - fi-pnv-d510: [FAIL][41] ([i915#3457]) -> [FAIL][42] ([i915#3472]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-pnv-d510/igt@gem_exec_gttfill@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-pnv-d510/igt@gem_exec_gttfill@basic.html - fi-ilk-650: [FAIL][43] ([i915#3457]) -> [FAIL][44] ([i915#3457] / [i915#3472]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-ilk-650/igt@gem_exec_gttfill@basic.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-ilk-650/igt@gem_exec_gttfill@basic.html * igt@i915_module_load@reload: - fi-elk-e7500: [DMESG-WARN][45] ([i915#3457]) -> [DMESG-FAIL][46] ([i915#3457]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-elk-e7500/igt@i915_module_load@reload.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-elk-e7500/igt@i915_module_load@reload.html - fi-bsw-kefka: [DMESG-WARN][47] ([i915#1982] / [i915#3457]) -> [DMESG-FAIL][48] ([i915#3457]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-kefka/igt@i915_module_load@reload.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bsw-kefka/igt@i915_module_load@reload.html * igt@i915_selftest@live@execlists: - fi-tgl-u2: [INCOMPLETE][49] ([i915#3462]) -> [DMESG-FAIL][50] ([i915#3462]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-tgl-u2/igt@i915_selftest@live@execlists.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-tgl-u2/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@mman: - fi-bwr-2160: [DMESG-FAIL][51] ([i915#3457]) -> [DMESG-WARN][52] ([i915#3457]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bwr-2160/igt@i915_selftest@live@mman.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-bwr-2160/igt@i915_selftest@live@mman.html * igt@runner@aborted: - fi-skl-6600u: [FAIL][53] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][54] ([i915#1436] / [i915#3363]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-skl-6600u/igt@runner@aborted.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-skl-6600u/igt@runner@aborted.html - fi-glk-dsi: [FAIL][55] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][56] ([i915#3363] / [k.org#202321]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-glk-dsi/igt@runner@aborted.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-glk-dsi/igt@runner@aborted.html - fi-cfl-guc: [FAIL][57] ([i915#3363]) -> [FAIL][58] ([i915#2426] / [i915#3363]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-cfl-guc/igt@runner@aborted.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/fi-cfl-guc/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177 [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276 [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457 [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462 [i915#3468]: https://gitlab.freedesktop.org/drm/intel/issues/3468 [i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (43 -> 30) ------------------------------ Additional (2): fi-kbl-soraka fi-rkl-11500t Missing (15): fi-kbl-7567u fi-cml-u2 fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-tgl-1115g4 fi-icl-u2 fi-bsw-cyan fi-kbl-7500u fi-dg1-1 fi-cfl-8109u fi-bdw-samus fi-ehl-2 fi-skl-6700k2 fi-kbl-r Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_6083 -> IGTPW_5807 CI-20190529: 20190529 CI_DRM_10074: 5aefdc1f23734b6a3d545c8497b098ba4d704a0c @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5807: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/index.html IGT_6083: d28aee5c5f528aa6c352c3339f20aaed4d698ffa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/index.html [-- Attachment #1.2: Type: text/html, Size: 17387 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Keep tests working without relocations (rev2) 2021-05-13 5:09 [igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations Andrzej Turko ` (2 preceding siblings ...) 2021-05-13 5:56 ` [igt-dev] ✓ Fi.CI.BAT: success for Keep tests working without relocations (rev2) Patchwork @ 2021-05-13 8:12 ` Patchwork 3 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-05-13 8:12 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 30263 bytes --] == Series Details == Series: Keep tests working without relocations (rev2) URL : https://patchwork.freedesktop.org/series/90049/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10074_full -> IGTPW_5807_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_5807_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_5807_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_5807_full: ### IGT changes ### #### Possible regressions #### * igt@api_intel_bb@intel-bb-blit-none: - shard-glk: [PASS][1] -> [FAIL][2] +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk5/igt@api_intel_bb@intel-bb-blit-none.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk2/igt@api_intel_bb@intel-bb-blit-none.html * igt@gem_exec_gttfill@engines@vcs1: - shard-tglb: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_exec_gttfill@engines@vcs1.html * igt@kms_plane_cursor@pipe-a-overlay-size-256: - shard-snb: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@kms_plane_cursor@pipe-a-overlay-size-256.html * igt@kms_prime@basic-crc@second-to-first: - shard-glk: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk2/igt@kms_prime@basic-crc@second-to-first.html #### Warnings #### * igt@kms_plane_cursor@pipe-b-viewport-size-128: - shard-tglb: [FAIL][6] ([i915#3457]) -> [FAIL][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-tglb6/igt@kms_plane_cursor@pipe-b-viewport-size-128.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@kms_plane_cursor@pipe-b-viewport-size-128.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@kms_plane@plane-position-covered@pipe-b-planes}: - shard-glk: [FAIL][8] ([i915#3457]) -> [FAIL][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk8/igt@kms_plane@plane-position-covered@pipe-b-planes.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk2/igt@kms_plane@plane-position-covered@pipe-b-planes.html New tests --------- New tests have been introduced between CI_DRM_10074_full and IGTPW_5807_full: ### New IGT tests (2) ### * igt@kms_plane@plane-panning-top-left@pipe-a-planes: - Statuses : 3 pass(s) - Exec time: [0.53, 1.44] s * igt@kms_plane@plane-panning-top-left@pipe-b-planes: - Statuses : 3 pass(s) - Exec time: [0.53, 2.50] s Known issues ------------ Here are the changes found in IGTPW_5807_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@drm_read@fault-buffer: - shard-glk: NOTRUN -> [DMESG-WARN][10] ([i915#3457]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk5/igt@drm_read@fault-buffer.html * igt@feature_discovery@chamelium: - shard-tglb: NOTRUN -> [SKIP][11] ([fdo#111827]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb5/igt@feature_discovery@chamelium.html - shard-iclb: NOTRUN -> [SKIP][12] ([fdo#111827]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@feature_discovery@chamelium.html * igt@gem_create@create-massive: - shard-iclb: NOTRUN -> [DMESG-WARN][13] ([i915#3002]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb2/igt@gem_create@create-massive.html - shard-kbl: NOTRUN -> [DMESG-WARN][14] ([i915#3002]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl4/igt@gem_create@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][15] ([i915#180] / [i915#3457]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +5 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed-process.html * igt@gem_ctx_persistence@processes: - shard-glk: [PASS][17] -> [TIMEOUT][18] ([i915#3457]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk2/igt@gem_ctx_persistence@processes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk9/igt@gem_ctx_persistence@processes.html * igt@gem_ctx_sseu@invalid-sseu: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#280]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@gem_ctx_sseu@invalid-sseu.html * igt@gem_eio@in-flight-contexts-1us: - shard-tglb: NOTRUN -> [TIMEOUT][20] ([i915#3063] / [i915#3457]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_eio@in-flight-contexts-1us.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2842] / [i915#3457]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][23] ([i915#2842] / [i915#3457]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@gem_exec_fair@basic-none-vip@rcs0.html - shard-iclb: NOTRUN -> [FAIL][24] ([i915#2842] / [i915#3457]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb3/igt@gem_exec_fair@basic-none-vip@rcs0.html - shard-glk: NOTRUN -> [FAIL][25] ([i915#2842] / [i915#3457]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk3/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fence@keep-in-fence@vecs0: - shard-glk: NOTRUN -> [INCOMPLETE][26] ([i915#3457]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk5/igt@gem_exec_fence@keep-in-fence@vecs0.html * igt@gem_exec_gttfill@engines@vecs0: - shard-tglb: NOTRUN -> [WARN][27] ([i915#3457]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_exec_gttfill@engines@vecs0.html * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> [SKIP][28] ([fdo#109283]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb4/igt@gem_exec_params@no-vebox.html - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#109283]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_exec_params@no-vebox.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][30] ([fdo#112283]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb5/igt@gem_exec_params@secure-non-root.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-tglb: NOTRUN -> [FAIL][31] ([i915#2389] / [i915#3457]) +4 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb6/igt@gem_exec_reloc@basic-wide-active@bcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][32] ([i915#2389] / [i915#3457]) +2 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@gem_exec_reloc@basic-wide-active@rcs0.html - shard-kbl: NOTRUN -> [FAIL][33] ([i915#2389] / [i915#3457]) +4 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl2/igt@gem_exec_reloc@basic-wide-active@rcs0.html * igt@gem_exec_schedule@preempt@vcs0: - shard-glk: NOTRUN -> [FAIL][34] ([i915#3457]) +39 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk4/igt@gem_exec_schedule@preempt@vcs0.html * igt@gem_exec_schedule@submit-late-slice@vecs0: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#3457]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl3/igt@gem_exec_schedule@submit-late-slice@vecs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl2/igt@gem_exec_schedule@submit-late-slice@vecs0.html * igt@gem_exec_whisper@basic-contexts-all: - shard-glk: [PASS][37] -> [DMESG-WARN][38] ([i915#118] / [i915#95]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk5/igt@gem_exec_whisper@basic-contexts-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk8/igt@gem_exec_whisper@basic-contexts-all.html * igt@gem_media_vme: - shard-tglb: NOTRUN -> [SKIP][39] ([i915#284]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_media_vme.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-glk: [PASS][40] -> [INCOMPLETE][41] ([i915#3468]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk4/igt@gem_mmap_gtt@cpuset-basic-small-copy.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk6/igt@gem_mmap_gtt@cpuset-basic-small-copy.html - shard-apl: [PASS][42] -> [INCOMPLETE][43] ([i915#3468]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl3/igt@gem_mmap_gtt@cpuset-basic-small-copy.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl6/igt@gem_mmap_gtt@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-snb: NOTRUN -> [INCOMPLETE][44] ([i915#3468]) +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: NOTRUN -> [FAIL][45] ([i915#644]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk6/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][46] ([i915#2658]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@gem_pwrite@basic-exhaustion.html - shard-iclb: NOTRUN -> [WARN][47] ([i915#2658]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb4/igt@gem_pwrite@basic-exhaustion.html - shard-kbl: NOTRUN -> [WARN][48] ([i915#2658]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl2/igt@gem_pwrite@basic-exhaustion.html - shard-tglb: NOTRUN -> [WARN][49] ([i915#2658]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_pwrite@basic-exhaustion.html - shard-glk: NOTRUN -> [WARN][50] ([i915#2658]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk9/igt@gem_pwrite@basic-exhaustion.html * igt@gem_render_copy@yf-tiled-ccs-to-x-tiled: - shard-apl: NOTRUN -> [INCOMPLETE][51] ([i915#3468]) +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl6/igt@gem_render_copy@yf-tiled-ccs-to-x-tiled.html * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs: - shard-kbl: NOTRUN -> [INCOMPLETE][52] ([i915#3468]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl4/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs.html * igt@gem_softpin@evict-snoop: - shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109312]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@gem_softpin@evict-snoop.html * igt@gem_spin_batch@legacy@default: - shard-apl: NOTRUN -> [FAIL][54] ([i915#2898] / [i915#3457]) +3 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl1/igt@gem_spin_batch@legacy@default.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#3323]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl4/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@input-checking: - shard-tglb: NOTRUN -> [DMESG-WARN][56] ([i915#3002]) +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_userptr_blits@input-checking.html - shard-apl: NOTRUN -> [DMESG-WARN][57] ([i915#3002]) +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl2/igt@gem_userptr_blits@input-checking.html - shard-glk: NOTRUN -> [DMESG-WARN][58] ([i915#3002]) +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk6/igt@gem_userptr_blits@input-checking.html - shard-snb: NOTRUN -> [DMESG-WARN][59] ([i915#3002]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-tglb: NOTRUN -> [SKIP][60] ([i915#3297]) +2 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gem_userptr_blits@unsync-unmap-cycles.html - shard-iclb: NOTRUN -> [SKIP][61] ([i915#3297]) +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@gem_userptr_blits@unsync-unmap-cycles.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][62] -> [DMESG-WARN][63] ([i915#180] / [i915#3457]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl1/igt@gem_workarounds@suspend-resume-context.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl1/igt@gem_workarounds@suspend-resume-context.html * igt@gen3_render_mixed_blits: - shard-tglb: NOTRUN -> [SKIP][64] ([fdo#109289]) +5 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@gen3_render_mixed_blits.html * igt@gen7_exec_parse@load-register-reg: - shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109289]) +4 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb4/igt@gen7_exec_parse@load-register-reg.html * igt@gen9_exec_parse@bb-large: - shard-tglb: NOTRUN -> [SKIP][66] ([i915#2527]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@gen9_exec_parse@bb-large.html - shard-kbl: NOTRUN -> [FAIL][67] ([i915#3296]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl2/igt@gen9_exec_parse@bb-large.html * igt@gen9_exec_parse@bb-start-cmd: - shard-tglb: NOTRUN -> [SKIP][68] ([fdo#112306]) +3 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb2/igt@gen9_exec_parse@bb-start-cmd.html * igt@gen9_exec_parse@secure-batches: - shard-iclb: NOTRUN -> [SKIP][69] ([fdo#112306]) +2 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@gen9_exec_parse@secure-batches.html * igt@i915_hangman@engine-error@bcs0: - shard-tglb: NOTRUN -> [DMESG-WARN][70] ([i915#3457]) +9 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb5/igt@i915_hangman@engine-error@bcs0.html * igt@i915_hangman@engine-error@vcs0: - shard-iclb: NOTRUN -> [DMESG-WARN][71] ([i915#3457]) +7 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@i915_hangman@engine-error@vcs0.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#1937]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html - shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#1937]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a: - shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#1937]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-kbl: NOTRUN -> [DMESG-WARN][75] ([i915#3457]) +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl4/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rpm@cursor-dpms: - shard-iclb: [PASS][76] -> [DMESG-WARN][77] ([i915#3457]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-iclb3/igt@i915_pm_rpm@cursor-dpms.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb6/igt@i915_pm_rpm@cursor-dpms.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-tglb: NOTRUN -> [SKIP][78] ([fdo#111644] / [i915#1397] / [i915#2411]) +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb7/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109293] / [fdo#109506]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb4/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait: - shard-iclb: NOTRUN -> [SKIP][80] ([fdo#110892]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb3/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-tglb: NOTRUN -> [SKIP][81] ([fdo#109506] / [i915#2411]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@i915_pm_rps@reset: - shard-apl: NOTRUN -> [DMESG-FAIL][82] ([i915#3457]) +1 similar issue [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl1/igt@i915_pm_rps@reset.html - shard-glk: NOTRUN -> [DMESG-FAIL][83] ([i915#3457]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk3/igt@i915_pm_rps@reset.html * igt@i915_query@query-topology-known-pci-ids: - shard-tglb: NOTRUN -> [SKIP][84] ([fdo#109303]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb2/igt@i915_query@query-topology-known-pci-ids.html - shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109303]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb6/igt@i915_query@query-topology-known-pci-ids.html * igt@i915_query@query-topology-unsupported: - shard-iclb: NOTRUN -> [SKIP][86] ([fdo#109302]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb7/igt@i915_query@query-topology-unsupported.html - shard-tglb: NOTRUN -> [SKIP][87] ([fdo#109302]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@i915_query@query-topology-unsupported.html * igt@i915_selftest@live@execlists: - shard-tglb: NOTRUN -> [INCOMPLETE][88] ([i915#3462]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb6/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@gt_lrc: - shard-tglb: NOTRUN -> [DMESG-FAIL][89] ([i915#2373]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb6/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@gt_pm: - shard-tglb: NOTRUN -> [DMESG-FAIL][90] ([i915#1759] / [i915#2291]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb6/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - shard-snb: NOTRUN -> [INCOMPLETE][91] ([i915#2782]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@mman: - shard-snb: NOTRUN -> [DMESG-WARN][92] ([i915#3457]) +1 similar issue [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@i915_selftest@live@mman.html * igt@kms_big_fb@linear-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][93] ([fdo#111614]) +7 similar issues [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb7/igt@kms_big_fb@linear-8bpp-rotate-270.html * igt@kms_big_fb@x-tiled-16bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][94] ([fdo#110725] / [fdo#111614]) +5 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-180: - shard-tglb: NOTRUN -> [SKIP][95] ([fdo#111615]) +8 similar issues [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb5/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html - shard-iclb: NOTRUN -> [SKIP][96] ([fdo#110723]) +1 similar issue [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html * igt@kms_big_joiner@invalid-modeset: - shard-iclb: NOTRUN -> [SKIP][97] ([i915#2705]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb7/igt@kms_big_joiner@invalid-modeset.html - shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2705]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl6/igt@kms_big_joiner@invalid-modeset.html - shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2705]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl8/igt@kms_big_joiner@invalid-modeset.html - shard-glk: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2705]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk4/igt@kms_big_joiner@invalid-modeset.html - shard-tglb: NOTRUN -> [SKIP][101] ([i915#2705]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@kms_big_joiner@invalid-modeset.html * igt@kms_ccs@pipe-a-ccs-on-another-bo: - shard-snb: NOTRUN -> [SKIP][102] ([fdo#109271]) +373 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@kms_ccs@pipe-a-ccs-on-another-bo.html * igt@kms_ccs@pipe-d-bad-rotation-90: - shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109278]) +13 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb6/igt@kms_ccs@pipe-d-bad-rotation-90.html * igt@kms_chamelium@hdmi-edid-read: - shard-tglb: NOTRUN -> [SKIP][104] ([fdo#109284] / [fdo#111827]) +23 similar issues [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb3/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109284] / [fdo#111827]) +17 similar issues [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb4/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html * igt@kms_chamelium@vga-hpd-enable-disable-mode: - shard-glk: NOTRUN -> [SKIP][106] ([fdo#109271] / [fdo#111827]) +14 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk9/igt@kms_chamelium@vga-hpd-enable-disable-mode.html * igt@kms_color@pipe-a-degamma: - shard-iclb: NOTRUN -> [FAIL][107] ([i915#1149]) +1 similar issue [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb4/igt@kms_color@pipe-a-degamma.html * igt@kms_color@pipe-b-degamma: - shard-tglb: NOTRUN -> [FAIL][108] ([i915#1149]) +1 similar issue [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb2/igt@kms_color@pipe-b-degamma.html - shard-glk: NOTRUN -> [FAIL][109] ([i915#71]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk2/igt@kms_color@pipe-b-degamma.html * igt@kms_color@pipe-c-gamma: - shard-glk: [PASS][110] -> [FAIL][111] ([i915#71]) +1 similar issue [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk3/igt@kms_color@pipe-c-gamma.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk4/igt@kms_color@pipe-c-gamma.html * igt@kms_color@pipe-d-ctm-0-75: - shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109278] / [i915#1149]) +1 similar issue [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb5/igt@kms_color@pipe-d-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-0-25: - shard-snb: NOTRUN -> [SKIP][113] ([fdo#109271] / [fdo#111827]) +29 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-0-25.html * igt@kms_color_chamelium@pipe-a-ctm-0-75: - shard-kbl: NOTRUN -> [SKIP][114] ([fdo#109271] / [fdo#111827]) +26 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [fdo#111827]) +22 similar issues [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-iclb: NOTRUN -> [SKIP][116] ([fdo#109278] / [fdo#109284] / [fdo#111827]) [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@kms_color_chamelium@pipe-d-gamma.html * igt@kms_content_protection@dp-mst-lic-type-0: - shard-iclb: NOTRUN -> [SKIP][117] ([i915#3116]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb3/igt@kms_content_protection@dp-mst-lic-type-0.html - shard-tglb: NOTRUN -> [SKIP][118] ([i915#3116]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb8/igt@kms_content_protection@dp-mst-lic-type-0.html * igt@kms_content_protection@lic: - shard-apl: NOTRUN -> [TIMEOUT][119] ([i915#1319]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl2/igt@kms_content_protection@lic.html * igt@kms_content_protection@mei_interface: - shard-iclb: NOTRUN -> [SKIP][120] ([fdo#109300] / [fdo#111066]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@kms_content_protection@mei_interface.html * igt@kms_content_protection@srm: - shard-tglb: NOTRUN -> [SKIP][121] ([fdo#111828]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@kms_content_protection@srm.html - shard-kbl: NOTRUN -> [TIMEOUT][122] ([i915#1319]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl2/igt@kms_content_protection@srm.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding: - shard-snb: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#3457]) +46 similar issues [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb7/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html * igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement: - shard-iclb: NOTRUN -> [SKIP][124] ([fdo#109278] / [fdo#109279] / [i915#3457]) +2 similar issues [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-random: - shard-apl: NOTRUN -> [FAIL][125] ([i915#3444] / [i915#3457]) +3 similar issues [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen: - shard-tglb: [PASS][126] -> [FAIL][127] ([i915#2124] / [i915#3457]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen: - shard-snb: NOTRUN -> [FAIL][128] ([i915#3457]) +10 similar issues [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-snb5/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html * igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding: - shard-tglb: NOTRUN -> [SKIP][129] ([i915#3359] / [i915#3457]) +7 similar issues [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen: - shard-kbl: NOTRUN -> [FAIL][130] ([i915#3444] / [i915#3457]) +19 similar issues [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html - shard-iclb: NOTRUN -> [FAIL][131] ([i915#3457]) +11 similar issues [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-iclb4/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-random: - shard-glk: NOTRUN -> [FAIL][132] ([i915#3444] / [i915#3457]) +13 similar issues [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/shard-glk3/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque: - shard-kbl: [PASS][133] -> [FAIL][134] ([i915#3444] / [i915#3457]) [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-alph == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5807/index.html [-- Attachment #1.2: Type: text/html, Size: 34060 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH v3 i-g-t 0/2] Keep tests working without relocations @ 2021-06-09 10:42 Andrzej Turko 2021-06-09 10:42 ` [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens " Andrzej Turko 0 siblings, 1 reply; 9+ messages in thread From: Andrzej Turko @ 2021-06-09 10:42 UTC (permalink / raw) To: igt-dev With relocations disabled for newer generations the addresses of buffer objects in memory need to be known in advance and, hence, assigned in userspace. If relocations are not supported, the tests now use the intel allocator to find offsets and update the contents of batches correspondingly. Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Andrzej Turko (2): tests/i915/gem_exec_gttfill: Support gens without relocations tests/i915/gem_exec_store: Support gens without relocations tests/i915/gem_exec_gttfill.c | 75 +++++++++++-- tests/i915/gem_exec_store.c | 194 +++++++++++++++++++++++++--------- 2 files changed, 209 insertions(+), 60 deletions(-) -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens without relocations 2021-06-09 10:42 [igt-dev] [PATCH v3 i-g-t 0/2] Keep tests working without relocations Andrzej Turko @ 2021-06-09 10:42 ` Andrzej Turko 0 siblings, 0 replies; 9+ messages in thread From: Andrzej Turko @ 2021-06-09 10:42 UTC (permalink / raw) To: igt-dev With relocations disabled for newer generations addresses of objects need to be assigned by the test. As all the objects won't fit in the gtt, using the allocator does not guarantee that submitted batches won't overlap. It only reduces the number of overlapping objects while ensuring that evictions happen at different offsets. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- tests/i915/gem_exec_gttfill.c | 75 ++++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c index c0e27c9bb..091c74ebb 100644 --- a/tests/i915/gem_exec_gttfill.c +++ b/tests/i915/gem_exec_gttfill.c @@ -28,6 +28,8 @@ IGT_TEST_DESCRIPTION("Fill the GTT with batches."); #define BATCH_SIZE (4096<<10) +/* We don't have alignment detection yet, so assume the worst-case scenario. */ +#define BATCH_ALIGNMENT (1 << 21) struct batch { uint32_t handle; @@ -47,15 +49,21 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) static void submit(int fd, int gen, struct drm_i915_gem_execbuffer2 *eb, struct drm_i915_gem_relocation_entry *reloc, - struct batch *batches, unsigned int count) + struct batch *batches, unsigned int count, + uint64_t ahnd, bool do_relocs) { struct drm_i915_gem_exec_object2 obj; uint32_t batch[16]; - unsigned n; + uint64_t address, value; + unsigned n, j; memset(&obj, 0, sizeof(obj)); - obj.relocs_ptr = to_user_pointer(reloc); - obj.relocation_count = 2; + if (do_relocs) { + obj.relocs_ptr = to_user_pointer(reloc); + obj.relocation_count = 2; + } else { + obj.flags |= EXEC_OBJECT_PINNED; + } memset(reloc, 0, 2*sizeof(*reloc)); reloc[0].offset = eb->batch_start_offset; @@ -85,16 +93,40 @@ static void submit(int fd, int gen, batch[++n] = 0; /* lower_32_bits(value) */ batch[++n] = 0; /* upper_32_bits(value) / nop */ batch[++n] = MI_BATCH_BUFFER_END; - eb->buffers_ptr = to_user_pointer(&obj); + j = 0; for (unsigned i = 0; i < count; i++) { obj.handle = batches[i].handle; reloc[0].target_handle = obj.handle; reloc[1].target_handle = obj.handle; - obj.offset = 0; - reloc[0].presumed_offset = obj.offset; - reloc[1].presumed_offset = obj.offset; + if (do_relocs) { + obj.offset = 0; + } else { + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, + BATCH_SIZE, + BATCH_ALIGNMENT, + ALLOC_STRATEGY_HIGH_TO_LOW); + for (; obj.offset == -1; j = ((++j) == count ? 0 : j)) { + if (i != j) + intel_allocator_free(ahnd, batches[j].handle); + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, + BATCH_SIZE, + BATCH_ALIGNMENT, + ALLOC_STRATEGY_HIGH_TO_LOW); + } + + /* If there is no relocation support, we assume gen >= 8. */ + reloc[0].presumed_offset = obj.offset; + address = obj.offset + reloc[0].delta; + batch[1] = address; + batch[2] = address >> 32; + + reloc[1].presumed_offset = obj.offset; + value = obj.offset + reloc[1].delta; + batch[3] = value; + batch[4] = value >> 32; + } memcpy(batches[i].ptr + eb->batch_start_offset, batch, sizeof(batch)); @@ -116,7 +148,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) struct batch *batches; unsigned nengine; unsigned count; - uint64_t size; + uint64_t size, ahnd; + bool do_relocs = gem_has_relocations(fd); shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); igt_assert(shared != MAP_FAILED); @@ -138,6 +171,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) igt_assert(nengine * 64 <= BATCH_SIZE); size = gem_aperture_size(fd); + if (!gem_uses_full_ppgtt(fd)) + size /= 2; if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */ size = 1ull << 32; igt_require(size < (1ull<<32) * BATCH_SIZE); @@ -145,6 +180,12 @@ static void fillgtt(int fd, unsigned ring, int timeout) count = size / BATCH_SIZE + 1; igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n", count, (long long)size, nengine); + + intel_allocator_multiprocess_start(); + /* Avoid allocating on the last page */ + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_HIGH_TO_LOW); intel_require_memory(count, BATCH_SIZE, CHECK_RAM); intel_detect_and_clear_missed_interrupts(fd); @@ -165,7 +206,7 @@ static void fillgtt(int fd, unsigned ring, int timeout) } /* Flush all memory before we start the timer */ - submit(fd, gen, &execbuf, reloc, batches, count); + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); igt_info("Setup %u batches in %.2fms\n", count, 1e-6 * igt_nsec_elapsed(&tv)); @@ -176,8 +217,14 @@ static void fillgtt(int fd, unsigned ring, int timeout) igt_permute_array(batches, count, xchg_batch); execbuf.batch_start_offset = child*64; execbuf.flags |= engines[child]; + + /* We need to open the allocator again in the new process */ + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_HIGH_TO_LOW); + igt_until_timeout(timeout) { - submit(fd, gen, &execbuf, reloc, batches, count); + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); for (unsigned i = 0; i < count; i++) { uint64_t offset, delta; @@ -189,13 +236,18 @@ static void fillgtt(int fd, unsigned ring, int timeout) } shared[child] = cycles; igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles); + intel_allocator_close(ahnd); } igt_waitchildren(); + intel_allocator_close(ahnd); + intel_allocator_multiprocess_stop(); + for (unsigned i = 0; i < count; i++) { munmap(batches[i].ptr, BATCH_SIZE); gem_close(fd, batches[i].handle); } + free(batches); shared[nengine] = 0; for (unsigned i = 0; i < nengine; i++) @@ -216,6 +268,7 @@ igt_main igt_fork_hang_detector(i915); } + igt_subtest("basic") /* just enough to run a single pass */ fillgtt(i915, ALL_ENGINES, 1); -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens without relocations @ 2021-05-12 5:40 Andrzej Turko 2021-05-12 8:14 ` Zbigniew Kempczyński 2021-05-12 9:28 ` Zbigniew Kempczyński 0 siblings, 2 replies; 9+ messages in thread From: Andrzej Turko @ 2021-05-12 5:40 UTC (permalink / raw) To: igt-dev With relocations disabled for newer generations addresses of objects need to be assigned by the test. As all the objects won't fit in the gtt, using the allocator does not guarantee that submitted batches won't overlap. It only reduces the number of overlapping objects while ensuring that evictions happen at different offsets. Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> --- tests/i915/gem_exec_gttfill.c | 75 ++++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c index c0e27c9bb..091c74ebb 100644 --- a/tests/i915/gem_exec_gttfill.c +++ b/tests/i915/gem_exec_gttfill.c @@ -28,6 +28,8 @@ IGT_TEST_DESCRIPTION("Fill the GTT with batches."); #define BATCH_SIZE (4096<<10) +/* We don't have alignment detection yet, so assume the worst-case scenario. */ +#define BATCH_ALIGNMENT (1 << 21) struct batch { uint32_t handle; @@ -47,15 +49,21 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) static void submit(int fd, int gen, struct drm_i915_gem_execbuffer2 *eb, struct drm_i915_gem_relocation_entry *reloc, - struct batch *batches, unsigned int count) + struct batch *batches, unsigned int count, + uint64_t ahnd, bool do_relocs) { struct drm_i915_gem_exec_object2 obj; uint32_t batch[16]; - unsigned n; + uint64_t address, value; + unsigned n, j; memset(&obj, 0, sizeof(obj)); - obj.relocs_ptr = to_user_pointer(reloc); - obj.relocation_count = 2; + if (do_relocs) { + obj.relocs_ptr = to_user_pointer(reloc); + obj.relocation_count = 2; + } else { + obj.flags |= EXEC_OBJECT_PINNED; + } memset(reloc, 0, 2*sizeof(*reloc)); reloc[0].offset = eb->batch_start_offset; @@ -85,16 +93,40 @@ static void submit(int fd, int gen, batch[++n] = 0; /* lower_32_bits(value) */ batch[++n] = 0; /* upper_32_bits(value) / nop */ batch[++n] = MI_BATCH_BUFFER_END; - eb->buffers_ptr = to_user_pointer(&obj); + j = 0; for (unsigned i = 0; i < count; i++) { obj.handle = batches[i].handle; reloc[0].target_handle = obj.handle; reloc[1].target_handle = obj.handle; - obj.offset = 0; - reloc[0].presumed_offset = obj.offset; - reloc[1].presumed_offset = obj.offset; + if (do_relocs) { + obj.offset = 0; + } else { + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, + BATCH_SIZE, + BATCH_ALIGNMENT, + ALLOC_STRATEGY_HIGH_TO_LOW); + for (; obj.offset == -1; j = ((++j) == count ? 0 : j)) { + if (i != j) + intel_allocator_free(ahnd, batches[j].handle); + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, + BATCH_SIZE, + BATCH_ALIGNMENT, + ALLOC_STRATEGY_HIGH_TO_LOW); + } + + /* If there is no relocation support, we assume gen >= 8. */ + reloc[0].presumed_offset = obj.offset; + address = obj.offset + reloc[0].delta; + batch[1] = address; + batch[2] = address >> 32; + + reloc[1].presumed_offset = obj.offset; + value = obj.offset + reloc[1].delta; + batch[3] = value; + batch[4] = value >> 32; + } memcpy(batches[i].ptr + eb->batch_start_offset, batch, sizeof(batch)); @@ -116,7 +148,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) struct batch *batches; unsigned nengine; unsigned count; - uint64_t size; + uint64_t size, ahnd; + bool do_relocs = gem_has_relocations(fd); shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); igt_assert(shared != MAP_FAILED); @@ -138,6 +171,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) igt_assert(nengine * 64 <= BATCH_SIZE); size = gem_aperture_size(fd); + if (!gem_uses_full_ppgtt(fd)) + size /= 2; if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */ size = 1ull << 32; igt_require(size < (1ull<<32) * BATCH_SIZE); @@ -145,6 +180,12 @@ static void fillgtt(int fd, unsigned ring, int timeout) count = size / BATCH_SIZE + 1; igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n", count, (long long)size, nengine); + + intel_allocator_multiprocess_start(); + /* Avoid allocating on the last page */ + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_HIGH_TO_LOW); intel_require_memory(count, BATCH_SIZE, CHECK_RAM); intel_detect_and_clear_missed_interrupts(fd); @@ -165,7 +206,7 @@ static void fillgtt(int fd, unsigned ring, int timeout) } /* Flush all memory before we start the timer */ - submit(fd, gen, &execbuf, reloc, batches, count); + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); igt_info("Setup %u batches in %.2fms\n", count, 1e-6 * igt_nsec_elapsed(&tv)); @@ -176,8 +217,14 @@ static void fillgtt(int fd, unsigned ring, int timeout) igt_permute_array(batches, count, xchg_batch); execbuf.batch_start_offset = child*64; execbuf.flags |= engines[child]; + + /* We need to open the allocator again in the new process */ + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_HIGH_TO_LOW); + igt_until_timeout(timeout) { - submit(fd, gen, &execbuf, reloc, batches, count); + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); for (unsigned i = 0; i < count; i++) { uint64_t offset, delta; @@ -189,13 +236,18 @@ static void fillgtt(int fd, unsigned ring, int timeout) } shared[child] = cycles; igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles); + intel_allocator_close(ahnd); } igt_waitchildren(); + intel_allocator_close(ahnd); + intel_allocator_multiprocess_stop(); + for (unsigned i = 0; i < count; i++) { munmap(batches[i].ptr, BATCH_SIZE); gem_close(fd, batches[i].handle); } + free(batches); shared[nengine] = 0; for (unsigned i = 0; i < nengine; i++) @@ -216,6 +268,7 @@ igt_main igt_fork_hang_detector(i915); } + igt_subtest("basic") /* just enough to run a single pass */ fillgtt(i915, ALL_ENGINES, 1); -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens without relocations 2021-05-12 5:40 Andrzej Turko @ 2021-05-12 8:14 ` Zbigniew Kempczyński 2021-05-12 9:28 ` Zbigniew Kempczyński 1 sibling, 0 replies; 9+ messages in thread From: Zbigniew Kempczyński @ 2021-05-12 8:14 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev On Wed, May 12, 2021 at 07:40:09AM +0200, Andrzej Turko wrote: > With relocations disabled for newer generations > addresses of objects need to be assigned by the test. > As all the objects won't fit in the gtt, using the allocator > does not guarantee that submitted batches won't overlap. > It only reduces the number of overlapping objects while ensuring > that evictions happen at different offsets. > > Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > --- > tests/i915/gem_exec_gttfill.c | 75 ++++++++++++++++++++++++++++++----- > 1 file changed, 64 insertions(+), 11 deletions(-) > > diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c > index c0e27c9bb..091c74ebb 100644 > --- a/tests/i915/gem_exec_gttfill.c > +++ b/tests/i915/gem_exec_gttfill.c > @@ -28,6 +28,8 @@ > IGT_TEST_DESCRIPTION("Fill the GTT with batches."); > > #define BATCH_SIZE (4096<<10) > +/* We don't have alignment detection yet, so assume the worst-case scenario. */ > +#define BATCH_ALIGNMENT (1 << 21) > > struct batch { > uint32_t handle; > @@ -47,15 +49,21 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > static void submit(int fd, int gen, > struct drm_i915_gem_execbuffer2 *eb, > struct drm_i915_gem_relocation_entry *reloc, > - struct batch *batches, unsigned int count) > + struct batch *batches, unsigned int count, > + uint64_t ahnd, bool do_relocs) ahnd == 0 is invalid, you can use it instead of additional do_relocs variable. > { > struct drm_i915_gem_exec_object2 obj; > uint32_t batch[16]; > - unsigned n; > + uint64_t address, value; > + unsigned n, j; > > memset(&obj, 0, sizeof(obj)); > - obj.relocs_ptr = to_user_pointer(reloc); > - obj.relocation_count = 2; > + if (do_relocs) { > + obj.relocs_ptr = to_user_pointer(reloc); > + obj.relocation_count = 2; > + } else { > + obj.flags |= EXEC_OBJECT_PINNED; > + } > > memset(reloc, 0, 2*sizeof(*reloc)); > reloc[0].offset = eb->batch_start_offset; > @@ -85,16 +93,40 @@ static void submit(int fd, int gen, > batch[++n] = 0; /* lower_32_bits(value) */ > batch[++n] = 0; /* upper_32_bits(value) / nop */ > batch[++n] = MI_BATCH_BUFFER_END; > - > eb->buffers_ptr = to_user_pointer(&obj); > + j = 0; > for (unsigned i = 0; i < count; i++) { > obj.handle = batches[i].handle; > reloc[0].target_handle = obj.handle; > reloc[1].target_handle = obj.handle; > > - obj.offset = 0; > - reloc[0].presumed_offset = obj.offset; > - reloc[1].presumed_offset = obj.offset; > + if (do_relocs) { > + obj.offset = 0; > + } else { > + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, > + BATCH_SIZE, > + BATCH_ALIGNMENT, > + ALLOC_STRATEGY_HIGH_TO_LOW); > + for (; obj.offset == -1; j = ((++j) == count ? 0 : j)) { > + if (i != j) > + intel_allocator_free(ahnd, batches[j].handle); > + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, > + BATCH_SIZE, > + BATCH_ALIGNMENT, > + ALLOC_STRATEGY_HIGH_TO_LOW); > + } Ha, we're in userspace competing over single offsets set. Why you just don't use: j = (j + 1) % count; It is more readable and no sequencing risk can occur (it would be likely catched by compiler). > + > + /* If there is no relocation support, we assume gen >= 8. */ > + reloc[0].presumed_offset = obj.offset; > + address = obj.offset + reloc[0].delta; > + batch[1] = address; > + batch[2] = address >> 32; > + > + reloc[1].presumed_offset = obj.offset; > + value = obj.offset + reloc[1].delta; > + batch[3] = value; > + batch[4] = value >> 32; > + } > > memcpy(batches[i].ptr + eb->batch_start_offset, > batch, sizeof(batch)); > @@ -116,7 +148,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) > struct batch *batches; > unsigned nengine; > unsigned count; > - uint64_t size; > + uint64_t size, ahnd; > + bool do_relocs = gem_has_relocations(fd); > > shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > igt_assert(shared != MAP_FAILED); > @@ -138,6 +171,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) > igt_assert(nengine * 64 <= BATCH_SIZE); > > size = gem_aperture_size(fd); > + if (!gem_uses_full_ppgtt(fd)) > + size /= 2; > if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */ > size = 1ull << 32; > igt_require(size < (1ull<<32) * BATCH_SIZE); > @@ -145,6 +180,12 @@ static void fillgtt(int fd, unsigned ring, int timeout) > count = size / BATCH_SIZE + 1; > igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n", > count, (long long)size, nengine); > + > + intel_allocator_multiprocess_start(); intel_allocator_multiprocess_start()|stop() should be in igt_fixture. Otherwise if test will fail we got hanging allocator thread. This likely is not a problem for CI (igt_runner calls tests individually) we can encounter unpredictable effects when tests are running sequentially. -- Zbigniew > + /* Avoid allocating on the last page */ > + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_HIGH_TO_LOW); > intel_require_memory(count, BATCH_SIZE, CHECK_RAM); > intel_detect_and_clear_missed_interrupts(fd); > > @@ -165,7 +206,7 @@ static void fillgtt(int fd, unsigned ring, int timeout) > } > > /* Flush all memory before we start the timer */ > - submit(fd, gen, &execbuf, reloc, batches, count); > + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); > > igt_info("Setup %u batches in %.2fms\n", > count, 1e-6 * igt_nsec_elapsed(&tv)); > @@ -176,8 +217,14 @@ static void fillgtt(int fd, unsigned ring, int timeout) > igt_permute_array(batches, count, xchg_batch); > execbuf.batch_start_offset = child*64; > execbuf.flags |= engines[child]; > + > + /* We need to open the allocator again in the new process */ > + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_HIGH_TO_LOW); > + > igt_until_timeout(timeout) { > - submit(fd, gen, &execbuf, reloc, batches, count); > + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); > for (unsigned i = 0; i < count; i++) { > uint64_t offset, delta; > > @@ -189,13 +236,18 @@ static void fillgtt(int fd, unsigned ring, int timeout) > } > shared[child] = cycles; > igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles); > + intel_allocator_close(ahnd); > } > igt_waitchildren(); > > + intel_allocator_close(ahnd); > + intel_allocator_multiprocess_stop(); > + > for (unsigned i = 0; i < count; i++) { > munmap(batches[i].ptr, BATCH_SIZE); > gem_close(fd, batches[i].handle); > } > + free(batches); > > shared[nengine] = 0; > for (unsigned i = 0; i < nengine; i++) > @@ -216,6 +268,7 @@ igt_main > igt_fork_hang_detector(i915); > } > > + > igt_subtest("basic") /* just enough to run a single pass */ > fillgtt(i915, ALL_ENGINES, 1); > > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens without relocations 2021-05-12 5:40 Andrzej Turko 2021-05-12 8:14 ` Zbigniew Kempczyński @ 2021-05-12 9:28 ` Zbigniew Kempczyński 1 sibling, 0 replies; 9+ messages in thread From: Zbigniew Kempczyński @ 2021-05-12 9:28 UTC (permalink / raw) To: Andrzej Turko; +Cc: igt-dev On Wed, May 12, 2021 at 07:40:09AM +0200, Andrzej Turko wrote: > With relocations disabled for newer generations > addresses of objects need to be assigned by the test. > As all the objects won't fit in the gtt, using the allocator > does not guarantee that submitted batches won't overlap. > It only reduces the number of overlapping objects while ensuring > that evictions happen at different offsets. > > Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> > --- > tests/i915/gem_exec_gttfill.c | 75 ++++++++++++++++++++++++++++++----- > 1 file changed, 64 insertions(+), 11 deletions(-) > > diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c > index c0e27c9bb..091c74ebb 100644 > --- a/tests/i915/gem_exec_gttfill.c > +++ b/tests/i915/gem_exec_gttfill.c > @@ -28,6 +28,8 @@ > IGT_TEST_DESCRIPTION("Fill the GTT with batches."); > > #define BATCH_SIZE (4096<<10) > +/* We don't have alignment detection yet, so assume the worst-case scenario. */ > +#define BATCH_ALIGNMENT (1 << 21) > > struct batch { > uint32_t handle; > @@ -47,15 +49,21 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j) > static void submit(int fd, int gen, > struct drm_i915_gem_execbuffer2 *eb, > struct drm_i915_gem_relocation_entry *reloc, > - struct batch *batches, unsigned int count) > + struct batch *batches, unsigned int count, > + uint64_t ahnd, bool do_relocs) > { > struct drm_i915_gem_exec_object2 obj; > uint32_t batch[16]; > - unsigned n; > + uint64_t address, value; > + unsigned n, j; > > memset(&obj, 0, sizeof(obj)); > - obj.relocs_ptr = to_user_pointer(reloc); > - obj.relocation_count = 2; > + if (do_relocs) { > + obj.relocs_ptr = to_user_pointer(reloc); > + obj.relocation_count = 2; > + } else { > + obj.flags |= EXEC_OBJECT_PINNED; > + } > > memset(reloc, 0, 2*sizeof(*reloc)); > reloc[0].offset = eb->batch_start_offset; > @@ -85,16 +93,40 @@ static void submit(int fd, int gen, > batch[++n] = 0; /* lower_32_bits(value) */ > batch[++n] = 0; /* upper_32_bits(value) / nop */ > batch[++n] = MI_BATCH_BUFFER_END; > - > eb->buffers_ptr = to_user_pointer(&obj); > + j = 0; > for (unsigned i = 0; i < count; i++) { > obj.handle = batches[i].handle; > reloc[0].target_handle = obj.handle; > reloc[1].target_handle = obj.handle; > > - obj.offset = 0; > - reloc[0].presumed_offset = obj.offset; > - reloc[1].presumed_offset = obj.offset; > + if (do_relocs) { > + obj.offset = 0; > + } else { > + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, > + BATCH_SIZE, > + BATCH_ALIGNMENT, > + ALLOC_STRATEGY_HIGH_TO_LOW); > + for (; obj.offset == -1; j = ((++j) == count ? 0 : j)) { > + if (i != j) > + intel_allocator_free(ahnd, batches[j].handle); > + obj.offset = __intel_allocator_alloc(ahnd, obj.handle, > + BATCH_SIZE, > + BATCH_ALIGNMENT, > + ALLOC_STRATEGY_HIGH_TO_LOW); > + } > + > + /* If there is no relocation support, we assume gen >= 8. */ > + reloc[0].presumed_offset = obj.offset; > + address = obj.offset + reloc[0].delta; > + batch[1] = address; > + batch[2] = address >> 32; > + > + reloc[1].presumed_offset = obj.offset; > + value = obj.offset + reloc[1].delta; > + batch[3] = value; > + batch[4] = value >> 32; > + } > > memcpy(batches[i].ptr + eb->batch_start_offset, > batch, sizeof(batch)); > @@ -116,7 +148,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) > struct batch *batches; > unsigned nengine; > unsigned count; > - uint64_t size; > + uint64_t size, ahnd; > + bool do_relocs = gem_has_relocations(fd); > > shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > igt_assert(shared != MAP_FAILED); > @@ -138,6 +171,8 @@ static void fillgtt(int fd, unsigned ring, int timeout) > igt_assert(nengine * 64 <= BATCH_SIZE); > > size = gem_aperture_size(fd); > + if (!gem_uses_full_ppgtt(fd)) > + size /= 2; Chris noticed you've limited gtt size unnecessary while we want to fill it and enforce eviction. As an idea is to evict bb vma within gtt and we have full control over offsets we can limit this to few buffers and move this to gem_softpin@bb-evict to BAT (skip this for reloc gens). So leave test intact adding igt_require(gem_has_relocations()) check and add gem_softpin@bb-evict which will do eviction in narrower vm range. -- Zbigniew > if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */ > size = 1ull << 32; > igt_require(size < (1ull<<32) * BATCH_SIZE); > @@ -145,6 +180,12 @@ static void fillgtt(int fd, unsigned ring, int timeout) > count = size / BATCH_SIZE + 1; > igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n", > count, (long long)size, nengine); > + > + intel_allocator_multiprocess_start(); > + /* Avoid allocating on the last page */ > + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_HIGH_TO_LOW); > intel_require_memory(count, BATCH_SIZE, CHECK_RAM); > intel_detect_and_clear_missed_interrupts(fd); > > @@ -165,7 +206,7 @@ static void fillgtt(int fd, unsigned ring, int timeout) > } > > /* Flush all memory before we start the timer */ > - submit(fd, gen, &execbuf, reloc, batches, count); > + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); > > igt_info("Setup %u batches in %.2fms\n", > count, 1e-6 * igt_nsec_elapsed(&tv)); > @@ -176,8 +217,14 @@ static void fillgtt(int fd, unsigned ring, int timeout) > igt_permute_array(batches, count, xchg_batch); > execbuf.batch_start_offset = child*64; > execbuf.flags |= engines[child]; > + > + /* We need to open the allocator again in the new process */ > + ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_HIGH_TO_LOW); > + > igt_until_timeout(timeout) { > - submit(fd, gen, &execbuf, reloc, batches, count); > + submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs); > for (unsigned i = 0; i < count; i++) { > uint64_t offset, delta; > > @@ -189,13 +236,18 @@ static void fillgtt(int fd, unsigned ring, int timeout) > } > shared[child] = cycles; > igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles); > + intel_allocator_close(ahnd); > } > igt_waitchildren(); > > + intel_allocator_close(ahnd); > + intel_allocator_multiprocess_stop(); > + > for (unsigned i = 0; i < count; i++) { > munmap(batches[i].ptr, BATCH_SIZE); > gem_close(fd, batches[i].handle); > } > + free(batches); > > shared[nengine] = 0; > for (unsigned i = 0; i < nengine; i++) > @@ -216,6 +268,7 @@ igt_main > igt_fork_hang_detector(i915); > } > > + > igt_subtest("basic") /* just enough to run a single pass */ > fillgtt(i915, ALL_ENGINES, 1); > > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-06-09 10:42 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-05-13 5:09 [igt-dev] [PATCH i-g-t 0/2] Keep tests working without relocations Andrzej Turko 2021-05-13 5:09 ` [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens " Andrzej Turko 2021-05-13 5:09 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_exec_store: " Andrzej Turko 2021-05-13 5:56 ` [igt-dev] ✓ Fi.CI.BAT: success for Keep tests working without relocations (rev2) Patchwork 2021-05-13 8:12 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2021-06-09 10:42 [igt-dev] [PATCH v3 i-g-t 0/2] Keep tests working without relocations Andrzej Turko 2021-06-09 10:42 ` [igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens " Andrzej Turko 2021-05-12 5:40 Andrzej Turko 2021-05-12 8:14 ` Zbigniew Kempczyński 2021-05-12 9:28 ` Zbigniew Kempczyński
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