* [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms
@ 2021-04-14 2:27 Ville Syrjala
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
` (9 more replies)
0 siblings, 10 replies; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add new platform support to intel_watermark. And while at it we
pimp it with some extra WM_DBG and WM_SR_CNT goodness.
Ville Syrjälä (8):
tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues
tools/intel_watermark: Use WM_SR_CNT to observe SR residency
tools/intel_watermark: Deal with TGL planes
tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp
tools/intel_watermark: TGL+ can have 4 pipes
tools/intel_watermark: Make reg dump section less wide
tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks
tools/intel_watermark: Widen register bitfields
tools/intel_watermark.c | 335 +++++++++++++++++++++++++++++++---------
1 file changed, 259 insertions(+), 76 deletions(-)
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:31 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
` (8 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
WM_DBG has some useful sticky bits which tell us whether the
hardware has entered specific LP1+ and/or maxfifo modes since
those bits were last cleared. Let's dump those out.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 14d1ae0d80f7..bc2a46232772 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -41,6 +41,11 @@ static uint32_t read_reg(uint32_t addr)
return INREG(display_base + addr);
}
+static void write_reg(uint32_t addr, uint32_t val)
+{
+ OUTREG(display_base + addr, val);
+}
+
struct gmch_wm {
int wm, wm1, dl, fifo, fbc, burst;
bool dl_prec, valid;
@@ -249,6 +254,7 @@ static void skl_wm_dump(void)
uint32_t nv12_buf_cfg[num_pipes][max_planes];
uint32_t plane_ctl[num_pipes][max_planes];
uint32_t wm_linetime[num_pipes];
+ uint32_t wm_dbg;
intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
@@ -455,6 +461,17 @@ static void skl_wm_dump(void)
printf("* plane watermark enabled\n");
printf("(x) line watermark if enabled\n");
+
+ wm_dbg = read_reg(0x45280);
+ printf("WM_DBG: 0x%08x\n", wm_dbg);
+ printf(" LP used:");
+ for (level = 1; level < num_levels; level++) {
+ if (wm_dbg & (1 << (23 + level)))
+ printf(" LP%d", level);
+ }
+ printf("\n");
+ /* clear the sticky bits */
+ write_reg(0x45280, wm_dbg);
}
static void ilk_wm_dump(void)
@@ -608,6 +625,22 @@ static void ilk_wm_dump(void)
}
printf("FBC watermark = %s\n",
endis(!REG_DECODE1(arb_ctl, 15, 1)));
+
+ if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
+ uint32_t wm_dbg = read_reg(0x45280);
+ printf("WM_DBG: 0x%08x\n", wm_dbg);
+ if (wm_dbg & (1 << 31))
+ printf(" Full maxfifo used\n");
+ if (wm_dbg & (1 << 30))
+ printf(" Sprite maxfifo used\n");
+ printf(" LP used:");
+ for (i = 1; i < 4; i++) {
+ if (wm_dbg & (1 << (23+i)))
+ printf(" LP%d", i);
+ }
+ /* clear the sticky bits */
+ write_reg(0x45280, wm_dbg);
+ }
}
static void vlv_wm_dump(void)
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:36 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
` (7 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
WM_SR_CNT (exists since HSW) has some kind of SR residency counter,
which is nice for checking whether the watermarks work decently.
Let's use it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 53 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index bc2a46232772..39aaf9fbe055 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -35,6 +35,7 @@
static uint32_t display_base;
static uint32_t devid;
+static unsigned int sr_sleep;
static uint32_t read_reg(uint32_t addr)
{
@@ -240,6 +241,22 @@ static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane)
return reg_name;
}
+static void hsw_wm_sr_cnt(void)
+{
+ if (sr_sleep) {
+ uint32_t pre, post;
+
+ pre = read_reg(0x45264);
+ sleep(sr_sleep);
+ post = read_reg(0x45264);
+
+ printf("WM_SR_CNT: 0x%08x->0x%08x\n", pre, post);
+ printf("SR residency: %u%%\n", ((post - pre) * 8 / (sr_sleep * 10000)));
+ } else {
+ printf("WM_SR_CNT: 0x%08x\n", read_reg(0x45264));
+ }
+}
+
static void skl_wm_dump(void)
{
struct intel_mmio_data mmio_data;
@@ -462,6 +479,8 @@ static void skl_wm_dump(void)
printf("* plane watermark enabled\n");
printf("(x) line watermark if enabled\n");
+ hsw_wm_sr_cnt();
+
wm_dbg = read_reg(0x45280);
printf("WM_DBG: 0x%08x\n", wm_dbg);
printf(" LP used:");
@@ -627,7 +646,11 @@ static void ilk_wm_dump(void)
endis(!REG_DECODE1(arb_ctl, 15, 1)));
if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
- uint32_t wm_dbg = read_reg(0x45280);
+ uint32_t wm_dbg;
+
+ hsw_wm_sr_cnt();
+
+ wm_dbg = read_reg(0x45280);
printf("WM_DBG: 0x%08x\n", wm_dbg);
if (wm_dbg & (1 << 31))
printf(" Full maxfifo used\n");
@@ -1265,10 +1288,38 @@ static void gen2_wm_dump(void)
}
}
+static void __attribute__((noreturn)) usage(const char *name)
+{
+ fprintf(stderr, "Usage: %s [options]\n"
+ " -s,--sr-sleep <seconds>\n",
+ name);
+ exit(1);
+}
+
int main(int argc, char *argv[])
{
devid = intel_get_pci_device()->device_id;
+ for (;;) {
+ static const struct option long_options[] = {
+ { .name = "sr-sleep", .has_arg = required_argument, },
+ {}
+ };
+
+ int opt = getopt_long(argc, argv, "s:", long_options, NULL);
+ if (opt == -1)
+ break;
+
+ switch (opt) {
+ case 's':
+ sr_sleep = atoi(optarg);
+ break;
+ default:
+ usage(argv[0]);
+ break;
+ }
+ }
+
if (intel_gen(devid) >= 9) {
skl_wm_dump();
} else if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) {
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:47 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
` (6 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
TGL has the same amount of planes as ICL. Make intel_watermark
aware of that fact.
v2: Use intel_gen()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 39aaf9fbe055..4a5764b59677 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -133,9 +133,11 @@ static char endis_ast(bool enabled)
static int skl_num_planes(uint32_t d, int pipe)
{
- if (IS_GEN11(d))
+ int gen = intel_gen(d);
+
+ if (gen >= 11)
return 8;
- else if (IS_GEN10(d) || IS_GEMINILAKE(d))
+ else if (gen == 10 || IS_GEMINILAKE(d))
return 5;
else if (IS_BROXTON(d))
return pipe == 2 ? 4 : 5;
@@ -145,9 +147,11 @@ static int skl_num_planes(uint32_t d, int pipe)
static int skl_max_planes(uint32_t d)
{
- if (IS_GEN11(d))
+ int gen = intel_gen(d);
+
+ if (gen >= 11)
return 8;
- else if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d))
+ else if (gen == 10 || IS_GEMINILAKE(d) || IS_BROXTON(d))
return 5;
else
return 4;
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
` (2 preceding siblings ...)
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:53 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
` (5 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Modern platforms have just 5 universal planes + cursor per pipe..
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 4a5764b59677..ff373fdb0c6d 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -135,7 +135,9 @@ static int skl_num_planes(uint32_t d, int pipe)
{
int gen = intel_gen(d);
- if (gen >= 11)
+ if (gen >= 13 || IS_ALDERLAKE_S(d) || IS_ROCKETLAKE(d))
+ return 6;
+ else if (gen >= 11)
return 8;
else if (gen == 10 || IS_GEMINILAKE(d))
return 5;
@@ -149,7 +151,9 @@ static int skl_max_planes(uint32_t d)
{
int gen = intel_gen(d);
- if (gen >= 11)
+ if (gen >= 13 || IS_ALDERLAKE_S(d) || IS_ROCKETLAKE(d))
+ return 6;
+ else if (gen >= 11)
return 8;
else if (gen == 10 || IS_GEMINILAKE(d) || IS_BROXTON(d))
return 5;
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
` (3 preceding siblings ...)
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:53 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
` (4 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Decode pipe D watermark stuff too.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index ff373fdb0c6d..657fff20ec7a 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -131,6 +131,11 @@ static char endis_ast(bool enabled)
return enabled ? '*' : ' ';
}
+static int skl_num_pipes(uint32_t d)
+{
+ return intel_gen(d) >= 12 ? 4 : 3;
+}
+
static int skl_num_planes(uint32_t d, int pipe)
{
int gen = intel_gen(d);
@@ -269,7 +274,7 @@ static void skl_wm_dump(void)
{
struct intel_mmio_data mmio_data;
int pipe, plane, level;
- int num_pipes = 3;
+ int num_pipes = skl_num_pipes(devid);
int max_planes = skl_max_planes(devid);
int num_levels = 8;
uint32_t base_addr = 0x70000, addr, wm_offset;
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
` (4 preceding siblings ...)
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:50 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
` (3 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Don't repeat the register name for each pipe to make the
register dump portion a bit less wide.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 98 ++++++++++++++++++-----------------------
1 file changed, 43 insertions(+), 55 deletions(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 657fff20ec7a..31ce165f282b 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -166,90 +166,80 @@ static int skl_max_planes(uint32_t d)
return 4;
}
-static const char *skl_plane_name(int pipe, int plane)
+static const char *skl_plane_name(int plane)
{
static char name[32];
if (plane == 0)
snprintf(name, sizeof(name), "CURSOR");
else
- snprintf(name, sizeof(name), "PLANE_%1d%c",
- plane, pipe_name(pipe));
+ snprintf(name, sizeof(name), "PLANE_%1d", plane);
return name;
}
-static const char *skl_wm_linetime_reg_name(int pipe)
+static const char *skl_wm_linetime_reg_name(void)
{
static char reg_name[32];
- snprintf(reg_name, sizeof(reg_name), "WM_LINETIME_%c",
- pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "WM_LINETIME");
return reg_name;
}
-static const char *skl_plane_ctl_reg_name(int pipe, int plane)
+static const char *skl_plane_ctl_reg_name(int plane)
{
static char reg_name[32];
if (plane == 0)
- snprintf(reg_name, sizeof(reg_name), "CUR_CTL_%c",
- pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "CUR_CTL");
else
- snprintf(reg_name, sizeof(reg_name), "PLANE_CTL_%1d_%c",
- plane, pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "PLANE_CTL_%1d", plane);
return reg_name;
}
-static const char *skl_wm_reg_name(int pipe, int plane, int level)
+static const char *skl_wm_reg_name(int plane, int level)
{
static char reg_name[32];
if (plane == 0)
- snprintf(reg_name, sizeof(reg_name), "CUR_WM_%c_%1d",
- pipe_name(pipe), level);
+ snprintf(reg_name, sizeof(reg_name), "CUR_WM_%1d", level);
else
- snprintf(reg_name, sizeof(reg_name), "PLANE_WM_%1d_%c_%1d",
- plane, pipe_name(pipe), level);
+ snprintf(reg_name, sizeof(reg_name), "PLANE_WM_%1d_%1d", plane, level);
return reg_name;
}
-static const char *skl_wm_trans_reg_name(int pipe, int plane)
+static const char *skl_wm_trans_reg_name(int plane)
{
static char reg_name[32];
if (plane == 0)
- snprintf(reg_name, sizeof(reg_name), "CUR_WM_TRANS_%c",
- pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "CUR_WM_TRANS");
else
- snprintf(reg_name, sizeof(reg_name), "PLANE_WM_TRANS_%1d_%c",
- plane, pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "PLANE_WM_TRANS_%1d", plane);
+
return reg_name;
}
-static const char *skl_buf_cfg_reg_name(int pipe, int plane)
+static const char *skl_buf_cfg_reg_name(int plane)
{
static char reg_name[32];
if (plane == 0)
- snprintf(reg_name, sizeof(reg_name), "CUR_BUF_CFG_%c",
- pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "CUR_BUF_CFG");
else
- snprintf(reg_name, sizeof(reg_name), "PLANE_BUF_CFG_%1d_%c",
- plane, pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "PLANE_BUF_CFG_%1d", plane);
return reg_name;
}
-static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane)
+static const char *skl_nv12_buf_cfg_reg_name(int plane)
{
static char reg_name[32];
- snprintf(reg_name, sizeof(reg_name), "PLANE_NV12_BUF_CFG_%1d_%c",
- plane, pipe_name(pipe));
+ snprintf(reg_name, sizeof(reg_name), "PLANE_NV12_BUF_CFG_%1d", plane);
return reg_name;
}
@@ -310,21 +300,23 @@ static void skl_wm_dump(void)
}
}
- for (pipe = 0; pipe < num_pipes; pipe++) {
- printf("%18s 0x%08x\t",
- skl_wm_linetime_reg_name(pipe),
- wm_linetime[pipe]);
- }
+ printf("%21c\t", '\0');
+ for (pipe = 0; pipe < num_pipes; pipe++)
+ printf("PIPE_%-5c\t", pipe_name(pipe));
+ printf("\n\n");
+
+ printf("%21s\t", skl_wm_linetime_reg_name());
+ for (pipe = 0; pipe < num_pipes; pipe++)
+ printf("0x%08x\t", wm_linetime[pipe]);
printf("\n\n");
for (plane = 0; plane < max_planes; plane++) {
+ printf("%21s\t", skl_plane_ctl_reg_name(plane));
+
for (pipe = 0; pipe < num_pipes; pipe++) {
if (plane >= skl_num_planes(devid, pipe))
break;
-
- printf("%18s 0x%08x\t" ,
- skl_plane_ctl_reg_name(pipe, plane),
- plane_ctl[pipe][plane]);
+ printf("0x%08x\t" , plane_ctl[pipe][plane]);
}
printf("\n");
}
@@ -332,13 +324,12 @@ static void skl_wm_dump(void)
for (plane = 0; plane < max_planes; plane++) {
for (level = 0; level < num_levels; level++) {
+ printf("%21s\t", skl_wm_reg_name(plane, level));
+
for (pipe = 0; pipe < num_pipes; pipe++) {
if (plane >= skl_num_planes(devid, pipe))
break;
-
- printf("%18s 0x%08x\t" ,
- skl_wm_reg_name(pipe, plane, level),
- wm[level][pipe][plane]);
+ printf("0x%08x\t", wm[level][pipe][plane]);
}
printf("\n");
}
@@ -346,26 +337,24 @@ static void skl_wm_dump(void)
}
for (plane = 0; plane < max_planes; plane++) {
+ printf("%21s\t", skl_wm_trans_reg_name(plane));
+
for (pipe = 0; pipe < num_pipes; pipe++) {
if (plane >= skl_num_planes(devid, pipe))
break;
-
- printf("%18s 0x%08x\t",
- skl_wm_trans_reg_name(pipe, plane),
- wm_trans[pipe][plane]);
+ printf("0x%08x\t", wm_trans[pipe][plane]);
}
printf("\n");
}
printf("\n");
for (plane = 0; plane < max_planes; plane++) {
+ printf("%21s\t", skl_buf_cfg_reg_name(plane));
+
for (pipe = 0; pipe < num_pipes; pipe++) {
if (plane >= skl_num_planes(devid, pipe))
break;
-
- printf("%18s 0x%08x\t",
- skl_buf_cfg_reg_name(pipe, plane),
- buf_cfg[pipe][plane]);
+ printf("0x%08x\t", buf_cfg[pipe][plane]);
}
printf("\n");
@@ -375,13 +364,12 @@ static void skl_wm_dump(void)
if (plane == 0)
continue;
+ printf("%21s\t", skl_nv12_buf_cfg_reg_name(plane));
+
for (pipe = 0; pipe < num_pipes; pipe++) {
if (plane >= skl_num_planes(devid, pipe))
break;
-
- printf("%18s 0x%08x\t",
- skl_nv12_buf_cfg_reg_name(pipe, plane),
- nv12_buf_cfg[pipe][plane]);
+ printf("0x%08x\t", nv12_buf_cfg[pipe][plane]);
}
printf("\n");
}
@@ -405,7 +393,7 @@ static void skl_wm_dump(void)
REG_DECODE1(plane_ctl[pipe][plane], 5, 1);
else
enable = REG_DECODE1(plane_ctl[pipe][plane], 31, 1);
- printf("%9s%c", skl_plane_name(pipe, plane),
+ printf("%9s%c", skl_plane_name(plane),
endis_ast(enable));
}
printf("\n");
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
` (5 preceding siblings ...)
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:51 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
` (2 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ADL-P introduces dedicated SAGV watermark registers. Decode them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 106 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 102 insertions(+), 4 deletions(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 31ce165f282b..f5613c333dc3 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -166,6 +166,19 @@ static int skl_max_planes(uint32_t d)
return 4;
}
+static bool skl_has_sagv_wm(uint32_t d)
+{
+ return intel_gen(d) >= 13;
+}
+
+static int skl_num_wm_levels(uint32_t d)
+{
+ if (skl_has_sagv_wm(d))
+ return 6;
+ else
+ return 8;
+}
+
static const char *skl_plane_name(int plane)
{
static char name[32];
@@ -223,6 +236,30 @@ static const char *skl_wm_trans_reg_name(int plane)
return reg_name;
}
+static const char *skl_wm_sagv_reg_name(int plane)
+{
+ static char reg_name[32];
+
+ if (plane == 0)
+ snprintf(reg_name, sizeof(reg_name), "CUR_WM_SAGV");
+ else
+ snprintf(reg_name, sizeof(reg_name), "PLANE_WM_SAGV_%1d", plane);
+
+ return reg_name;
+}
+
+static const char *skl_wm_sagv_trans_reg_name(int plane)
+{
+ static char reg_name[32];
+
+ if (plane == 0)
+ snprintf(reg_name, sizeof(reg_name), "CUR_WM_SAGV_TRANS");
+ else
+ snprintf(reg_name, sizeof(reg_name), "PLANE_WM_SAGV_TRANS_%1d", plane);
+
+ return reg_name;
+}
+
static const char *skl_buf_cfg_reg_name(int plane)
{
static char reg_name[32];
@@ -266,10 +303,12 @@ static void skl_wm_dump(void)
int pipe, plane, level;
int num_pipes = skl_num_pipes(devid);
int max_planes = skl_max_planes(devid);
- int num_levels = 8;
+ int num_levels = skl_num_wm_levels(devid);
uint32_t base_addr = 0x70000, addr, wm_offset;
uint32_t wm[num_levels][num_pipes][max_planes];
uint32_t wm_trans[num_pipes][max_planes];
+ uint32_t wm_sagv[num_pipes][max_planes];
+ uint32_t wm_sagv_trans[num_pipes][max_planes];
uint32_t buf_cfg[num_pipes][max_planes];
uint32_t nv12_buf_cfg[num_pipes][max_planes];
uint32_t plane_ctl[num_pipes][max_planes];
@@ -297,6 +336,11 @@ static void skl_wm_dump(void)
wm_offset = addr + 0x00140 + level * 0x4;
wm[level][pipe][plane] = read_reg(wm_offset);
}
+
+ if (skl_has_sagv_wm(devid)) {
+ wm_sagv[pipe][plane] = read_reg(addr + 0x00158);
+ wm_sagv_trans[pipe][plane] = read_reg(addr + 0x0015c);
+ }
}
}
@@ -348,6 +392,32 @@ static void skl_wm_dump(void)
}
printf("\n");
+ if (skl_has_sagv_wm(devid)) {
+ for (plane = 0; plane < max_planes; plane++) {
+ printf("%21s\t", skl_wm_sagv_reg_name(plane));
+
+ for (pipe = 0; pipe < num_pipes; pipe++) {
+ if (plane >= skl_num_planes(devid, pipe))
+ break;
+ printf("0x%08x\t", wm_sagv[pipe][plane]);
+ }
+ printf("\n");
+ }
+ printf("\n");
+
+ for (plane = 0; plane < max_planes; plane++) {
+ printf("%21s\t", skl_wm_sagv_trans_reg_name(plane));
+
+ for (pipe = 0; pipe < num_pipes; pipe++) {
+ if (plane >= skl_num_planes(devid, pipe))
+ break;
+ printf("0x%08x\t", wm_sagv_trans[pipe][plane]);
+ }
+ printf("\n");
+ }
+ printf("\n");
+ }
+
for (plane = 0; plane < max_planes; plane++) {
printf("%21s\t", skl_buf_cfg_reg_name(plane));
@@ -386,7 +456,7 @@ static void skl_wm_dump(void)
linetime = REG_DECODE1(wm_linetime[pipe], 0, 9);
printf("LINETIME: %d (%.3f usec)\n", linetime, linetime* 0.125f);
- printf("LEVEL");
+ printf(" LEVEL");
for (plane = 0; plane < num_planes; plane++) {
if (plane == 0)
enable = REG_DECODE1(plane_ctl[pipe][plane], 0, 3) ||
@@ -399,7 +469,7 @@ static void skl_wm_dump(void)
printf("\n");
for (level = 0; level < num_levels; level++) {
- printf("%5d", level);
+ printf("%10d", level);
for (plane = 0; plane < num_planes; plane++) {
blocks = REG_DECODE1(wm[level][pipe][plane], 0, 11);
lines = REG_DECODE1(wm[level][pipe][plane], 14, 5);
@@ -414,7 +484,7 @@ static void skl_wm_dump(void)
printf("\n");
}
- printf("TRANS");
+ printf(" TRANS");
for (plane = 0; plane < num_planes; plane++) {
blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 11);
lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5);
@@ -427,6 +497,34 @@ static void skl_wm_dump(void)
printf("(--)");
}
+ if (skl_has_sagv_wm(devid)) {
+ printf("\n SAGV");
+ for (plane = 0; plane < num_planes; plane++) {
+ blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 11);
+ lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 5);
+ enable = REG_DECODE1(wm_sagv[pipe][plane], 31, 1);
+
+ printf("%5d%c", blocks, endis_ast(enable));
+ if (!REG_DECODE1(wm_sagv[pipe][plane], 30, 1))
+ printf("(%2d)", lines);
+ else
+ printf("(--)");
+ }
+
+ printf("\nSAGV TRANS");
+ for (plane = 0; plane < num_planes; plane++) {
+ blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 11);
+ lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 5);
+ enable = REG_DECODE1(wm_sagv_trans[pipe][plane], 31, 1);
+
+ printf("%5d%c", blocks, endis_ast(enable));
+ if (!REG_DECODE1(wm_sagv_trans[pipe][plane], 30, 1))
+ printf("(%2d)", lines);
+ else
+ printf("(--)");
+ }
+ }
+
printf("\nDDB allocation:");
printf("\nstart");
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
` (6 preceding siblings ...)
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
@ 2021-04-14 2:27 ` Ville Syrjala
2021-05-14 9:51 ` Lisovskiy, Stanislav
2021-04-14 3:04 ` [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms Patchwork
2021-04-14 4:01 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 1 reply; 19+ messages in thread
From: Ville Syrjala @ 2021-04-14 2:27 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Modern platforms have more bits in the registers. Deal with it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/intel_watermark.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index f5613c333dc3..1e235ed30a63 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -471,8 +471,8 @@ static void skl_wm_dump(void)
for (level = 0; level < num_levels; level++) {
printf("%10d", level);
for (plane = 0; plane < num_planes; plane++) {
- blocks = REG_DECODE1(wm[level][pipe][plane], 0, 11);
- lines = REG_DECODE1(wm[level][pipe][plane], 14, 5);
+ blocks = REG_DECODE1(wm[level][pipe][plane], 0, 12);
+ lines = REG_DECODE1(wm[level][pipe][plane], 14, 13);
enable = REG_DECODE1(wm[level][pipe][plane], 31, 1);
printf("%5d%c", blocks, endis_ast(enable));
@@ -486,8 +486,8 @@ static void skl_wm_dump(void)
printf(" TRANS");
for (plane = 0; plane < num_planes; plane++) {
- blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 11);
- lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5);
+ blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 12);
+ lines = REG_DECODE1(wm_trans[pipe][plane], 14, 13);
enable = REG_DECODE1(wm_trans[pipe][plane], 31, 1);
printf("%5d%c", blocks, endis_ast(enable));
@@ -500,8 +500,8 @@ static void skl_wm_dump(void)
if (skl_has_sagv_wm(devid)) {
printf("\n SAGV");
for (plane = 0; plane < num_planes; plane++) {
- blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 11);
- lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 5);
+ blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 12);
+ lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 13);
enable = REG_DECODE1(wm_sagv[pipe][plane], 31, 1);
printf("%5d%c", blocks, endis_ast(enable));
@@ -513,8 +513,8 @@ static void skl_wm_dump(void)
printf("\nSAGV TRANS");
for (plane = 0; plane < num_planes; plane++) {
- blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 11);
- lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 5);
+ blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 12);
+ lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 13);
enable = REG_DECODE1(wm_sagv_trans[pipe][plane], 31, 1);
printf("%5d%c", blocks, endis_ast(enable));
@@ -529,20 +529,20 @@ static void skl_wm_dump(void)
printf("\nstart");
for (plane = 0; plane < num_planes; plane++) {
- start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
+ start = REG_DECODE1(buf_cfg[pipe][plane], 0, 12);
printf("%10d", start);
}
printf("\n end");
for (plane = 0; plane < num_planes; plane++) {
- end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
+ end = REG_DECODE1(buf_cfg[pipe][plane], 16, 12);
printf("%10d", end);
}
printf("\n size");
for (plane = 0; plane < num_planes; plane++) {
- start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
- end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
+ start = REG_DECODE1(buf_cfg[pipe][plane], 0, 12);
+ end = REG_DECODE1(buf_cfg[pipe][plane], 16, 12);
size = end - start + 1;
printf("%10d", (end == 0 && size == 1) ? 0 : size);
}
@@ -553,20 +553,20 @@ static void skl_wm_dump(void)
printf("\nstart");
for (plane = 0; plane < num_planes; plane++) {
- start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
+ start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 12);
printf("%10d", start);
}
printf("\n end");
for (plane = 0; plane < num_planes; plane++) {
- end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
+ end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 12);
printf("%10d", end);
}
printf("\n size");
for (plane = 0; plane < num_planes; plane++) {
- start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
- end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
+ start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 12);
+ end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 12);
size = end - start + 1;
printf("%10d", (end == 0 && size == 1) ? 0 : size);
}
--
2.26.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
` (7 preceding siblings ...)
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
@ 2021-04-14 3:04 ` Patchwork
2021-04-14 4:01 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-04-14 3:04 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 4157 bytes --]
== Series Details ==
Series: tools/intel_watermark: Support new platofrms
URL : https://patchwork.freedesktop.org/series/89037/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9966 -> IGTPW_5740
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/index.html
Known issues
------------
Here are the changes found in IGTPW_5740 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-icl-y/igt@amdgpu/amd_basic@semaphore.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-y: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-icl-y/igt@gem_huc_copy@huc-copy.html
* igt@i915_module_load@reload:
- fi-kbl-soraka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/fi-kbl-soraka/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-kbl-soraka/igt@i915_module_load@reload.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-y: NOTRUN -> [SKIP][5] ([fdo#109284] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-icl-y/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-y: NOTRUN -> [SKIP][6] ([fdo#109285])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-icl-y/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-y: NOTRUN -> [SKIP][7] ([fdo#109278])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-icl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-icl-y: NOTRUN -> [SKIP][8] ([fdo#110189]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-icl-y: NOTRUN -> [SKIP][9] ([i915#3301])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-icl-y/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-tgl-y: [DMESG-WARN][10] ([i915#1982] / [k.org#205379]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/fi-tgl-y/igt@i915_module_load@reload.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/fi-tgl-y/igt@i915_module_load@reload.html
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (46 -> 40)
------------------------------
Additional (1): fi-icl-y
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-dg1-1 fi-bsw-kefka fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6064 -> IGTPW_5740
CI-20190529: 20190529
CI_DRM_9966: 0f7f5236775ef3b8bb2ed5ba456797850f0c4e93 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5740: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/index.html
IGT_6064: 48d89e2c65c54883b0776930a884e6d3bcefb45b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/index.html
[-- Attachment #1.2: Type: text/html, Size: 5027 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for tools/intel_watermark: Support new platofrms
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
` (8 preceding siblings ...)
2021-04-14 3:04 ` [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms Patchwork
@ 2021-04-14 4:01 ` Patchwork
9 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-04-14 4:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 30262 bytes --]
== Series Details ==
Series: tools/intel_watermark: Support new platofrms
URL : https://patchwork.freedesktop.org/series/89037/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9966_full -> IGTPW_5740_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/index.html
Known issues
------------
Here are the changes found in IGTPW_5740_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@clone:
- shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +6 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-snb7/igt@gem_ctx_persistence@clone.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][2] -> [TIMEOUT][3] ([i915#2369] / [i915#2481] / [i915#3070])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb1/igt@gem_eio@unwedge-stress.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk8/igt@gem_exec_fair@basic-none@vecs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk4/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][8] ([fdo#109283])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb7/igt@gem_exec_params@no-blt.html
- shard-iclb: NOTRUN -> [SKIP][9] ([fdo#109283])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb5/igt@gem_exec_params@no-blt.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl: NOTRUN -> [FAIL][10] ([i915#2389]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl1/igt@gem_exec_reloc@basic-wide-active@bcs0.html
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([i915#1895])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb3/igt@gem_exec_whisper@basic-queues-priority-all.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority-all.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2428])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb6/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl4/igt@gem_pwrite@basic-exhaustion.html
- shard-apl: NOTRUN -> [WARN][16] ([i915#2658])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl7/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#1699]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl2/igt@gem_userptr_blits@process-exit-mmap-busy@uc.html
* igt@gem_userptr_blits@set-cache-level:
- shard-apl: NOTRUN -> [FAIL][18] ([i915#3324])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl2/igt@gem_userptr_blits@set-cache-level.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][19] ([i915#2724])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-snb6/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#112306])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb6/igt@gen9_exec_parse@batch-zero-length.html
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#112306])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb6/igt@gen9_exec_parse@batch-zero-length.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][22] -> [INCOMPLETE][23] ([i915#2782])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-snb5/igt@i915_selftest@live@hangcheck.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-tglb: NOTRUN -> [SKIP][24] ([fdo#111615]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_joiner@invalid-modeset:
- shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#2705])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl2/igt@kms_big_joiner@invalid-modeset.html
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2705])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl1/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_chamelium@dp-frame-dump:
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109284] / [fdo#111827]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb1/igt@kms_chamelium@dp-frame-dump.html
- shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk1/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_chamelium@dp-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +6 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl7/igt@kms_chamelium@dp-hpd-for-each-pipe.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +19 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#109284] / [fdo#111827]) +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb6/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +22 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][33] ([i915#1319]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl7/igt@kms_content_protection@atomic-dpms.html
- shard-kbl: NOTRUN -> [TIMEOUT][34] ([i915#1319])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl4/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-iclb: NOTRUN -> [SKIP][35] ([i915#3116])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb4/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-tglb: NOTRUN -> [SKIP][36] ([i915#3116])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb5/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][37] ([i915#2105])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl8/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#3319]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +4 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#109278]) +7 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb2/igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271]) +366 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-snb5/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][43] -> [FAIL][44] ([i915#72])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109274] / [fdo#109278]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb1/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
- shard-glk: [PASS][46] -> [FAIL][47] ([i915#52] / [i915#54]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk2/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html
* igt@kms_flip@2x-flip-vs-panning-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][48] -> [DMESG-WARN][49] ([i915#118] / [i915#95]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk4/igt@kms_flip@2x-flip-vs-panning-interruptible@bc-hdmi-a1-hdmi-a2.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk8/igt@kms_flip@2x-flip-vs-panning-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109274])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb6/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [PASS][51] -> [FAIL][52] ([i915#79])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-kbl: NOTRUN -> [FAIL][53] ([i915#2641])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
- shard-tglb: NOTRUN -> [SKIP][54] ([i915#2587])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
- shard-glk: NOTRUN -> [FAIL][55] ([i915#2628])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
- shard-apl: NOTRUN -> [FAIL][56] ([i915#2641])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#2672])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#2642])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2672])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +9 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
- shard-tglb: NOTRUN -> [SKIP][61] ([fdo#111825]) +12 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109289])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb8/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109289])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb6/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
- shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
- shard-apl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
- shard-kbl: NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][70] ([i915#265])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2733])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +5 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
- shard-glk: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#658])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#658]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109642] / [fdo#111068] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb8/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][77] -> [SKIP][78] ([fdo#109441]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][79] ([IGT#2])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl2/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][80] -> [DMESG-WARN][81] ([i915#180] / [i915#295])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][82] -> [DMESG-WARN][83] ([i915#180])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-apl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271]) +245 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl1/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#2530]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb1/igt@nouveau_crc@pipe-a-source-rg.html
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#2530]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb3/igt@nouveau_crc@pipe-a-source-rg.html
* igt@perf@polling-parameterized:
- shard-iclb: [PASS][87] -> [FAIL][88] ([i915#1542])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb8/igt@perf@polling-parameterized.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb2/igt@perf@polling-parameterized.html
* igt@prime_nv_pcopy@test2:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271]) +116 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl6/igt@prime_nv_pcopy@test2.html
* igt@prime_nv_pcopy@test3_3:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109291])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb6/igt@prime_nv_pcopy@test3_3.html
- shard-glk: NOTRUN -> [SKIP][91] ([fdo#109271]) +25 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk1/igt@prime_nv_pcopy@test3_3.html
- shard-tglb: NOTRUN -> [SKIP][92] ([fdo#109291])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb6/igt@prime_nv_pcopy@test3_3.html
* igt@prime_vgem@coherency-blt:
- shard-glk: [PASS][93] -> [INCOMPLETE][94] ([i915#2944])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk4/igt@prime_vgem@coherency-blt.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk7/igt@prime_vgem@coherency-blt.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl2/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@pidname:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994]) +4 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl2/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@gem_create@create-clear:
- shard-glk: [FAIL][97] ([i915#1888] / [i915#3160]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk4/igt@gem_create@create-clear.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk2/igt@gem_create@create-clear.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][99] ([i915#2369] / [i915#3063]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-tglb3/igt@gem_eio@unwedge-stress.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][101] ([i915#2846]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][103] ([i915#2842]) -> [PASS][104] +2 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][105] ([i915#2842]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [FAIL][107] ([i915#2842]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [SKIP][109] ([fdo#109271]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [DMESG-WARN][111] ([i915#118] / [i915#95]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk4/igt@gem_exec_whisper@basic-queues-forked-all.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk5/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_mmap_gtt@big-copy-xy:
- shard-glk: [FAIL][113] ([i915#307]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk7/igt@gem_mmap_gtt@big-copy-xy.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk2/igt@gem_mmap_gtt@big-copy-xy.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [FAIL][115] ([i915#307]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb2/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][117] ([i915#180]) -> [PASS][118] +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [FAIL][119] ([i915#2574]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-tglb8/igt@kms_async_flips@test-time-stamp.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-tglb6/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-WARN][121] ([i915#180]) -> [PASS][122] +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-glk: [FAIL][123] ([i915#52] / [i915#54]) -> [PASS][124] +4 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk2/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk3/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][125] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][127] ([fdo#109441]) -> [PASS][128] +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-glk: [FAIL][129] ([i915#43]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-glk5/igt@kms_vblank@pipe-b-accuracy-idle.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-glk6/igt@kms_vblank@pipe-b-accuracy-idle.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [INCOMPLETE][131] ([i915#155] / [i915#2828] / [i915#794]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][133] ([fdo#109271]) -> [FAIL][134] ([i915#2842])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][135] ([i915#2684]) -> [WARN][136] ([i915#2681] / [i915#2684])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][137] ([i915#1804] / [i915#2684]) -> [WARN][138] ([i915#2684])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][139] ([fdo#109349]) -> [DMESG-WARN][140] ([i915#1226])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-iclb: [SKIP][141] ([i915#658]) -> [SKIP][142] ([i915#2920])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][143] ([i915#2920]) -> [SKIP][144] ([i915#658]) +1 similar issue
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9966/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151]) ([i915#180] / [i915#2505] / [i915#3002] / [i915#92]) -> ([FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#602])
[145]: https://intel-gfx-ci.01.org/tree/drm
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5740/index.html
[-- Attachment #1.2: Type: text/html, Size: 33575 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
@ 2021-05-14 9:31 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:47AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WM_DBG has some useful sticky bits which tell us whether the
> hardware has entered specific LP1+ and/or maxfifo modes since
> those bits were last cleared. Let's dump those out.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
> ---
> tools/intel_watermark.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 14d1ae0d80f7..bc2a46232772 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -41,6 +41,11 @@ static uint32_t read_reg(uint32_t addr)
> return INREG(display_base + addr);
> }
>
> +static void write_reg(uint32_t addr, uint32_t val)
> +{
> + OUTREG(display_base + addr, val);
> +}
> +
> struct gmch_wm {
> int wm, wm1, dl, fifo, fbc, burst;
> bool dl_prec, valid;
> @@ -249,6 +254,7 @@ static void skl_wm_dump(void)
> uint32_t nv12_buf_cfg[num_pipes][max_planes];
> uint32_t plane_ctl[num_pipes][max_planes];
> uint32_t wm_linetime[num_pipes];
> + uint32_t wm_dbg;
>
> intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
>
> @@ -455,6 +461,17 @@ static void skl_wm_dump(void)
>
> printf("* plane watermark enabled\n");
> printf("(x) line watermark if enabled\n");
> +
> + wm_dbg = read_reg(0x45280);
> + printf("WM_DBG: 0x%08x\n", wm_dbg);
> + printf(" LP used:");
> + for (level = 1; level < num_levels; level++) {
> + if (wm_dbg & (1 << (23 + level)))
> + printf(" LP%d", level);
> + }
> + printf("\n");
> + /* clear the sticky bits */
> + write_reg(0x45280, wm_dbg);
> }
>
> static void ilk_wm_dump(void)
> @@ -608,6 +625,22 @@ static void ilk_wm_dump(void)
> }
> printf("FBC watermark = %s\n",
> endis(!REG_DECODE1(arb_ctl, 15, 1)));
> +
> + if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
> + uint32_t wm_dbg = read_reg(0x45280);
> + printf("WM_DBG: 0x%08x\n", wm_dbg);
> + if (wm_dbg & (1 << 31))
> + printf(" Full maxfifo used\n");
> + if (wm_dbg & (1 << 30))
> + printf(" Sprite maxfifo used\n");
> + printf(" LP used:");
> + for (i = 1; i < 4; i++) {
> + if (wm_dbg & (1 << (23+i)))
> + printf(" LP%d", i);
> + }
> + /* clear the sticky bits */
> + write_reg(0x45280, wm_dbg);
> + }
> }
>
> static void vlv_wm_dump(void)
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
@ 2021-05-14 9:36 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:36 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:48AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> WM_SR_CNT (exists since HSW) has some kind of SR residency counter,
> which is nice for checking whether the watermarks work decently.
> Let's use it.
As I understood this is just somekind of a counter which indicates,
how long we kept memory awake.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/intel_watermark.c | 53 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index bc2a46232772..39aaf9fbe055 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -35,6 +35,7 @@
>
> static uint32_t display_base;
> static uint32_t devid;
> +static unsigned int sr_sleep;
>
> static uint32_t read_reg(uint32_t addr)
> {
> @@ -240,6 +241,22 @@ static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane)
> return reg_name;
> }
>
> +static void hsw_wm_sr_cnt(void)
> +{
> + if (sr_sleep) {
> + uint32_t pre, post;
> +
> + pre = read_reg(0x45264);
> + sleep(sr_sleep);
> + post = read_reg(0x45264);
> +
> + printf("WM_SR_CNT: 0x%08x->0x%08x\n", pre, post);
> + printf("SR residency: %u%%\n", ((post - pre) * 8 / (sr_sleep * 10000)));
> + } else {
> + printf("WM_SR_CNT: 0x%08x\n", read_reg(0x45264));
> + }
> +}
> +
> static void skl_wm_dump(void)
> {
> struct intel_mmio_data mmio_data;
> @@ -462,6 +479,8 @@ static void skl_wm_dump(void)
> printf("* plane watermark enabled\n");
> printf("(x) line watermark if enabled\n");
>
> + hsw_wm_sr_cnt();
> +
> wm_dbg = read_reg(0x45280);
> printf("WM_DBG: 0x%08x\n", wm_dbg);
> printf(" LP used:");
> @@ -627,7 +646,11 @@ static void ilk_wm_dump(void)
> endis(!REG_DECODE1(arb_ctl, 15, 1)));
>
> if (IS_BROADWELL(devid) || IS_HASWELL(devid)) {
> - uint32_t wm_dbg = read_reg(0x45280);
> + uint32_t wm_dbg;
> +
> + hsw_wm_sr_cnt();
> +
> + wm_dbg = read_reg(0x45280);
> printf("WM_DBG: 0x%08x\n", wm_dbg);
> if (wm_dbg & (1 << 31))
> printf(" Full maxfifo used\n");
> @@ -1265,10 +1288,38 @@ static void gen2_wm_dump(void)
> }
> }
>
> +static void __attribute__((noreturn)) usage(const char *name)
> +{
> + fprintf(stderr, "Usage: %s [options]\n"
> + " -s,--sr-sleep <seconds>\n",
> + name);
> + exit(1);
> +}
> +
> int main(int argc, char *argv[])
> {
> devid = intel_get_pci_device()->device_id;
>
> + for (;;) {
> + static const struct option long_options[] = {
> + { .name = "sr-sleep", .has_arg = required_argument, },
> + {}
> + };
> +
> + int opt = getopt_long(argc, argv, "s:", long_options, NULL);
> + if (opt == -1)
> + break;
> +
> + switch (opt) {
> + case 's':
> + sr_sleep = atoi(optarg);
> + break;
> + default:
> + usage(argv[0]);
> + break;
> + }
> + }
> +
> if (intel_gen(devid) >= 9) {
> skl_wm_dump();
> } else if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) {
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
@ 2021-05-14 9:47 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:49AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> TGL has the same amount of planes as ICL. Make intel_watermark
> aware of that fact.
>
> v2: Use intel_gen()
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/intel_watermark.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 39aaf9fbe055..4a5764b59677 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -133,9 +133,11 @@ static char endis_ast(bool enabled)
>
> static int skl_num_planes(uint32_t d, int pipe)
> {
> - if (IS_GEN11(d))
> + int gen = intel_gen(d);
> +
> + if (gen >= 11)
> return 8;
> - else if (IS_GEN10(d) || IS_GEMINILAKE(d))
> + else if (gen == 10 || IS_GEMINILAKE(d))
> return 5;
> else if (IS_BROXTON(d))
> return pipe == 2 ? 4 : 5;
> @@ -145,9 +147,11 @@ static int skl_num_planes(uint32_t d, int pipe)
>
> static int skl_max_planes(uint32_t d)
> {
> - if (IS_GEN11(d))
> + int gen = intel_gen(d);
> +
> + if (gen >= 11)
> return 8;
> - else if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d))
> + else if (gen == 10 || IS_GEMINILAKE(d) || IS_BROXTON(d))
> return 5;
> else
> return 4;
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
@ 2021-05-14 9:50 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:50 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:52AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Don't repeat the register name for each pipe to make the
> register dump portion a bit less wide.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
> ---
> tools/intel_watermark.c | 98 ++++++++++++++++++-----------------------
> 1 file changed, 43 insertions(+), 55 deletions(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 657fff20ec7a..31ce165f282b 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -166,90 +166,80 @@ static int skl_max_planes(uint32_t d)
> return 4;
> }
>
> -static const char *skl_plane_name(int pipe, int plane)
> +static const char *skl_plane_name(int plane)
> {
> static char name[32];
>
> if (plane == 0)
> snprintf(name, sizeof(name), "CURSOR");
> else
> - snprintf(name, sizeof(name), "PLANE_%1d%c",
> - plane, pipe_name(pipe));
> + snprintf(name, sizeof(name), "PLANE_%1d", plane);
>
> return name;
> }
>
> -static const char *skl_wm_linetime_reg_name(int pipe)
> +static const char *skl_wm_linetime_reg_name(void)
> {
> static char reg_name[32];
>
> - snprintf(reg_name, sizeof(reg_name), "WM_LINETIME_%c",
> - pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "WM_LINETIME");
>
> return reg_name;
> }
>
> -static const char *skl_plane_ctl_reg_name(int pipe, int plane)
> +static const char *skl_plane_ctl_reg_name(int plane)
> {
> static char reg_name[32];
>
> if (plane == 0)
> - snprintf(reg_name, sizeof(reg_name), "CUR_CTL_%c",
> - pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "CUR_CTL");
> else
> - snprintf(reg_name, sizeof(reg_name), "PLANE_CTL_%1d_%c",
> - plane, pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "PLANE_CTL_%1d", plane);
>
> return reg_name;
> }
>
> -static const char *skl_wm_reg_name(int pipe, int plane, int level)
> +static const char *skl_wm_reg_name(int plane, int level)
> {
> static char reg_name[32];
>
> if (plane == 0)
> - snprintf(reg_name, sizeof(reg_name), "CUR_WM_%c_%1d",
> - pipe_name(pipe), level);
> + snprintf(reg_name, sizeof(reg_name), "CUR_WM_%1d", level);
> else
> - snprintf(reg_name, sizeof(reg_name), "PLANE_WM_%1d_%c_%1d",
> - plane, pipe_name(pipe), level);
> + snprintf(reg_name, sizeof(reg_name), "PLANE_WM_%1d_%1d", plane, level);
>
> return reg_name;
> }
>
> -static const char *skl_wm_trans_reg_name(int pipe, int plane)
> +static const char *skl_wm_trans_reg_name(int plane)
> {
> static char reg_name[32];
>
> if (plane == 0)
> - snprintf(reg_name, sizeof(reg_name), "CUR_WM_TRANS_%c",
> - pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "CUR_WM_TRANS");
> else
> - snprintf(reg_name, sizeof(reg_name), "PLANE_WM_TRANS_%1d_%c",
> - plane, pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "PLANE_WM_TRANS_%1d", plane);
> +
> return reg_name;
> }
>
> -static const char *skl_buf_cfg_reg_name(int pipe, int plane)
> +static const char *skl_buf_cfg_reg_name(int plane)
> {
> static char reg_name[32];
>
> if (plane == 0)
> - snprintf(reg_name, sizeof(reg_name), "CUR_BUF_CFG_%c",
> - pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "CUR_BUF_CFG");
> else
> - snprintf(reg_name, sizeof(reg_name), "PLANE_BUF_CFG_%1d_%c",
> - plane, pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "PLANE_BUF_CFG_%1d", plane);
>
> return reg_name;
> }
>
> -static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane)
> +static const char *skl_nv12_buf_cfg_reg_name(int plane)
> {
> static char reg_name[32];
>
> - snprintf(reg_name, sizeof(reg_name), "PLANE_NV12_BUF_CFG_%1d_%c",
> - plane, pipe_name(pipe));
> + snprintf(reg_name, sizeof(reg_name), "PLANE_NV12_BUF_CFG_%1d", plane);
>
> return reg_name;
> }
> @@ -310,21 +300,23 @@ static void skl_wm_dump(void)
> }
> }
>
> - for (pipe = 0; pipe < num_pipes; pipe++) {
> - printf("%18s 0x%08x\t",
> - skl_wm_linetime_reg_name(pipe),
> - wm_linetime[pipe]);
> - }
> + printf("%21c\t", '\0');
> + for (pipe = 0; pipe < num_pipes; pipe++)
> + printf("PIPE_%-5c\t", pipe_name(pipe));
> + printf("\n\n");
> +
> + printf("%21s\t", skl_wm_linetime_reg_name());
> + for (pipe = 0; pipe < num_pipes; pipe++)
> + printf("0x%08x\t", wm_linetime[pipe]);
> printf("\n\n");
>
> for (plane = 0; plane < max_planes; plane++) {
> + printf("%21s\t", skl_plane_ctl_reg_name(plane));
> +
> for (pipe = 0; pipe < num_pipes; pipe++) {
> if (plane >= skl_num_planes(devid, pipe))
> break;
> -
> - printf("%18s 0x%08x\t" ,
> - skl_plane_ctl_reg_name(pipe, plane),
> - plane_ctl[pipe][plane]);
> + printf("0x%08x\t" , plane_ctl[pipe][plane]);
> }
> printf("\n");
> }
> @@ -332,13 +324,12 @@ static void skl_wm_dump(void)
>
> for (plane = 0; plane < max_planes; plane++) {
> for (level = 0; level < num_levels; level++) {
> + printf("%21s\t", skl_wm_reg_name(plane, level));
> +
> for (pipe = 0; pipe < num_pipes; pipe++) {
> if (plane >= skl_num_planes(devid, pipe))
> break;
> -
> - printf("%18s 0x%08x\t" ,
> - skl_wm_reg_name(pipe, plane, level),
> - wm[level][pipe][plane]);
> + printf("0x%08x\t", wm[level][pipe][plane]);
> }
> printf("\n");
> }
> @@ -346,26 +337,24 @@ static void skl_wm_dump(void)
> }
>
> for (plane = 0; plane < max_planes; plane++) {
> + printf("%21s\t", skl_wm_trans_reg_name(plane));
> +
> for (pipe = 0; pipe < num_pipes; pipe++) {
> if (plane >= skl_num_planes(devid, pipe))
> break;
> -
> - printf("%18s 0x%08x\t",
> - skl_wm_trans_reg_name(pipe, plane),
> - wm_trans[pipe][plane]);
> + printf("0x%08x\t", wm_trans[pipe][plane]);
> }
> printf("\n");
> }
> printf("\n");
>
> for (plane = 0; plane < max_planes; plane++) {
> + printf("%21s\t", skl_buf_cfg_reg_name(plane));
> +
> for (pipe = 0; pipe < num_pipes; pipe++) {
> if (plane >= skl_num_planes(devid, pipe))
> break;
> -
> - printf("%18s 0x%08x\t",
> - skl_buf_cfg_reg_name(pipe, plane),
> - buf_cfg[pipe][plane]);
> + printf("0x%08x\t", buf_cfg[pipe][plane]);
> }
> printf("\n");
>
> @@ -375,13 +364,12 @@ static void skl_wm_dump(void)
> if (plane == 0)
> continue;
>
> + printf("%21s\t", skl_nv12_buf_cfg_reg_name(plane));
> +
> for (pipe = 0; pipe < num_pipes; pipe++) {
> if (plane >= skl_num_planes(devid, pipe))
> break;
> -
> - printf("%18s 0x%08x\t",
> - skl_nv12_buf_cfg_reg_name(pipe, plane),
> - nv12_buf_cfg[pipe][plane]);
> + printf("0x%08x\t", nv12_buf_cfg[pipe][plane]);
> }
> printf("\n");
> }
> @@ -405,7 +393,7 @@ static void skl_wm_dump(void)
> REG_DECODE1(plane_ctl[pipe][plane], 5, 1);
> else
> enable = REG_DECODE1(plane_ctl[pipe][plane], 31, 1);
> - printf("%9s%c", skl_plane_name(pipe, plane),
> + printf("%9s%c", skl_plane_name(plane),
> endis_ast(enable));
> }
> printf("\n");
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
@ 2021-05-14 9:51 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:53AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ADL-P introduces dedicated SAGV watermark registers. Decode them.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/intel_watermark.c | 106 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 102 insertions(+), 4 deletions(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 31ce165f282b..f5613c333dc3 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -166,6 +166,19 @@ static int skl_max_planes(uint32_t d)
> return 4;
> }
>
> +static bool skl_has_sagv_wm(uint32_t d)
> +{
> + return intel_gen(d) >= 13;
> +}
> +
> +static int skl_num_wm_levels(uint32_t d)
> +{
> + if (skl_has_sagv_wm(d))
> + return 6;
> + else
> + return 8;
> +}
> +
> static const char *skl_plane_name(int plane)
> {
> static char name[32];
> @@ -223,6 +236,30 @@ static const char *skl_wm_trans_reg_name(int plane)
> return reg_name;
> }
>
> +static const char *skl_wm_sagv_reg_name(int plane)
> +{
> + static char reg_name[32];
> +
> + if (plane == 0)
> + snprintf(reg_name, sizeof(reg_name), "CUR_WM_SAGV");
> + else
> + snprintf(reg_name, sizeof(reg_name), "PLANE_WM_SAGV_%1d", plane);
> +
> + return reg_name;
> +}
> +
> +static const char *skl_wm_sagv_trans_reg_name(int plane)
> +{
> + static char reg_name[32];
> +
> + if (plane == 0)
> + snprintf(reg_name, sizeof(reg_name), "CUR_WM_SAGV_TRANS");
> + else
> + snprintf(reg_name, sizeof(reg_name), "PLANE_WM_SAGV_TRANS_%1d", plane);
> +
> + return reg_name;
> +}
> +
> static const char *skl_buf_cfg_reg_name(int plane)
> {
> static char reg_name[32];
> @@ -266,10 +303,12 @@ static void skl_wm_dump(void)
> int pipe, plane, level;
> int num_pipes = skl_num_pipes(devid);
> int max_planes = skl_max_planes(devid);
> - int num_levels = 8;
> + int num_levels = skl_num_wm_levels(devid);
> uint32_t base_addr = 0x70000, addr, wm_offset;
> uint32_t wm[num_levels][num_pipes][max_planes];
> uint32_t wm_trans[num_pipes][max_planes];
> + uint32_t wm_sagv[num_pipes][max_planes];
> + uint32_t wm_sagv_trans[num_pipes][max_planes];
> uint32_t buf_cfg[num_pipes][max_planes];
> uint32_t nv12_buf_cfg[num_pipes][max_planes];
> uint32_t plane_ctl[num_pipes][max_planes];
> @@ -297,6 +336,11 @@ static void skl_wm_dump(void)
> wm_offset = addr + 0x00140 + level * 0x4;
> wm[level][pipe][plane] = read_reg(wm_offset);
> }
> +
> + if (skl_has_sagv_wm(devid)) {
> + wm_sagv[pipe][plane] = read_reg(addr + 0x00158);
> + wm_sagv_trans[pipe][plane] = read_reg(addr + 0x0015c);
> + }
> }
> }
>
> @@ -348,6 +392,32 @@ static void skl_wm_dump(void)
> }
> printf("\n");
>
> + if (skl_has_sagv_wm(devid)) {
> + for (plane = 0; plane < max_planes; plane++) {
> + printf("%21s\t", skl_wm_sagv_reg_name(plane));
> +
> + for (pipe = 0; pipe < num_pipes; pipe++) {
> + if (plane >= skl_num_planes(devid, pipe))
> + break;
> + printf("0x%08x\t", wm_sagv[pipe][plane]);
> + }
> + printf("\n");
> + }
> + printf("\n");
> +
> + for (plane = 0; plane < max_planes; plane++) {
> + printf("%21s\t", skl_wm_sagv_trans_reg_name(plane));
> +
> + for (pipe = 0; pipe < num_pipes; pipe++) {
> + if (plane >= skl_num_planes(devid, pipe))
> + break;
> + printf("0x%08x\t", wm_sagv_trans[pipe][plane]);
> + }
> + printf("\n");
> + }
> + printf("\n");
> + }
> +
> for (plane = 0; plane < max_planes; plane++) {
> printf("%21s\t", skl_buf_cfg_reg_name(plane));
>
> @@ -386,7 +456,7 @@ static void skl_wm_dump(void)
> linetime = REG_DECODE1(wm_linetime[pipe], 0, 9);
> printf("LINETIME: %d (%.3f usec)\n", linetime, linetime* 0.125f);
>
> - printf("LEVEL");
> + printf(" LEVEL");
> for (plane = 0; plane < num_planes; plane++) {
> if (plane == 0)
> enable = REG_DECODE1(plane_ctl[pipe][plane], 0, 3) ||
> @@ -399,7 +469,7 @@ static void skl_wm_dump(void)
> printf("\n");
>
> for (level = 0; level < num_levels; level++) {
> - printf("%5d", level);
> + printf("%10d", level);
> for (plane = 0; plane < num_planes; plane++) {
> blocks = REG_DECODE1(wm[level][pipe][plane], 0, 11);
> lines = REG_DECODE1(wm[level][pipe][plane], 14, 5);
> @@ -414,7 +484,7 @@ static void skl_wm_dump(void)
> printf("\n");
> }
>
> - printf("TRANS");
> + printf(" TRANS");
> for (plane = 0; plane < num_planes; plane++) {
> blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 11);
> lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5);
> @@ -427,6 +497,34 @@ static void skl_wm_dump(void)
> printf("(--)");
> }
>
> + if (skl_has_sagv_wm(devid)) {
> + printf("\n SAGV");
> + for (plane = 0; plane < num_planes; plane++) {
> + blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 11);
> + lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 5);
> + enable = REG_DECODE1(wm_sagv[pipe][plane], 31, 1);
> +
> + printf("%5d%c", blocks, endis_ast(enable));
> + if (!REG_DECODE1(wm_sagv[pipe][plane], 30, 1))
> + printf("(%2d)", lines);
> + else
> + printf("(--)");
> + }
> +
> + printf("\nSAGV TRANS");
> + for (plane = 0; plane < num_planes; plane++) {
> + blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 11);
> + lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 5);
> + enable = REG_DECODE1(wm_sagv_trans[pipe][plane], 31, 1);
> +
> + printf("%5d%c", blocks, endis_ast(enable));
> + if (!REG_DECODE1(wm_sagv_trans[pipe][plane], 30, 1))
> + printf("(%2d)", lines);
> + else
> + printf("(--)");
> + }
> + }
> +
> printf("\nDDB allocation:");
>
> printf("\nstart");
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
@ 2021-05-14 9:51 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:54AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Modern platforms have more bits in the registers. Deal with it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
> ---
> tools/intel_watermark.c | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index f5613c333dc3..1e235ed30a63 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -471,8 +471,8 @@ static void skl_wm_dump(void)
> for (level = 0; level < num_levels; level++) {
> printf("%10d", level);
> for (plane = 0; plane < num_planes; plane++) {
> - blocks = REG_DECODE1(wm[level][pipe][plane], 0, 11);
> - lines = REG_DECODE1(wm[level][pipe][plane], 14, 5);
> + blocks = REG_DECODE1(wm[level][pipe][plane], 0, 12);
> + lines = REG_DECODE1(wm[level][pipe][plane], 14, 13);
> enable = REG_DECODE1(wm[level][pipe][plane], 31, 1);
>
> printf("%5d%c", blocks, endis_ast(enable));
> @@ -486,8 +486,8 @@ static void skl_wm_dump(void)
>
> printf(" TRANS");
> for (plane = 0; plane < num_planes; plane++) {
> - blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 11);
> - lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5);
> + blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 12);
> + lines = REG_DECODE1(wm_trans[pipe][plane], 14, 13);
> enable = REG_DECODE1(wm_trans[pipe][plane], 31, 1);
>
> printf("%5d%c", blocks, endis_ast(enable));
> @@ -500,8 +500,8 @@ static void skl_wm_dump(void)
> if (skl_has_sagv_wm(devid)) {
> printf("\n SAGV");
> for (plane = 0; plane < num_planes; plane++) {
> - blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 11);
> - lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 5);
> + blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 12);
> + lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 13);
> enable = REG_DECODE1(wm_sagv[pipe][plane], 31, 1);
>
> printf("%5d%c", blocks, endis_ast(enable));
> @@ -513,8 +513,8 @@ static void skl_wm_dump(void)
>
> printf("\nSAGV TRANS");
> for (plane = 0; plane < num_planes; plane++) {
> - blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 11);
> - lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 5);
> + blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 12);
> + lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 13);
> enable = REG_DECODE1(wm_sagv_trans[pipe][plane], 31, 1);
>
> printf("%5d%c", blocks, endis_ast(enable));
> @@ -529,20 +529,20 @@ static void skl_wm_dump(void)
>
> printf("\nstart");
> for (plane = 0; plane < num_planes; plane++) {
> - start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
> + start = REG_DECODE1(buf_cfg[pipe][plane], 0, 12);
> printf("%10d", start);
> }
>
> printf("\n end");
> for (plane = 0; plane < num_planes; plane++) {
> - end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
> + end = REG_DECODE1(buf_cfg[pipe][plane], 16, 12);
> printf("%10d", end);
> }
>
> printf("\n size");
> for (plane = 0; plane < num_planes; plane++) {
> - start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
> - end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
> + start = REG_DECODE1(buf_cfg[pipe][plane], 0, 12);
> + end = REG_DECODE1(buf_cfg[pipe][plane], 16, 12);
> size = end - start + 1;
> printf("%10d", (end == 0 && size == 1) ? 0 : size);
> }
> @@ -553,20 +553,20 @@ static void skl_wm_dump(void)
>
> printf("\nstart");
> for (plane = 0; plane < num_planes; plane++) {
> - start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
> + start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 12);
> printf("%10d", start);
> }
>
> printf("\n end");
> for (plane = 0; plane < num_planes; plane++) {
> - end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
> + end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 12);
> printf("%10d", end);
> }
>
> printf("\n size");
> for (plane = 0; plane < num_planes; plane++) {
> - start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
> - end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
> + start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 12);
> + end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 12);
> size = end - start + 1;
> printf("%10d", (end == 0 && size == 1) ? 0 : size);
> }
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
@ 2021-05-14 9:53 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:53 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:50AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Modern platforms have just 5 universal planes + cursor per pipe..
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/intel_watermark.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 4a5764b59677..ff373fdb0c6d 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -135,7 +135,9 @@ static int skl_num_planes(uint32_t d, int pipe)
> {
> int gen = intel_gen(d);
>
> - if (gen >= 11)
> + if (gen >= 13 || IS_ALDERLAKE_S(d) || IS_ROCKETLAKE(d))
> + return 6;
> + else if (gen >= 11)
> return 8;
> else if (gen == 10 || IS_GEMINILAKE(d))
> return 5;
> @@ -149,7 +151,9 @@ static int skl_max_planes(uint32_t d)
> {
> int gen = intel_gen(d);
>
> - if (gen >= 11)
> + if (gen >= 13 || IS_ALDERLAKE_S(d) || IS_ROCKETLAKE(d))
> + return 6;
> + else if (gen >= 11)
> return 8;
> else if (gen == 10 || IS_GEMINILAKE(d) || IS_BROXTON(d))
> return 5;
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
@ 2021-05-14 9:53 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 19+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-14 9:53 UTC (permalink / raw)
To: Ville Syrjala; +Cc: igt-dev
On Wed, Apr 14, 2021 at 05:27:51AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Decode pipe D watermark stuff too.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/intel_watermark.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index ff373fdb0c6d..657fff20ec7a 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -131,6 +131,11 @@ static char endis_ast(bool enabled)
> return enabled ? '*' : ' ';
> }
>
> +static int skl_num_pipes(uint32_t d)
> +{
> + return intel_gen(d) >= 12 ? 4 : 3;
> +}
> +
> static int skl_num_planes(uint32_t d, int pipe)
> {
> int gen = intel_gen(d);
> @@ -269,7 +274,7 @@ static void skl_wm_dump(void)
> {
> struct intel_mmio_data mmio_data;
> int pipe, plane, level;
> - int num_pipes = 3;
> + int num_pipes = skl_num_pipes(devid);
> int max_planes = skl_max_planes(devid);
> int num_levels = 8;
> uint32_t base_addr = 0x70000, addr, wm_offset;
> --
> 2.26.3
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-05-14 9:50 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
2021-05-14 9:31 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
2021-05-14 9:36 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
2021-05-14 9:47 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
2021-05-14 9:53 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
2021-05-14 9:53 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
2021-05-14 9:50 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
2021-05-14 9:51 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
2021-05-14 9:51 ` Lisovskiy, Stanislav
2021-04-14 3:04 ` [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms Patchwork
2021-04-14 4:01 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.