* [Intel-gfx] [CI 01/19] drm/i915/xelpd: Handle new location of outputs D and E
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
@ 2021-05-14 15:36 ` Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 02/19] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
` (21 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:36 UTC (permalink / raw)
To: intel-gfx
The DDI naming template for display version 12 went A-C, TC1-TC6. With
XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The XE_LPD design keeps the register offsets and bitfields relating to
the TC outputs in the same location they were previously. The new "D"
and "E" outputs now take the locations that were previously used by TC5
and TC6 outputs, or what we would have considered to be outputs "H" and
"I" under the legacy lettering scheme.
For the most part everything will just work as long as we initialize the
output with the proper 'enum port' value. However we do need to take
care to pick the correct AUX channel when parsing the VBT (e.g., a
reference to 'AUX D' is actually asking us to use the 8th aux channel,
not the fourth). We should also make sure that our encoders and aux
channels are named appropriately so that it's easier to correlate driver
debug messages with the bspec instructions.
v2:
- Update handling of TGL_TRANS_CLK_SEL_PORT. (Jose)
v3:
- Add hpd_pin to handle outputs D and E (Jose)
- Fixed conversion of BIOS port to aux ch for TC ports (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 28 +++++++++++---
drivers/gpu/drm/i915/display/intel_ddi.c | 40 +++++++++++++++-----
drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
drivers/gpu/drm/i915/display/intel_display.h | 8 ++++
drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 ++++---
5 files changed, 74 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9785dfc2de0b..e67d9988dfbf 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2873,7 +2873,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) == 13)
+ aux_ch = AUX_CH_D_XELPD;
+ else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC3;
else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
aux_ch = AUX_CH_USBC2;
@@ -2881,22 +2883,36 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) == 13)
+ aux_ch = AUX_CH_E_XELPD;
+ else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC4;
else
aux_ch = AUX_CH_E;
break;
case DP_AUX_F:
- aux_ch = AUX_CH_F;
+ if (DISPLAY_VER(i915) == 13)
+ aux_ch = AUX_CH_USBC1;
+ else
+ aux_ch = AUX_CH_F;
break;
case DP_AUX_G:
- aux_ch = AUX_CH_G;
+ if (DISPLAY_VER(i915) == 13)
+ aux_ch = AUX_CH_USBC2;
+ else
+ aux_ch = AUX_CH_G;
break;
case DP_AUX_H:
- aux_ch = AUX_CH_H;
+ if (DISPLAY_VER(i915) == 13)
+ aux_ch = AUX_CH_USBC3;
+ else
+ aux_ch = AUX_CH_H;
break;
case DP_AUX_I:
- aux_ch = AUX_CH_I;
+ if (DISPLAY_VER(i915) == 13)
+ aux_ch = AUX_CH_USBC4;
+ else
+ aux_ch = AUX_CH_I;
break;
default:
MISSING_CASE(info->alternate_aux_channel);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b7a2fce684c9..b0ea08136118 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -854,18 +854,19 @@ void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
if (cpu_transcoder != TRANSCODER_EDP) {
- if (DISPLAY_VER(dev_priv) >= 12)
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TGL_TRANS_CLK_SEL_PORT(port));
+ if (DISPLAY_VER(dev_priv) >= 13)
+ val = TGL_TRANS_CLK_SEL_PORT(phy);
+ else if (DISPLAY_VER(dev_priv) >= 12)
+ val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
else
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ val = TRANS_CLK_SEL_PORT(encoder->port);
+
+ intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
}
}
@@ -4356,6 +4357,17 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
i915->hti_state & HDPORT_DDI_USED(phy);
}
+static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
+ enum port port)
+{
+ if (port >= PORT_D_XELPD)
+ return HPD_PORT_D + port - PORT_D_XELPD;
+ else if (port >= PORT_TC1)
+ return HPD_PORT_TC1 + port - PORT_TC1;
+ else
+ return HPD_PORT_A + port - PORT_A;
+}
+
static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -4495,7 +4507,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder = &dig_port->base;
encoder->devdata = devdata;
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+ DRM_MODE_ENCODER_TMDS,
+ "DDI %c/PHY %c",
+ port_name(port - PORT_D_XELPD + PORT_D),
+ phy_name(phy));
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
@@ -4606,7 +4624,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->get_config = hsw_ddi_get_config;
}
- if (IS_DG1(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13)
+ encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
+ else if (IS_DG1(dev_priv))
encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0c2b194006f8..3ab8af355b8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3681,7 +3681,11 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+ if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
+ return PHY_D + port - PORT_D_XELPD;
+ else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
+ return PHY_F + port - PORT_TC1;
+ else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
return PHY_B + port - PORT_TC1;
else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index e7764e746c6a..bd69affc791c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -217,6 +217,10 @@ enum port {
PORT_TC5,
PORT_TC6,
+ /* XE_LPD repositions D/E offsets and bitfields */
+ PORT_D_XELPD = PORT_TC5,
+ PORT_E_XELPD,
+
I915_MAX_PORTS
};
@@ -300,6 +304,10 @@ enum aux_ch {
AUX_CH_USBC4,
AUX_CH_USBC5,
AUX_CH_USBC6,
+
+ /* XE_LPD repositions D/E offsets and bitfields */
+ AUX_CH_D_XELPD = AUX_CH_USBC5,
+ AUX_CH_E_XELPD,
};
#define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 350b12f0beb8..7c048d2ecf43 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -602,8 +602,8 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
+ case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
+ case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
return DP_AUX_CH_CTL(aux_ch);
default:
MISSING_CASE(aux_ch);
@@ -625,8 +625,8 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
+ case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
+ case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
return DP_AUX_CH_DATA(aux_ch, index);
default:
MISSING_CASE(aux_ch);
@@ -681,7 +681,11 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
drm_dp_aux_init(&intel_dp->aux);
/* Failure to allocate our preferred name is not critical */
- if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+ if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+ aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
+ encoder->base.name);
+ else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
aux_ch - AUX_CH_USBC1 + '1',
encoder->base.name);
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 02/19] drm/i915/xelpd: Increase maximum watermark lines to 255
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 01/19] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
@ 2021-05-14 15:36 ` Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 03/19] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
` (20 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:36 UTC (permalink / raw)
To: intel-gfx
XE_LPD continues to use the same "skylake-style" watermark
programming as other recent platforms. The only change to the watermark
calculations compared to Display12 is that XE_LPD now allows a
maximum of 255 lines vs the old limit of 31.
Due to the larger possible lines value, the corresponding bits
representing the value in PLANE_WM are also extended, so make sure we
read/write enough bits. Let's also take this opportunity to switch over
to the REG_FIELD notation.
Bspec: 49325
Bspec: 50419
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 871d839dfcb8..04072c7e9efa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6435,8 +6435,7 @@ enum {
#define _CUR_WM_TRANS_B_0 0x71168
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_SHIFT 14
-#define PLANE_WM_LINES_MASK 0x1f
+#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 00a5fe424c5a..86a78cbb60fc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5185,6 +5185,14 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
return level > 0;
}
+static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
+{
+ if (DISPLAY_VER(dev_priv) >= 13)
+ return 255;
+ else
+ return 31;
+}
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
unsigned int latency,
@@ -5289,7 +5297,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
if (!skl_wm_has_lines(dev_priv, level))
lines = 0;
- if (lines > 31) {
+ if (lines > skl_wm_max_lines(dev_priv)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
@@ -5585,7 +5593,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
if (level->ignore_lines)
val |= PLANE_WM_IGNORE_LINES;
val |= level->blocks;
- val |= level->lines << PLANE_WM_LINES_SHIFT;
+ val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
intel_de_write_fw(dev_priv, reg, val);
}
@@ -6193,8 +6201,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
level->enable = val & PLANE_WM_EN;
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
level->blocks = val & PLANE_WM_BLOCKS_MASK;
- level->lines = (val >> PLANE_WM_LINES_SHIFT) &
- PLANE_WM_LINES_MASK;
+ level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
}
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 03/19] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 01/19] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 02/19] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
@ 2021-05-14 15:36 ` Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 04/19] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
` (19 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:36 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 861409bc210d..d283c420af3f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1097,10 +1097,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc;
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1188,7 +1196,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- u8 dsc_max_bpc;
int pipe_bpp;
int ret;
@@ -1198,14 +1205,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(dev_priv) >= 12)
- dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
- else
- dsc_max_bpc = min_t(u8, 10,
- conn_state->max_requested_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 04/19] drm/i915/xelpd: Support DP1.4 compression BPPs
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (2 preceding siblings ...)
2021-05-14 15:36 ` [Intel-gfx] [CI 03/19] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
@ 2021-05-14 15:36 ` Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 05/19] drm/i915: Get slice height before computing rc params Matt Roper
` (18 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:36 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++++-------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d283c420af3f..93a686474d24 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -109,6 +109,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
@@ -494,7 +495,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner)
+ bool bigjoiner,
+ u32 pipe_bpp)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -519,6 +521,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
max_bpp_small_joiner_ram);
+
/*
* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
* check, output bpp from small joiner RAM check)
@@ -541,12 +544,17 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
return 0;
}
- /* Find the nearest match in the array of known BPPs from VESA */
- for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
- if (bits_per_pixel < valid_dsc_bpp[i + 1])
- break;
+ /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
+ if (DISPLAY_VER(i915) >= 13) {
+ bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
+ } else {
+ /* Find the nearest match in the array of known BPPs from VESA */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
}
- bits_per_pixel = valid_dsc_bpp[i];
/*
* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
@@ -780,6 +788,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
*/
if (DISPLAY_VER(dev_priv) >= 10 &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ /*
+ * TBD pass the connector BPC,
+ * for now U8_MAX so that max BPC on that platform would be picked
+ */
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
@@ -793,7 +807,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_lanes,
target_clock,
mode->hdisplay,
- bigjoiner) >> 4;
+ bigjoiner,
+ pipe_bpp) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1240,7 +1255,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner);
+ pipe_config->bigjoiner,
+ pipe_bpp);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 05/19] drm/i915: Get slice height before computing rc params
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (3 preceding siblings ...)
2021-05-14 15:36 ` [Intel-gfx] [CI 04/19] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
@ 2021-05-14 15:36 ` Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 06/19] drm/i915/xelpd: Provide port/phy mapping for vbt Matt Roper
` (17 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:36 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
We need slice height to calculate few RC parameters
hence assign slice height first.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 93a686474d24..02cb11ec46f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1154,10 +1154,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
*/
vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
- ret = intel_dsc_compute_params(encoder, crtc_state);
- if (ret)
- return ret;
-
/*
* Slice Height of 8 works for all currently available panels. So start
* with that if pic_height is an integral multiple of 8. Eventually add
@@ -1170,6 +1166,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
else
vdsc_cfg->slice_height = 2;
+ ret = intel_dsc_compute_params(encoder, crtc_state);
+ if (ret)
+ return ret;
+
vdsc_cfg->dsc_version_major =
(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 06/19] drm/i915/xelpd: Provide port/phy mapping for vbt
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (4 preceding siblings ...)
2021-05-14 15:36 ` [Intel-gfx] [CI 05/19] drm/i915: Get slice height before computing rc params Matt Roper
@ 2021-05-14 15:36 ` Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 07/19] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
` (16 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:36 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
This will allow proper DDI initialization based on vbt information.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index e67d9988dfbf..5b6922e28ef2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1743,8 +1743,24 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915,
[PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
[PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
};
+ static const int xelpd_port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+ [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
+ [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
+ [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 },
+ [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
+ };
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) == 13)
+ return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping),
+ ARRAY_SIZE(xelpd_port_mapping[0]),
+ xelpd_port_mapping,
+ dvo_port);
+ else if (IS_ALDERLAKE_S(i915))
return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
ARRAY_SIZE(adls_port_mapping[0]),
adls_port_mapping,
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 07/19] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (5 preceding siblings ...)
2021-05-14 15:36 ` [Intel-gfx] [CI 06/19] drm/i915/xelpd: Provide port/phy mapping for vbt Matt Roper
@ 2021-05-14 15:36 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 08/19] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
` (15 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:36 UTC (permalink / raw)
To: intel-gfx
ADL-P further extends the bits in PLANE_WM that represent blocks and
lines; we need to extend our masks accordingly. Since these bits are
reserved and MBZ on earlier platforms, it's safe to use the larger
bitmask on all platforms.
Bspec: 50419
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04072c7e9efa..02910d0299ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6435,8 +6435,8 @@ enum {
#define _CUR_WM_TRANS_B_0 0x71168
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
-#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
+#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
+#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 08/19] drm/i915/adl_p: Add cdclk support for ADL-P
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (6 preceding siblings ...)
2021-05-14 15:36 ` [Intel-gfx] [CI 07/19] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 09/19] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
` (14 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
ADL-P has 3 possible refclk frequencies: 19.2MHz,
24MHz and 38.4MHz
While we're at it, remove the drm_WARNs. They've never actually helped
us catch any problems, but it's very easy to forget to update them
properly for new platforms.
BSpec: 55409, 49208
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 41 +++++++++++++++-------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 25ef077dc389..d40126061038 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1253,6 +1253,27 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals adlp_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
@@ -1428,18 +1449,12 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
div = 2;
break;
case BXT_CDCLK_CD2X_DIV_SEL_1_5:
- drm_WARN(&dev_priv->drm,
- DISPLAY_VER(dev_priv) >= 10,
- "Unsupported divider\n");
div = 3;
break;
case BXT_CDCLK_CD2X_DIV_SEL_2:
div = 4;
break;
case BXT_CDCLK_CD2X_DIV_SEL_4:
- drm_WARN(&dev_priv->drm,
- DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv),
- "Unsupported divider\n");
div = 8;
break;
default:
@@ -1550,16 +1565,10 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
case 2:
return BXT_CDCLK_CD2X_DIV_SEL_1;
case 3:
- drm_WARN(&dev_priv->drm,
- DISPLAY_VER(dev_priv) >= 10,
- "Unsupported divider\n");
return BXT_CDCLK_CD2X_DIV_SEL_1_5;
case 4:
return BXT_CDCLK_CD2X_DIV_SEL_2;
case 8:
- drm_WARN(&dev_priv->drm,
- DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv),
- "Unsupported divider\n");
return BXT_CDCLK_CD2X_DIV_SEL_4;
}
}
@@ -2825,7 +2834,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dev_priv->display.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk.table = adlp_cdclk_table;
+ } else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 09/19] drm/i915/display/tc: Rename safe_mode functions ownership
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (7 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 08/19] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 10/19] drm/i915/adl_p: Enable modular fia Matt Roper
` (13 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display
has the control over the TC phy.
The "not safe" naming is confusing using ownership make it easier
to read also future platforms will have a new register that does the
same job as DP_PHY_MODE_STATUS_NOT_SAFE but with the onwership name.
BSpec: 49294
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 35 ++++++++++++-------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 59de6ca436db..d2d524329509 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -256,8 +256,8 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
}
-static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
- bool enable)
+static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
+ bool take)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -267,20 +267,20 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
if (val == 0xffffffff) {
drm_dbg_kms(&i915->drm,
- "Port %s: PHY in TCCOLD, can't %s safe-mode\n",
- dig_port->tc_port_name, enabledisable(enable));
+ "Port %s: PHY in TCCOLD, can't %s ownership\n",
+ dig_port->tc_port_name, take ? "take" : "release");
return false;
}
val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
- if (!enable)
+ if (take)
val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
intel_uncore_write(uncore,
PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
- if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
+ if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
drm_dbg_kms(&i915->drm,
"Port %s: PHY complete clear timed out\n",
dig_port->tc_port_name);
@@ -288,7 +288,7 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
return true;
}
-static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
+static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
@@ -303,7 +303,7 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
return true;
}
- return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx));
+ return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
}
/*
@@ -329,7 +329,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
goto out_set_tbt_alt_mode;
}
- if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
+ if (!icl_tc_phy_take_ownership(dig_port, true) &&
!drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
goto out_set_tbt_alt_mode;
@@ -348,7 +348,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
dig_port->tc_port_name);
- goto out_set_safe_mode;
+ goto out_release_phy;
}
if (max_lanes < required_lanes) {
@@ -356,15 +356,15 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
"Port %s: PHY max lanes %d < required lanes %d\n",
dig_port->tc_port_name,
max_lanes, required_lanes);
- goto out_set_safe_mode;
+ goto out_release_phy;
}
dig_port->tc_mode = TC_PORT_DP_ALT;
return;
-out_set_safe_mode:
- icl_tc_phy_set_safe_mode(dig_port, true);
+out_release_phy:
+ icl_tc_phy_take_ownership(dig_port, false);
out_set_tbt_alt_mode:
dig_port->tc_mode = TC_PORT_TBT_ALT;
}
@@ -380,7 +380,7 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
/* Nothing to do, we never disconnect from legacy mode */
break;
case TC_PORT_DP_ALT:
- icl_tc_phy_set_safe_mode(dig_port, true);
+ icl_tc_phy_take_ownership(dig_port, false);
dig_port->tc_mode = TC_PORT_TBT_ALT;
break;
case TC_PORT_TBT_ALT:
@@ -401,8 +401,8 @@ static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
return dig_port->tc_mode == TC_PORT_TBT_ALT;
}
- if (icl_tc_phy_is_in_safe_mode(dig_port)) {
- drm_dbg_kms(&i915->drm, "Port %s: PHY still in safe mode\n",
+ if (!icl_tc_phy_is_owned(dig_port)) {
+ drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
dig_port->tc_port_name);
return false;
@@ -417,10 +417,9 @@ intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
u32 live_status_mask = tc_port_live_status_mask(dig_port);
- bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
enum tc_port_mode mode;
- if (in_safe_mode ||
+ if (!icl_tc_phy_is_owned(dig_port) ||
drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
return TC_PORT_TBT_ALT;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 10/19] drm/i915/adl_p: Enable modular fia
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (8 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 09/19] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 11/19] drm/i915: Move intel_modeset_all_pipes() Matt Roper
` (12 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Alderlake P have modular FIA like TGL but it is always modular in all
skus, not like TGL that we had to read a register to check if it is
monolithic or modular.
BSpec: 55480
BSpec: 50572
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 4 ++++
drivers/gpu/drm/i915/i915_pci.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index d2d524329509..e325463acddd 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -624,6 +624,10 @@ tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig
if (!INTEL_INFO(i915)->display.has_modular_fia)
return false;
+ /* TODO: check if in real HW MODULAR_FIA_MASK is set, if so remove this block */
+ if (IS_ALDERLAKE_P(i915))
+ return true;
+
wakeref = tc_cold_block(dig_port);
val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
tc_cold_unblock(dig_port, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3a1cec2ba8ca..574881c0e339 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -954,6 +954,7 @@ static const struct intel_device_info adl_p_info = {
XE_LPD_FEATURES,
PLATFORM(INTEL_ALDERLAKE_P),
.require_force_probe = 1,
+ .display.has_modular_fia = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 11/19] drm/i915: Move intel_modeset_all_pipes()
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (9 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 10/19] drm/i915/adl_p: Enable modular fia Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 12/19] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
` (11 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_modeset_all_pipes() to a central place so that we can
use it elsewhere as well. No functional changes.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 38 --------------------
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
3 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d40126061038..c9f1484f3811 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2375,44 +2375,6 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
return 0;
}
-static int intel_modeset_all_pipes(struct intel_atomic_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc *crtc;
-
- /*
- * Add all pipes to the state, and force
- * a modeset on all the active ones.
- */
- for_each_intel_crtc(&dev_priv->drm, crtc) {
- struct intel_crtc_state *crtc_state;
- int ret;
-
- crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
- if (IS_ERR(crtc_state))
- return PTR_ERR(crtc_state);
-
- if (!crtc_state->hw.active ||
- drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
- continue;
-
- crtc_state->uapi.mode_changed = true;
-
- ret = drm_atomic_add_affected_connectors(&state->base,
- &crtc->base);
- if (ret)
- return ret;
-
- ret = intel_atomic_add_affected_planes(state, crtc);
- if (ret)
- return ret;
-
- crtc_state->update_planes |= crtc_state->active_planes;
- }
-
- return 0;
-}
-
static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
{
int min_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3ab8af355b8c..b5fd721137d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9033,6 +9033,44 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
verify_disabled_dpll_state(dev_priv);
}
+int intel_modeset_all_pipes(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ /*
+ * Add all pipes to the state, and force
+ * a modeset on all the active ones.
+ */
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+ int ret;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ if (!crtc_state->hw.active ||
+ drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
+ continue;
+
+ crtc_state->uapi.mode_changed = true;
+
+ ret = drm_atomic_add_affected_connectors(&state->base,
+ &crtc->base);
+ if (ret)
+ return ret;
+
+ ret = intel_atomic_add_affected_planes(state, crtc);
+ if (ret)
+ return ret;
+
+ crtc_state->update_planes |= crtc_state->active_planes;
+ }
+
+ return 0;
+}
+
static void
intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index bd69affc791c..c9dbaf074d77 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -646,6 +646,7 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
void intel_display_resume(struct drm_device *dev);
void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
+int intel_modeset_all_pipes(struct intel_atomic_state *state);
/* modesetting asserts */
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 12/19] drm/i915/adl_p: Enable/disable loadgen sharing
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (10 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 11/19] drm/i915: Move intel_modeset_all_pipes() Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 13/19] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
` (10 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: Mika Kahola <mika.kahola@intel.com>
Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
For all other modes, we can enable loadgen sharing feature.
BSpec: 55359
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b0ea08136118..feda6a4fb9d0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1459,6 +1459,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
val &= ~DKL_TX_DP20BITMODE;
intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
+
+ if ((intel_crtc_has_dp_encoder(crtc_state) &&
+ crtc_state->port_clock == 162000) ||
+ (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+ crtc_state->port_clock == 594000))
+ val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
+ else
+ val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02910d0299ba..31bc413dbba1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10831,6 +10831,7 @@ enum skl_power_gate {
_DKL_TX_DPCNTL1)
#define _DKL_TX_DPCNTL2 0x2C8
+#define DKL_TX_LOADGEN_SHARING_PMD_DISABLE REG_BIT(12)
#define DKL_TX_DP20BITMODE (1 << 2)
#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
_DKL_PHY1_BASE, \
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 13/19] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (11 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 12/19] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 14/19] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
` (9 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: Animesh Manna <animesh.manna@intel.com>
No need for checking dsc flag for uncompressed pipe joiner mode
validation.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 02cb11ec46f0..75f4c56757e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -819,8 +819,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc = dsc_max_output_bpp && dsc_slice_count;
}
- /* big joiner configuration needs DSC */
- if (bigjoiner && !dsc)
+ /*
+ * Big joiner configuration needs DSC for TGL which is not true for
+ * XE_LPD where uncompressed joiner is supported.
+ */
+ if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
return MODE_CLOCK_HIGH;
if (mode_rate > max_rate && !dsc)
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 14/19] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (12 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 13/19] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
` (8 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: Animesh Manna <animesh.manna@intel.com>
For uncompressed big joiner DSC engine will not be used so will avoid
compute config of DSC.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 75f4c56757e3..16cdec9a4aa3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1371,9 +1371,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
*/
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
- /* enable compression if the mode doesn't fit available BW */
+ /*
+ * Pipe joiner needs compression upto display12 due to BW limitation. DG2
+ * onwards pipe joiner can be enabled without compression.
+ */
drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
- if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
+ if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 &&
+ pipe_config->bigjoiner)) {
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
conn_state, &limits);
if (ret < 0)
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (13 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 14/19] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-06-03 9:39 ` Jani Nikula
2021-05-14 15:37 ` [Intel-gfx] [CI 16/19] drm/i915/adl_p: Add IPs stepping mapping Matt Roper
` (7 subsequent siblings)
22 siblings, 1 reply; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: Animesh Manna <animesh.manna@intel.com>
Respective bit for master or slave to be set for uncompressed
bigjoiner in dss_ctl1 register.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++
drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 2 +
4 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b5fd721137d3..422b59ebf6dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(master->base.dev);
struct intel_crtc_state *master_crtc_state;
struct drm_connector_state *conn_state;
struct drm_connector *conn;
@@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
/* and DSC on slave */
intel_dsc_enable(NULL, crtc_state);
}
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ intel_uncompressed_joiner_enable(crtc_state);
}
static void hsw_crtc_enable(struct intel_atomic_state *state,
@@ -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
}
intel_dsc_get_config(pipe_config);
+ if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
+ intel_uncompressed_joiner_get_config(pipe_config);
if (!active) {
/* bigjoiner slave doesn't enable transcoder */
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index adcd6752f919..efc3184d8315 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
}
+void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dss_ctl1_val = 0;
+
+ if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
+ if (crtc_state->bigjoiner_slave)
+ dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
+ else
+ dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
+
+ intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
+ }
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1060,13 +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (!old_crtc_state->dsc.compression_enable)
+ if (!(old_crtc_state->dsc.compression_enable &&
+ old_crtc_state->bigjoiner))
return;
intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
}
+void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dss_ctl1;
+
+ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
+ if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
+ crtc_state->bigjoiner = true;
+ if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
+ crtc_state->bigjoiner = true;
+ crtc_state->bigjoiner_slave = true;
+ if (!WARN_ON(crtc->pipe == PIPE_A))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
+ }
+}
+
void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 65d301c23580..fe4d45561253 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -12,11 +12,13 @@ struct intel_encoder;
struct intel_crtc_state;
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
+void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
+void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state);
void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31bc413dbba1..dd6e0bae9573 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11493,6 +11493,8 @@ enum skl_power_gate {
#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
+#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
+#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
#define _ICL_PIPE_DSS_CTL2_PB 0x78204
#define _ICL_PIPE_DSS_CTL2_PC 0x78404
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-05-14 15:37 ` [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
@ 2021-06-03 9:39 ` Jani Nikula
2021-06-03 12:33 ` Jani Nikula
2021-06-03 13:37 ` Manna, Animesh
0 siblings, 2 replies; 33+ messages in thread
From: Jani Nikula @ 2021-06-03 9:39 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> From: Animesh Manna <animesh.manna@intel.com>
>
> Respective bit for master or slave to be set for uncompressed
> bigjoiner in dss_ctl1 register.
I was looking at the changes here due to a static checker complaint, and
I think there are a number of issues here. Some more serious than
others, and some predate the patch.
Comments inline.
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> 4 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b5fd721137d3..422b59ebf6dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
> struct intel_crtc_state *master_crtc_state;
> struct drm_connector_state *conn_state;
> struct drm_connector *conn;
> @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
> /* and DSC on slave */
> intel_dsc_enable(NULL, crtc_state);
> }
> +
> + if (DISPLAY_VER(dev_priv) >= 13)
> + intel_uncompressed_joiner_enable(crtc_state);
> }
>
> static void hsw_crtc_enable(struct intel_atomic_state *state,
> @@ -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> }
>
> intel_dsc_get_config(pipe_config);
> + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
> + intel_uncompressed_joiner_get_config(pipe_config);
>
> if (!active) {
> /* bigjoiner slave doesn't enable transcoder */
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index adcd6752f919..efc3184d8315 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
> return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
> }
>
> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
Naming. Basically for any new function, the function name prefix should
match the file name. intel_vdsc.[ch] should have functions prefixed
intel_vdsc_*(). This is where we're headed to increase clarity.
intel_uncompressed_*() is something completely different.
Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should
probably stick with intel_dsc_*(). A possible function or file rename is
not out of the question, but that's a separate matter.
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 dss_ctl1_val = 0;
> +
> + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
> + if (crtc_state->bigjoiner_slave)
> + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
> + else
> + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
> +
> + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> + }
> +}
> +
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -1060,13 +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!old_crtc_state->dsc.compression_enable)
> + if (!(old_crtc_state->dsc.compression_enable &&
> + old_crtc_state->bigjoiner))
This fails to disable compression if we only have compression but no
bigjoiner, which is the more common case!
See also:
https://gitlab.freedesktop.org/drm/intel/-/issues/3537
https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-vandita.kulkarni@intel.com
> return;
>
> intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> }
>
> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 dss_ctl1;
> +
> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
> + crtc_state->bigjoiner = true;
> + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> + crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
> + crtc_state->bigjoiner = true;
> + crtc_state->bigjoiner_slave = true;
> + if (!WARN_ON(crtc->pipe == PIPE_A))
> + crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
> + }
Nitpick: This duplicates a bunch of logic for figuring out master/slave.
The static checker warning was about crtc->pipe + 1 usage. Since
INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
checker has a hard time figuring out it does not overflow
i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
So here in intel_vdsc.c the checks are for overflowing/underflowing the
pipe range. In intel_get_crtc_for_pipe() there's a check for the pipe
actually existing - the pipe numbering might not be contiguous.
Superficially the static checker warning is bogus, as in we won't
overflow anything. However, deep down there are issues in the
consistency of the checks and how to handle non-contigouous pipe
numbering.
Indeed, this does not *need* the number. We should figure out the next
*crtc*, not the next pipe *number*, which may or may not be pipe + 1.
BR,
Jani.
> +}
> +
> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 65d301c23580..fe4d45561253 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -12,11 +12,13 @@ struct intel_encoder;
> struct intel_crtc_state;
>
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
> int intel_dsc_compute_params(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state);
> void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 31bc413dbba1..dd6e0bae9573 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11493,6 +11493,8 @@ enum skl_power_gate {
> #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
> +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
>
> #define _ICL_PIPE_DSS_CTL2_PB 0x78204
> #define _ICL_PIPE_DSS_CTL2_PC 0x78404
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-06-03 9:39 ` Jani Nikula
@ 2021-06-03 12:33 ` Jani Nikula
2021-06-03 13:49 ` Manna, Animesh
2021-06-03 13:37 ` Manna, Animesh
1 sibling, 1 reply; 33+ messages in thread
From: Jani Nikula @ 2021-06-03 12:33 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Thu, 03 Jun 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> From: Animesh Manna <animesh.manna@intel.com>
>>
>> Respective bit for master or slave to be set for uncompressed
>> bigjoiner in dss_ctl1 register.
>
> I was looking at the changes here due to a static checker complaint, and
> I think there are a number of issues here. Some more serious than
> others, and some predate the patch.
>
> Comments inline.
>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 6 +++
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
>> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
>> drivers/gpu/drm/i915/i915_reg.h | 2 +
>> 4 files changed, 49 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index b5fd721137d3..422b59ebf6dc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
>> const struct intel_crtc_state *crtc_state)
>> {
>> struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
>> struct intel_crtc_state *master_crtc_state;
>> struct drm_connector_state *conn_state;
>> struct drm_connector *conn;
>> @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
>> /* and DSC on slave */
>> intel_dsc_enable(NULL, crtc_state);
>> }
>> +
>> + if (DISPLAY_VER(dev_priv) >= 13)
I don't think we should add these checks here. Make sure the crtc_state
only has the relevant stuff enabled if the platform supports it. Don't
duplicate the checks.
>> + intel_uncompressed_joiner_enable(crtc_state);
As this is always called after intel_dsc_enable(), I think it would make
sense to move this within intel_dsc_enable().
>> }
>>
>> static void hsw_crtc_enable(struct intel_atomic_state *state,
>> @@ -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>> }
>>
>> intel_dsc_get_config(pipe_config);
>> + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
>> + intel_uncompressed_joiner_get_config(pipe_config);
As this is always called after intel_dsc_get_config(), I think it would
make sense to move this within intel_dsc_get_config.
>>
>> if (!active) {
>> /* bigjoiner slave doesn't enable transcoder */
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index adcd6752f919..efc3184d8315 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
>> return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
>> }
>>
>> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
>
> Naming. Basically for any new function, the function name prefix should
> match the file name. intel_vdsc.[ch] should have functions prefixed
> intel_vdsc_*(). This is where we're headed to increase clarity.
>
> intel_uncompressed_*() is something completely different.
>
> Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should
> probably stick with intel_dsc_*(). A possible function or file rename is
> not out of the question, but that's a separate matter.
>
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + u32 dss_ctl1_val = 0;
>> +
>> + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
>> + if (crtc_state->bigjoiner_slave)
>> + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
>> + else
>> + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
>> +
>> + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
>> + }
>> +}
>> +
>> void intel_dsc_enable(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state)
>> {
>> @@ -1060,13 +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>
>> - if (!old_crtc_state->dsc.compression_enable)
>> + if (!(old_crtc_state->dsc.compression_enable &&
>> + old_crtc_state->bigjoiner))
>
> This fails to disable compression if we only have compression but no
> bigjoiner, which is the more common case!
>
> See also:
>
> https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-vandita.kulkarni@intel.com
>
>> return;
>>
>> intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
>> intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
>> }
>>
>> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> + u32 dss_ctl1;
>> +
>> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
You can't read this without holding the power domain.
Since this is always called after intel_dsc_get_config(), I think it
would make sense to move this reading there.
>> + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
>> + crtc_state->bigjoiner = true;
>> + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
>> + crtc_state->bigjoiner_linked_crtc =
>> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
>> + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
>> + crtc_state->bigjoiner = true;
>> + crtc_state->bigjoiner_slave = true;
>> + if (!WARN_ON(crtc->pipe == PIPE_A))
>> + crtc_state->bigjoiner_linked_crtc =
>> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
>> + }
>
> Nitpick: This duplicates a bunch of logic for figuring out master/slave.
>
> The static checker warning was about crtc->pipe + 1 usage. Since
> INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
> checker has a hard time figuring out it does not overflow
> i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
>
> So here in intel_vdsc.c the checks are for overflowing/underflowing the
> pipe range. In intel_get_crtc_for_pipe() there's a check for the pipe
> actually existing - the pipe numbering might not be contiguous.
>
> Superficially the static checker warning is bogus, as in we won't
> overflow anything. However, deep down there are issues in the
> consistency of the checks and how to handle non-contigouous pipe
> numbering.
>
> Indeed, this does not *need* the number. We should figure out the next
> *crtc*, not the next pipe *number*, which may or may not be pipe + 1.
>
>
> BR,
> Jani.
>
>> +}
>> +
>> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>> {
>> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> index 65d301c23580..fe4d45561253 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> @@ -12,11 +12,13 @@ struct intel_encoder;
>> struct intel_crtc_state;
>>
>> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
>> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
>> void intel_dsc_enable(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state);
>> void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
>> int intel_dsc_compute_params(struct intel_encoder *encoder,
>> struct intel_crtc_state *pipe_config);
>> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state);
>> void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>> enum intel_display_power_domain
>> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 31bc413dbba1..dd6e0bae9573 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -11493,6 +11493,8 @@ enum skl_power_gate {
>> #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
>> #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
>> +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
>>
>> #define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> #define _ICL_PIPE_DSS_CTL2_PC 0x78404
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-06-03 12:33 ` Jani Nikula
@ 2021-06-03 13:49 ` Manna, Animesh
2021-06-03 18:27 ` Navare, Manasi
0 siblings, 1 reply; 33+ messages in thread
From: Manna, Animesh @ 2021-06-03 13:49 UTC (permalink / raw)
To: Jani Nikula, Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, June 3, 2021 6:03 PM
> To: Roper, Matthew D <matthew.d.roper@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Navare, Manasi D
> <manasi.d.navare@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes
> for uncompressed joiner
>
> On Thu, 03 Jun 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> >> From: Animesh Manna <animesh.manna@intel.com>
> >>
> >> Respective bit for master or slave to be set for uncompressed
> >> bigjoiner in dss_ctl1 register.
> >
> > I was looking at the changes here due to a static checker complaint,
> > and I think there are a number of issues here. Some more serious than
> > others, and some predate the patch.
> >
> > Comments inline.
> >
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display.c | 6 +++
> >> drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
> >> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
> >> drivers/gpu/drm/i915/i915_reg.h | 2 +
> >> 4 files changed, 49 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index b5fd721137d3..422b59ebf6dc 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
> >> const struct intel_crtc_state
> *crtc_state) {
> >> struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> >> + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
> >> struct intel_crtc_state *master_crtc_state;
> >> struct drm_connector_state *conn_state;
> >> struct drm_connector *conn;
> >> @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
> >> /* and DSC on slave */
> >> intel_dsc_enable(NULL, crtc_state);
> >> }
> >> +
> >> + if (DISPLAY_VER(dev_priv) >= 13)
>
> I don't think we should add these checks here. Make sure the crtc_state only has
> the relevant stuff enabled if the platform supports it. Don't duplicate the checks.
Agree.
>
> >> + intel_uncompressed_joiner_enable(crtc_state);
>
> As this is always called after intel_dsc_enable(), I think it would make sense to
> move this within intel_dsc_enable().
Agree.
>
> >> }
> >>
> >> static void hsw_crtc_enable(struct intel_atomic_state *state, @@
> >> -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> >> }
> >>
> >> intel_dsc_get_config(pipe_config);
> >> + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
> >dsc.compression_enable)
> >> + intel_uncompressed_joiner_get_config(pipe_config);
>
> As this is always called after intel_dsc_get_config(), I think it would make sense
> to move this within intel_dsc_get_config.
>
> >>
> >> if (!active) {
> >> /* bigjoiner slave doesn't enable transcoder */ diff --git
> >> a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> index adcd6752f919..efc3184d8315 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
> intel_crtc_state *crtc_state)
> >> return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) :
> >> DSS_CTL2; }
> >>
> >> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> >> +*crtc_state)
> >
> > Naming. Basically for any new function, the function name prefix
> > should match the file name. intel_vdsc.[ch] should have functions
> > prefixed intel_vdsc_*(). This is where we're headed to increase clarity.
> >
> > intel_uncompressed_*() is something completely different.
> >
> > Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should
> > probably stick with intel_dsc_*(). A possible function or file rename
> > is not out of the question, but that's a separate matter.
> >
> >> +{
> >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> + u32 dss_ctl1_val = 0;
> >> +
> >> + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
> >> + if (crtc_state->bigjoiner_slave)
> >> + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
> >> + else
> >> + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
> >> +
> >> + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> >> + }
> >> +}
> >> +
> >> void intel_dsc_enable(struct intel_encoder *encoder,
> >> const struct intel_crtc_state *crtc_state) { @@ -1060,13
> >> +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state
> *old_crtc_state)
> >> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >>
> >> - if (!old_crtc_state->dsc.compression_enable)
> >> + if (!(old_crtc_state->dsc.compression_enable &&
> >> + old_crtc_state->bigjoiner))
> >
> > This fails to disable compression if we only have compression but no
> > bigjoiner, which is the more common case!
> >
> > See also:
> >
> > https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> > https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-v
> > andita.kulkarni@intel.com
> >
> >> return;
> >>
> >> intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> >> intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); }
> >>
> >> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> >> +*crtc_state) {
> >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> + u32 dss_ctl1;
> >> +
> >> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
>
> You can't read this without holding the power domain.
>
> Since this is always called after intel_dsc_get_config(), I think it would make
> sense to move this reading there.
Ok.
Earlier the plan is to have separate functions for uncompressed joiner, but as you suggested it can be done in the same functions of compressed bigjoiner code.
Thanks Jani for review.
Regards,
Animesh
>
> >> + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
> >> + crtc_state->bigjoiner = true;
> >> + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> >> + crtc_state->bigjoiner_linked_crtc =
> >> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe +
> 1);
> >> + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
> >> + crtc_state->bigjoiner = true;
> >> + crtc_state->bigjoiner_slave = true;
> >> + if (!WARN_ON(crtc->pipe == PIPE_A))
> >> + crtc_state->bigjoiner_linked_crtc =
> >> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
> 1);
> >> + }
> >
> > Nitpick: This duplicates a bunch of logic for figuring out master/slave.
> >
> > The static checker warning was about crtc->pipe + 1 usage. Since
> > INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
> > checker has a hard time figuring out it does not overflow
> > i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
> >
> > So here in intel_vdsc.c the checks are for overflowing/underflowing
> > the pipe range. In intel_get_crtc_for_pipe() there's a check for the
> > pipe actually existing - the pipe numbering might not be contiguous.
> >
> > Superficially the static checker warning is bogus, as in we won't
> > overflow anything. However, deep down there are issues in the
> > consistency of the checks and how to handle non-contigouous pipe
> > numbering.
> >
> > Indeed, this does not *need* the number. We should figure out the next
> > *crtc*, not the next pipe *number*, which may or may not be pipe + 1.
> >
> >
> > BR,
> > Jani.
> >
> >> +}
> >> +
> >> void intel_dsc_get_config(struct intel_crtc_state *crtc_state) {
> >> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; diff
> >> --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> b/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> index 65d301c23580..fe4d45561253 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> @@ -12,11 +12,13 @@ struct intel_encoder; struct intel_crtc_state;
> >>
> >> bool intel_dsc_source_support(const struct intel_crtc_state
> >> *crtc_state);
> >> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> >> +*crtc_state);
> >> void intel_dsc_enable(struct intel_encoder *encoder,
> >> const struct intel_crtc_state *crtc_state); void
> >> intel_dsc_disable(const struct intel_crtc_state *crtc_state); int
> >> intel_dsc_compute_params(struct intel_encoder *encoder,
> >> struct intel_crtc_state *pipe_config);
> >> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> >> +*crtc_state);
> >> void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
> >> enum intel_display_power_domain intel_dsc_power_domain(const struct
> >> intel_crtc_state *crtc_state); diff --git
> >> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 31bc413dbba1..dd6e0bae9573 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -11493,6 +11493,8 @@ enum skl_power_gate {
> >> #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> >> #define SPLITTER_CONFIGURATION_2_SEGMENT
> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> >> #define SPLITTER_CONFIGURATION_4_SEGMENT
> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> >> +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
> >> +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
> >>
> >> #define _ICL_PIPE_DSS_CTL2_PB 0x78204
> >> #define _ICL_PIPE_DSS_CTL2_PC 0x78404
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-06-03 13:49 ` Manna, Animesh
@ 2021-06-03 18:27 ` Navare, Manasi
2021-06-04 9:11 ` Jani Nikula
0 siblings, 1 reply; 33+ messages in thread
From: Navare, Manasi @ 2021-06-03 18:27 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
On Thu, Jun 03, 2021 at 06:49:23AM -0700, Manna, Animesh wrote:
>
>
> > -----Original Message-----
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Thursday, June 3, 2021 6:03 PM
> > To: Roper, Matthew D <matthew.d.roper@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Manna, Animesh <animesh.manna@intel.com>; Navare, Manasi D
> > <manasi.d.navare@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes
> > for uncompressed joiner
> >
> > On Thu, 03 Jun 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > > On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> > >> From: Animesh Manna <animesh.manna@intel.com>
> > >>
> > >> Respective bit for master or slave to be set for uncompressed
> > >> bigjoiner in dss_ctl1 register.
> > >
> > > I was looking at the changes here due to a static checker complaint,
> > > and I think there are a number of issues here. Some more serious than
> > > others, and some predate the patch.
> > >
> > > Comments inline.
> > >
> > >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> > >> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > >> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> > >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> > >> ---
> > >> drivers/gpu/drm/i915/display/intel_display.c | 6 +++
> > >> drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
> > >> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
> > >> drivers/gpu/drm/i915/i915_reg.h | 2 +
> > >> 4 files changed, 49 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > >> b/drivers/gpu/drm/i915/display/intel_display.c
> > >> index b5fd721137d3..422b59ebf6dc 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > >> @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> > intel_atomic_state *state,
> > >> const struct intel_crtc_state
> > *crtc_state) {
> > >> struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> > >> + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
> > >> struct intel_crtc_state *master_crtc_state;
> > >> struct drm_connector_state *conn_state;
> > >> struct drm_connector *conn;
> > >> @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> > intel_atomic_state *state,
> > >> /* and DSC on slave */
> > >> intel_dsc_enable(NULL, crtc_state);
> > >> }
> > >> +
> > >> + if (DISPLAY_VER(dev_priv) >= 13)
> >
> > I don't think we should add these checks here. Make sure the crtc_state only has
> > the relevant stuff enabled if the platform supports it. Don't duplicate the checks.
>
> Agree.
>
> >
> > >> + intel_uncompressed_joiner_enable(crtc_state);
> >
> > As this is always called after intel_dsc_enable(), I think it would make sense to
> > move this within intel_dsc_enable().
>
> Agree.
@Jani I had asked to create a separate joiner enable since having an uncompressed enable inside dsc_enable
just from the names makes it contradicting.
But sure may be with a comment before calling uncompressed_joiner_enable() it can be just called from inside dsc enable()
And instead of checking the display ver there we just use this condition:
if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
intel_uncompressed_joiner_enable(crtc_state);
}
Since the atomic check ensures that only for ver >=13 is when we allow big joiner and no DSC combination.
Animesh, Jani does that sound good?
Manasi
> >
> > >> }
> > >>
> > >> static void hsw_crtc_enable(struct intel_atomic_state *state, @@
> > >> -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > >> }
> > >>
> > >> intel_dsc_get_config(pipe_config);
> > >> + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
> > >dsc.compression_enable)
> > >> + intel_uncompressed_joiner_get_config(pipe_config);
> >
> > As this is always called after intel_dsc_get_config(), I think it would make sense
> > to move this within intel_dsc_get_config.
> >
> > >>
> > >> if (!active) {
> > >> /* bigjoiner slave doesn't enable transcoder */ diff --git
> > >> a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> index adcd6752f919..efc3184d8315 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
> > intel_crtc_state *crtc_state)
> > >> return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) :
> > >> DSS_CTL2; }
> > >>
> > >> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> > >> +*crtc_state)
> > >
> > > Naming. Basically for any new function, the function name prefix
> > > should match the file name. intel_vdsc.[ch] should have functions
> > > prefixed intel_vdsc_*(). This is where we're headed to increase clarity.
> > >
> > > intel_uncompressed_*() is something completely different.
> > >
> > > Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should
> > > probably stick with intel_dsc_*(). A possible function or file rename
> > > is not out of the question, but that's a separate matter.
> > >
> > >> +{
> > >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >> + u32 dss_ctl1_val = 0;
> > >> +
> > >> + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
> > >> + if (crtc_state->bigjoiner_slave)
> > >> + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
> > >> + else
> > >> + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
> > >> +
> > >> + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> > >> + }
> > >> +}
> > >> +
> > >> void intel_dsc_enable(struct intel_encoder *encoder,
> > >> const struct intel_crtc_state *crtc_state) { @@ -1060,13
> > >> +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state
> > *old_crtc_state)
> > >> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >>
> > >> - if (!old_crtc_state->dsc.compression_enable)
> > >> + if (!(old_crtc_state->dsc.compression_enable &&
> > >> + old_crtc_state->bigjoiner))
> > >
> > > This fails to disable compression if we only have compression but no
> > > bigjoiner, which is the more common case!
> > >
> > > See also:
> > >
> > > https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> > > https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-v
> > > andita.kulkarni@intel.com
> > >
> > >> return;
> > >>
> > >> intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> > >> intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); }
> > >>
> > >> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> > >> +*crtc_state) {
> > >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >> + u32 dss_ctl1;
> > >> +
> > >> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> >
> > You can't read this without holding the power domain.
> >
> > Since this is always called after intel_dsc_get_config(), I think it would make
> > sense to move this reading there.
>
> Ok.
> Earlier the plan is to have separate functions for uncompressed joiner, but as you suggested it can be done in the same functions of compressed bigjoiner code.
> Thanks Jani for review.
>
> Regards,
> Animesh
>
> >
> > >> + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
> > >> + crtc_state->bigjoiner = true;
> > >> + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> > >> + crtc_state->bigjoiner_linked_crtc =
> > >> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe +
> > 1);
> > >> + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
> > >> + crtc_state->bigjoiner = true;
> > >> + crtc_state->bigjoiner_slave = true;
> > >> + if (!WARN_ON(crtc->pipe == PIPE_A))
> > >> + crtc_state->bigjoiner_linked_crtc =
> > >> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
> > 1);
> > >> + }
> > >
> > > Nitpick: This duplicates a bunch of logic for figuring out master/slave.
> > >
> > > The static checker warning was about crtc->pipe + 1 usage. Since
> > > INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
> > > checker has a hard time figuring out it does not overflow
> > > i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
> > >
> > > So here in intel_vdsc.c the checks are for overflowing/underflowing
> > > the pipe range. In intel_get_crtc_for_pipe() there's a check for the
> > > pipe actually existing - the pipe numbering might not be contiguous.
> > >
> > > Superficially the static checker warning is bogus, as in we won't
> > > overflow anything. However, deep down there are issues in the
> > > consistency of the checks and how to handle non-contigouous pipe
> > > numbering.
> > >
> > > Indeed, this does not *need* the number. We should figure out the next
> > > *crtc*, not the next pipe *number*, which may or may not be pipe + 1.
> > >
> > >
> > > BR,
> > > Jani.
> > >
> > >> +}
> > >> +
> > >> void intel_dsc_get_config(struct intel_crtc_state *crtc_state) {
> > >> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; diff
> > >> --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > >> b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > >> index 65d301c23580..fe4d45561253 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > >> @@ -12,11 +12,13 @@ struct intel_encoder; struct intel_crtc_state;
> > >>
> > >> bool intel_dsc_source_support(const struct intel_crtc_state
> > >> *crtc_state);
> > >> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> > >> +*crtc_state);
> > >> void intel_dsc_enable(struct intel_encoder *encoder,
> > >> const struct intel_crtc_state *crtc_state); void
> > >> intel_dsc_disable(const struct intel_crtc_state *crtc_state); int
> > >> intel_dsc_compute_params(struct intel_encoder *encoder,
> > >> struct intel_crtc_state *pipe_config);
> > >> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> > >> +*crtc_state);
> > >> void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
> > >> enum intel_display_power_domain intel_dsc_power_domain(const struct
> > >> intel_crtc_state *crtc_state); diff --git
> > >> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > >> index 31bc413dbba1..dd6e0bae9573 100644
> > >> --- a/drivers/gpu/drm/i915/i915_reg.h
> > >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> > >> @@ -11493,6 +11493,8 @@ enum skl_power_gate {
> > >> #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> > >> #define SPLITTER_CONFIGURATION_2_SEGMENT
> > REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> > >> #define SPLITTER_CONFIGURATION_4_SEGMENT
> > REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> > >> +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
> > >> +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
> > >>
> > >> #define _ICL_PIPE_DSS_CTL2_PB 0x78204
> > >> #define _ICL_PIPE_DSS_CTL2_PC 0x78404
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-06-03 18:27 ` Navare, Manasi
@ 2021-06-04 9:11 ` Jani Nikula
0 siblings, 0 replies; 33+ messages in thread
From: Jani Nikula @ 2021-06-04 9:11 UTC (permalink / raw)
To: Navare, Manasi, Manna, Animesh; +Cc: intel-gfx
On Thu, 03 Jun 2021, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> On Thu, Jun 03, 2021 at 06:49:23AM -0700, Manna, Animesh wrote:
>>
>>
>> > -----Original Message-----
>> > From: Jani Nikula <jani.nikula@linux.intel.com>
>> > Sent: Thursday, June 3, 2021 6:03 PM
>> > To: Roper, Matthew D <matthew.d.roper@intel.com>; intel-
>> > gfx@lists.freedesktop.org
>> > Cc: Manna, Animesh <animesh.manna@intel.com>; Navare, Manasi D
>> > <manasi.d.navare@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> > Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes
>> > for uncompressed joiner
>> >
>> > On Thu, 03 Jun 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> > > On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> > >> From: Animesh Manna <animesh.manna@intel.com>
>> > >>
>> > >> Respective bit for master or slave to be set for uncompressed
>> > >> bigjoiner in dss_ctl1 register.
>> > >
>> > > I was looking at the changes here due to a static checker complaint,
>> > > and I think there are a number of issues here. Some more serious than
>> > > others, and some predate the patch.
>> > >
>> > > Comments inline.
>> > >
>> > >> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> > >> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> > >> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
>> > >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>> > >> ---
>> > >> drivers/gpu/drm/i915/display/intel_display.c | 6 +++
>> > >> drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
>> > >> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
>> > >> drivers/gpu/drm/i915/i915_reg.h | 2 +
>> > >> 4 files changed, 49 insertions(+), 1 deletion(-)
>> > >>
>> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > >> b/drivers/gpu/drm/i915/display/intel_display.c
>> > >> index b5fd721137d3..422b59ebf6dc 100644
>> > >> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > >> @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
>> > intel_atomic_state *state,
>> > >> const struct intel_crtc_state
>> > *crtc_state) {
>> > >> struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
>> > >> + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
>> > >> struct intel_crtc_state *master_crtc_state;
>> > >> struct drm_connector_state *conn_state;
>> > >> struct drm_connector *conn;
>> > >> @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
>> > intel_atomic_state *state,
>> > >> /* and DSC on slave */
>> > >> intel_dsc_enable(NULL, crtc_state);
>> > >> }
>> > >> +
>> > >> + if (DISPLAY_VER(dev_priv) >= 13)
>> >
>> > I don't think we should add these checks here. Make sure the crtc_state only has
>> > the relevant stuff enabled if the platform supports it. Don't duplicate the checks.
>>
>> Agree.
>
>
>>
>> >
>> > >> + intel_uncompressed_joiner_enable(crtc_state);
>> >
>> > As this is always called after intel_dsc_enable(), I think it would make sense to
>> > move this within intel_dsc_enable().
>>
>> Agree.
>
> @Jani I had asked to create a separate joiner enable since having an uncompressed enable inside dsc_enable
> just from the names makes it contradicting.
> But sure may be with a comment before calling uncompressed_joiner_enable() it can be just called from inside dsc enable()
> And instead of checking the display ver there we just use this condition:
> if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
> intel_uncompressed_joiner_enable(crtc_state);
> }
> Since the atomic check ensures that only for ver >=13 is when we allow big joiner and no DSC combination.
>
> Animesh, Jani does that sound good?
Yes.
Regarding naming semantics, I think we just need to consider DSC an
engine that does other things than just compression. The actual
registers being the same makes, I think, the logic harder to follow with
these being separate steps. Also, you can then cover them with a single
power domain get/put.
Anyway, care must be taken to not change the logic for compressed paths.
BR,
Jani.
>
> Manasi
>
>
>> >
>> > >> }
>> > >>
>> > >> static void hsw_crtc_enable(struct intel_atomic_state *state, @@
>> > >> -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>> > >> }
>> > >>
>> > >> intel_dsc_get_config(pipe_config);
>> > >> + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
>> > >dsc.compression_enable)
>> > >> + intel_uncompressed_joiner_get_config(pipe_config);
>> >
>> > As this is always called after intel_dsc_get_config(), I think it would make sense
>> > to move this within intel_dsc_get_config.
>> >
>> > >>
>> > >> if (!active) {
>> > >> /* bigjoiner slave doesn't enable transcoder */ diff --git
>> > >> a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > >> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > >> index adcd6752f919..efc3184d8315 100644
>> > >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > >> @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
>> > intel_crtc_state *crtc_state)
>> > >> return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) :
>> > >> DSS_CTL2; }
>> > >>
>> > >> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
>> > >> +*crtc_state)
>> > >
>> > > Naming. Basically for any new function, the function name prefix
>> > > should match the file name. intel_vdsc.[ch] should have functions
>> > > prefixed intel_vdsc_*(). This is where we're headed to increase clarity.
>> > >
>> > > intel_uncompressed_*() is something completely different.
>> > >
>> > > Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should
>> > > probably stick with intel_dsc_*(). A possible function or file rename
>> > > is not out of the question, but that's a separate matter.
>> > >
>> > >> +{
>> > >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > >> + u32 dss_ctl1_val = 0;
>> > >> +
>> > >> + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
>> > >> + if (crtc_state->bigjoiner_slave)
>> > >> + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
>> > >> + else
>> > >> + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
>> > >> +
>> > >> + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
>> > >> + }
>> > >> +}
>> > >> +
>> > >> void intel_dsc_enable(struct intel_encoder *encoder,
>> > >> const struct intel_crtc_state *crtc_state) { @@ -1060,13
>> > >> +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state
>> > *old_crtc_state)
>> > >> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>> > >> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > >>
>> > >> - if (!old_crtc_state->dsc.compression_enable)
>> > >> + if (!(old_crtc_state->dsc.compression_enable &&
>> > >> + old_crtc_state->bigjoiner))
>> > >
>> > > This fails to disable compression if we only have compression but no
>> > > bigjoiner, which is the more common case!
>> > >
>> > > See also:
>> > >
>> > > https://gitlab.freedesktop.org/drm/intel/-/issues/3537
>> > > https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-v
>> > > andita.kulkarni@intel.com
>> > >
>> > >> return;
>> > >>
>> > >> intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
>> > >> intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); }
>> > >>
>> > >> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
>> > >> +*crtc_state) {
>> > >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > >> + u32 dss_ctl1;
>> > >> +
>> > >> + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
>> >
>> > You can't read this without holding the power domain.
>> >
>> > Since this is always called after intel_dsc_get_config(), I think it would make
>> > sense to move this reading there.
>>
>> Ok.
>> Earlier the plan is to have separate functions for uncompressed joiner, but as you suggested it can be done in the same functions of compressed bigjoiner code.
>> Thanks Jani for review.
>>
>> Regards,
>> Animesh
>>
>> >
>> > >> + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
>> > >> + crtc_state->bigjoiner = true;
>> > >> + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
>> > >> + crtc_state->bigjoiner_linked_crtc =
>> > >> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe +
>> > 1);
>> > >> + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
>> > >> + crtc_state->bigjoiner = true;
>> > >> + crtc_state->bigjoiner_slave = true;
>> > >> + if (!WARN_ON(crtc->pipe == PIPE_A))
>> > >> + crtc_state->bigjoiner_linked_crtc =
>> > >> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
>> > 1);
>> > >> + }
>> > >
>> > > Nitpick: This duplicates a bunch of logic for figuring out master/slave.
>> > >
>> > > The static checker warning was about crtc->pipe + 1 usage. Since
>> > > INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
>> > > checker has a hard time figuring out it does not overflow
>> > > i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
>> > >
>> > > So here in intel_vdsc.c the checks are for overflowing/underflowing
>> > > the pipe range. In intel_get_crtc_for_pipe() there's a check for the
>> > > pipe actually existing - the pipe numbering might not be contiguous.
>> > >
>> > > Superficially the static checker warning is bogus, as in we won't
>> > > overflow anything. However, deep down there are issues in the
>> > > consistency of the checks and how to handle non-contigouous pipe
>> > > numbering.
>> > >
>> > > Indeed, this does not *need* the number. We should figure out the next
>> > > *crtc*, not the next pipe *number*, which may or may not be pipe + 1.
>> > >
>> > >
>> > > BR,
>> > > Jani.
>> > >
>> > >> +}
>> > >> +
>> > >> void intel_dsc_get_config(struct intel_crtc_state *crtc_state) {
>> > >> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; diff
>> > >> --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > >> b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > >> index 65d301c23580..fe4d45561253 100644
>> > >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > >> @@ -12,11 +12,13 @@ struct intel_encoder; struct intel_crtc_state;
>> > >>
>> > >> bool intel_dsc_source_support(const struct intel_crtc_state
>> > >> *crtc_state);
>> > >> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
>> > >> +*crtc_state);
>> > >> void intel_dsc_enable(struct intel_encoder *encoder,
>> > >> const struct intel_crtc_state *crtc_state); void
>> > >> intel_dsc_disable(const struct intel_crtc_state *crtc_state); int
>> > >> intel_dsc_compute_params(struct intel_encoder *encoder,
>> > >> struct intel_crtc_state *pipe_config);
>> > >> +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
>> > >> +*crtc_state);
>> > >> void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>> > >> enum intel_display_power_domain intel_dsc_power_domain(const struct
>> > >> intel_crtc_state *crtc_state); diff --git
>> > >> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > >> index 31bc413dbba1..dd6e0bae9573 100644
>> > >> --- a/drivers/gpu/drm/i915/i915_reg.h
>> > >> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > >> @@ -11493,6 +11493,8 @@ enum skl_power_gate {
>> > >> #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
>> > >> #define SPLITTER_CONFIGURATION_2_SEGMENT
>> > REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> > >> #define SPLITTER_CONFIGURATION_4_SEGMENT
>> > REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> > >> +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
>> > >> +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
>> > >>
>> > >> #define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> > >> #define _ICL_PIPE_DSS_CTL2_PC 0x78404
>> >
>> > --
>> > Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-06-03 9:39 ` Jani Nikula
2021-06-03 12:33 ` Jani Nikula
@ 2021-06-03 13:37 ` Manna, Animesh
2021-06-03 15:41 ` Jani Nikula
1 sibling, 1 reply; 33+ messages in thread
From: Manna, Animesh @ 2021-06-03 13:37 UTC (permalink / raw)
To: Jani Nikula, Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, June 3, 2021 3:10 PM
> To: Roper, Matthew D <matthew.d.roper@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Navare, Manasi D
> <manasi.d.navare@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes
> for uncompressed joiner
>
> On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> > From: Animesh Manna <animesh.manna@intel.com>
> >
> > Respective bit for master or slave to be set for uncompressed
> > bigjoiner in dss_ctl1 register.
>
> I was looking at the changes here due to a static checker complaint, and I think
> there are a number of issues here. Some more serious than others, and some
> predate the patch.
>
> Comments inline.
>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 6 +++
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
> > drivers/gpu/drm/i915/i915_reg.h | 2 +
> > 4 files changed, 49 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index b5fd721137d3..422b59ebf6dc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
> > const struct intel_crtc_state
> *crtc_state) {
> > struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
> > struct intel_crtc_state *master_crtc_state;
> > struct drm_connector_state *conn_state;
> > struct drm_connector *conn;
> > @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> intel_atomic_state *state,
> > /* and DSC on slave */
> > intel_dsc_enable(NULL, crtc_state);
> > }
> > +
> > + if (DISPLAY_VER(dev_priv) >= 13)
> > + intel_uncompressed_joiner_enable(crtc_state);
> > }
> >
> > static void hsw_crtc_enable(struct intel_atomic_state *state, @@
> > -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > }
> >
> > intel_dsc_get_config(pipe_config);
> > + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
> >dsc.compression_enable)
> > + intel_uncompressed_joiner_get_config(pipe_config);
> >
> > if (!active) {
> > /* bigjoiner slave doesn't enable transcoder */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index adcd6752f919..efc3184d8315 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
> intel_crtc_state *crtc_state)
> > return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
> > }
> >
> > +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> > +*crtc_state)
>
> Naming. Basically for any new function, the function name prefix should match
> the file name. intel_vdsc.[ch] should have functions prefixed intel_vdsc_*(). This
> is where we're headed to increase clarity.
>
> intel_uncompressed_*() is something completely different.
>
> Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should probably
> stick with intel_dsc_*(). A possible function or file rename is not out of the
> question, but that's a separate matter.
As there is not separate register for uncompressed joiner, using bitfield of dsc register only the function name can be changed to intel_dsc_uncompressed_joiner_enable().
>
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + u32 dss_ctl1_val = 0;
> > +
> > + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
> > + if (crtc_state->bigjoiner_slave)
> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
> > + else
> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
> > +
> > + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> > + }
> > +}
> > +
> > void intel_dsc_enable(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state) { @@ -1060,13
> > +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state
> *old_crtc_state)
> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > - if (!old_crtc_state->dsc.compression_enable)
> > + if (!(old_crtc_state->dsc.compression_enable &&
> > + old_crtc_state->bigjoiner))
>
> This fails to disable compression if we only have compression but no bigjoiner,
> which is the more common case!
>
> See also:
>
> https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-
> vandita.kulkarni@intel.com
>
We may need to remove both the condition check.
In uncompressed bigjoiner, compression_enable flag will be 0 and may not clear the bit of dss_ctl1_reg.
So can we remove both the checks, hoping it will not harm reseting the register even if it is not set.
> > return;
> >
> > intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> > intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); }
> >
> > +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> > +*crtc_state) {
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + u32 dss_ctl1;
> > +
> > + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> > + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
> > + crtc_state->bigjoiner = true;
> > + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> > + crtc_state->bigjoiner_linked_crtc =
> > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe +
> 1);
> > + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
> > + crtc_state->bigjoiner = true;
> > + crtc_state->bigjoiner_slave = true;
> > + if (!WARN_ON(crtc->pipe == PIPE_A))
> > + crtc_state->bigjoiner_linked_crtc =
> > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
> 1);
> > + }
>
> Nitpick: This duplicates a bunch of logic for figuring out master/slave.
>
> The static checker warning was about crtc->pipe + 1 usage. Since
> INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
> checker has a hard time figuring out it does not overflow
> i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
>
> So here in intel_vdsc.c the checks are for overflowing/underflowing the pipe
> range. In intel_get_crtc_for_pipe() there's a check for the pipe actually existing -
> the pipe numbering might not be contiguous.
>
> Superficially the static checker warning is bogus, as in we won't overflow
> anything. However, deep down there are issues in the consistency of the checks
> and how to handle non-contigouous pipe numbering.
>
> Indeed, this does not *need* the number. We should figure out the next *crtc*,
> not the next pipe *number*, which may or may not be pipe + 1.
dss_ctl1 value is used to identify master or slave crtc. If needed WARN_ON check can be removed... but pipe enum values like PIPE_A/B/C/D is used to get the master/slave crtc and always bigjoiner is possible with two adjacent pipes.
Regards,
Animesh
>
>
> BR,
> Jani.
>
> > +}
> > +
> > void intel_dsc_get_config(struct intel_crtc_state *crtc_state) {
> > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; diff
> > --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > index 65d301c23580..fe4d45561253 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> > @@ -12,11 +12,13 @@ struct intel_encoder; struct intel_crtc_state;
> >
> > bool intel_dsc_source_support(const struct intel_crtc_state
> > *crtc_state);
> > +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> > +*crtc_state);
> > void intel_dsc_enable(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state); void
> > intel_dsc_disable(const struct intel_crtc_state *crtc_state); int
> > intel_dsc_compute_params(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config);
> > +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> > +*crtc_state);
> > void intel_dsc_get_config(struct intel_crtc_state *crtc_state); enum
> > intel_display_power_domain intel_dsc_power_domain(const struct
> > intel_crtc_state *crtc_state); diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 31bc413dbba1..dd6e0bae9573 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -11493,6 +11493,8 @@ enum skl_power_gate {
> > #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> > #define SPLITTER_CONFIGURATION_2_SEGMENT
> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> > #define SPLITTER_CONFIGURATION_4_SEGMENT
> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> > +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
> > +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
> >
> > #define _ICL_PIPE_DSS_CTL2_PB 0x78204
> > #define _ICL_PIPE_DSS_CTL2_PC 0x78404
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-06-03 13:37 ` Manna, Animesh
@ 2021-06-03 15:41 ` Jani Nikula
2021-06-04 8:54 ` Manna, Animesh
0 siblings, 1 reply; 33+ messages in thread
From: Jani Nikula @ 2021-06-03 15:41 UTC (permalink / raw)
To: Manna, Animesh, Roper, Matthew D, intel-gfx
On Thu, 03 Jun 2021, "Manna, Animesh" <animesh.manna@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Thursday, June 3, 2021 3:10 PM
>> To: Roper, Matthew D <matthew.d.roper@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Navare, Manasi D
>> <manasi.d.navare@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes
>> for uncompressed joiner
>>
>> On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>> > From: Animesh Manna <animesh.manna@intel.com>
>> >
>> > Respective bit for master or slave to be set for uncompressed
>> > bigjoiner in dss_ctl1 register.
>>
>> I was looking at the changes here due to a static checker complaint, and I think
>> there are a number of issues here. Some more serious than others, and some
>> predate the patch.
>>
>> Comments inline.
>>
>> > Cc: Manasi Navare <manasi.d.navare@intel.com>
>> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> > Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_display.c | 6 +++
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
>> > drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
>> > drivers/gpu/drm/i915/i915_reg.h | 2 +
>> > 4 files changed, 49 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index b5fd721137d3..422b59ebf6dc 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
>> intel_atomic_state *state,
>> > const struct intel_crtc_state
>> *crtc_state) {
>> > struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
>> > + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
>> > struct intel_crtc_state *master_crtc_state;
>> > struct drm_connector_state *conn_state;
>> > struct drm_connector *conn;
>> > @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
>> intel_atomic_state *state,
>> > /* and DSC on slave */
>> > intel_dsc_enable(NULL, crtc_state);
>> > }
>> > +
>> > + if (DISPLAY_VER(dev_priv) >= 13)
>> > + intel_uncompressed_joiner_enable(crtc_state);
>> > }
>> >
>> > static void hsw_crtc_enable(struct intel_atomic_state *state, @@
>> > -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>> > }
>> >
>> > intel_dsc_get_config(pipe_config);
>> > + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
>> >dsc.compression_enable)
>> > + intel_uncompressed_joiner_get_config(pipe_config);
>> >
>> > if (!active) {
>> > /* bigjoiner slave doesn't enable transcoder */ diff --git
>> > a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index adcd6752f919..efc3184d8315 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
>> intel_crtc_state *crtc_state)
>> > return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
>> > }
>> >
>> > +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
>> > +*crtc_state)
>>
>> Naming. Basically for any new function, the function name prefix should match
>> the file name. intel_vdsc.[ch] should have functions prefixed intel_vdsc_*(). This
>> is where we're headed to increase clarity.
>>
>> intel_uncompressed_*() is something completely different.
>>
>> Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should probably
>> stick with intel_dsc_*(). A possible function or file rename is not out of the
>> question, but that's a separate matter.
>
> As there is not separate register for uncompressed joiner, using bitfield of dsc register only the function name can be changed to intel_dsc_uncompressed_joiner_enable().
>
>>
>> > +{
>> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > + u32 dss_ctl1_val = 0;
>> > +
>> > + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
>> > + if (crtc_state->bigjoiner_slave)
>> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
>> > + else
>> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
>> > +
>> > + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
>> > + }
>> > +}
>> > +
>> > void intel_dsc_enable(struct intel_encoder *encoder,
>> > const struct intel_crtc_state *crtc_state) { @@ -1060,13
>> > +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state
>> *old_crtc_state)
>> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >
>> > - if (!old_crtc_state->dsc.compression_enable)
>> > + if (!(old_crtc_state->dsc.compression_enable &&
>> > + old_crtc_state->bigjoiner))
>>
>> This fails to disable compression if we only have compression but no bigjoiner,
>> which is the more common case!
>>
>> See also:
>>
>> https://gitlab.freedesktop.org/drm/intel/-/issues/3537
>> https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-
>> vandita.kulkarni@intel.com
>>
>
> We may need to remove both the condition check.
> In uncompressed bigjoiner, compression_enable flag will be 0 and may not clear the bit of dss_ctl1_reg.
> So can we remove both the checks, hoping it will not harm reseting the register even if it is not set.
Now it only disables if *both* were enabled. It needs to be disabled if
*either* was enabled. But if *neither* was enabled, we don't need to do
this.
>
>> > return;
>> >
>> > intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
>> > intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); }
>> >
>> > +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
>> > +*crtc_state) {
>> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > + u32 dss_ctl1;
>> > +
>> > + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
>> > + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
>> > + crtc_state->bigjoiner = true;
>> > + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
>> > + crtc_state->bigjoiner_linked_crtc =
>> > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe +
>> 1);
>> > + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
>> > + crtc_state->bigjoiner = true;
>> > + crtc_state->bigjoiner_slave = true;
>> > + if (!WARN_ON(crtc->pipe == PIPE_A))
>> > + crtc_state->bigjoiner_linked_crtc =
>> > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
>> 1);
>> > + }
>>
>> Nitpick: This duplicates a bunch of logic for figuring out master/slave.
>>
>> The static checker warning was about crtc->pipe + 1 usage. Since
>> INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
>> checker has a hard time figuring out it does not overflow
>> i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
>>
>> So here in intel_vdsc.c the checks are for overflowing/underflowing the pipe
>> range. In intel_get_crtc_for_pipe() there's a check for the pipe actually existing -
>> the pipe numbering might not be contiguous.
>>
>> Superficially the static checker warning is bogus, as in we won't overflow
>> anything. However, deep down there are issues in the consistency of the checks
>> and how to handle non-contigouous pipe numbering.
>>
>> Indeed, this does not *need* the number. We should figure out the next *crtc*,
>> not the next pipe *number*, which may or may not be pipe + 1.
>
> dss_ctl1 value is used to identify master or slave crtc. If needed WARN_ON check can be removed... but pipe enum values like PIPE_A/B/C/D is used to get the master/slave crtc and always bigjoiner is possible with two adjacent pipes.
I sent the patch for this and you reviewed it... but are adjacent pipes
a requirement for bigjoiner? Would e.g. A+C work if B was fused off? If
not, my patch 2/2 is incorrect.
BR,
Jani.
>
> Regards,
> Animesh
>
>>
>>
>> BR,
>> Jani.
>>
>> > +}
>> > +
>> > void intel_dsc_get_config(struct intel_crtc_state *crtc_state) {
>> > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; diff
>> > --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > index 65d301c23580..fe4d45561253 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
>> > @@ -12,11 +12,13 @@ struct intel_encoder; struct intel_crtc_state;
>> >
>> > bool intel_dsc_source_support(const struct intel_crtc_state
>> > *crtc_state);
>> > +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
>> > +*crtc_state);
>> > void intel_dsc_enable(struct intel_encoder *encoder,
>> > const struct intel_crtc_state *crtc_state); void
>> > intel_dsc_disable(const struct intel_crtc_state *crtc_state); int
>> > intel_dsc_compute_params(struct intel_encoder *encoder,
>> > struct intel_crtc_state *pipe_config);
>> > +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
>> > +*crtc_state);
>> > void intel_dsc_get_config(struct intel_crtc_state *crtc_state); enum
>> > intel_display_power_domain intel_dsc_power_domain(const struct
>> > intel_crtc_state *crtc_state); diff --git
>> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 31bc413dbba1..dd6e0bae9573 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -11493,6 +11493,8 @@ enum skl_power_gate {
>> > #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
>> > #define SPLITTER_CONFIGURATION_2_SEGMENT
>> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> > #define SPLITTER_CONFIGURATION_4_SEGMENT
>> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> > +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
>> > +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
>> >
>> > #define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> > #define _ICL_PIPE_DSS_CTL2_PC 0x78404
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
2021-06-03 15:41 ` Jani Nikula
@ 2021-06-04 8:54 ` Manna, Animesh
0 siblings, 0 replies; 33+ messages in thread
From: Manna, Animesh @ 2021-06-04 8:54 UTC (permalink / raw)
To: Jani Nikula, Roper, Matthew D, intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, June 3, 2021 9:12 PM
> To: Manna, Animesh <animesh.manna@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>
> Subject: RE: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes
> for uncompressed joiner
>
> On Thu, 03 Jun 2021, "Manna, Animesh" <animesh.manna@intel.com> wrote:
> >> -----Original Message-----
> >> From: Jani Nikula <jani.nikula@linux.intel.com>
> >> Sent: Thursday, June 3, 2021 3:10 PM
> >> To: Roper, Matthew D <matthew.d.roper@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: Manna, Animesh <animesh.manna@intel.com>; Navare, Manasi D
> >> <manasi.d.navare@intel.com>; Kulkarni, Vandita
> >> <vandita.kulkarni@intel.com>
> >> Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit
> >> changes for uncompressed joiner
> >>
> >> On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> >> > From: Animesh Manna <animesh.manna@intel.com>
> >> >
> >> > Respective bit for master or slave to be set for uncompressed
> >> > bigjoiner in dss_ctl1 register.
> >>
> >> I was looking at the changes here due to a static checker complaint,
> >> and I think there are a number of issues here. Some more serious than
> >> others, and some predate the patch.
> >>
> >> Comments inline.
> >>
> >> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> >> > Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> >> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/display/intel_display.c | 6 +++
> >> > drivers/gpu/drm/i915/display/intel_vdsc.c | 40 +++++++++++++++++++-
> >> > drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
> >> > drivers/gpu/drm/i915/i915_reg.h | 2 +
> >> > 4 files changed, 49 insertions(+), 1 deletion(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> > b/drivers/gpu/drm/i915/display/intel_display.c
> >> > index b5fd721137d3..422b59ebf6dc 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> > @@ -3411,6 +3411,7 @@ static void
> >> > icl_ddi_bigjoiner_pre_enable(struct
> >> intel_atomic_state *state,
> >> > const struct intel_crtc_state
> >> *crtc_state) {
> >> > struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
> >> > + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
> >> > struct intel_crtc_state *master_crtc_state;
> >> > struct drm_connector_state *conn_state;
> >> > struct drm_connector *conn;
> >> > @@ -3444,6 +3445,9 @@ static void
> >> > icl_ddi_bigjoiner_pre_enable(struct
> >> intel_atomic_state *state,
> >> > /* and DSC on slave */
> >> > intel_dsc_enable(NULL, crtc_state);
> >> > }
> >> > +
> >> > + if (DISPLAY_VER(dev_priv) >= 13)
> >> > + intel_uncompressed_joiner_enable(crtc_state);
> >> > }
> >> >
> >> > static void hsw_crtc_enable(struct intel_atomic_state *state, @@
> >> > -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc
> *crtc,
> >> > }
> >> >
> >> > intel_dsc_get_config(pipe_config);
> >> > + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
> >> >dsc.compression_enable)
> >> > + intel_uncompressed_joiner_get_config(pipe_config);
> >> >
> >> > if (!active) {
> >> > /* bigjoiner slave doesn't enable transcoder */ diff --git
> >> > a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > index adcd6752f919..efc3184d8315 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
> >> intel_crtc_state *crtc_state)
> >> > return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) :
> >> > DSS_CTL2; }
> >> >
> >> > +void intel_uncompressed_joiner_enable(const struct
> >> > +intel_crtc_state
> >> > +*crtc_state)
> >>
> >> Naming. Basically for any new function, the function name prefix
> >> should match the file name. intel_vdsc.[ch] should have functions
> >> prefixed intel_vdsc_*(). This is where we're headed to increase clarity.
> >>
> >> intel_uncompressed_*() is something completely different.
> >>
> >> Granted, here we already have intel_dsc_*() in intel_vdsc.c. We
> >> should probably stick with intel_dsc_*(). A possible function or file
> >> rename is not out of the question, but that's a separate matter.
> >
> > As there is not separate register for uncompressed joiner, using bitfield of dsc
> register only the function name can be changed to
> intel_dsc_uncompressed_joiner_enable().
> >
> >>
> >> > +{
> >> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > + u32 dss_ctl1_val = 0;
> >> > +
> >> > + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
> >> > + if (crtc_state->bigjoiner_slave)
> >> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
> >> > + else
> >> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
> >> > +
> >> > + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
> >> > + }
> >> > +}
> >> > +
> >> > void intel_dsc_enable(struct intel_encoder *encoder,
> >> > const struct intel_crtc_state *crtc_state) { @@ -1060,13
> >> > +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state
> >> *old_crtc_state)
> >> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> >> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> >
> >> > - if (!old_crtc_state->dsc.compression_enable)
> >> > + if (!(old_crtc_state->dsc.compression_enable &&
> >> > + old_crtc_state->bigjoiner))
> >>
> >> This fails to disable compression if we only have compression but no
> >> bigjoiner, which is the more common case!
> >>
> >> See also:
> >>
> >> https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> >> https://patchwork.freedesktop.org/patch/msgid/20210603065356.15435-1-
> >> vandita.kulkarni@intel.com
> >>
> >
> > We may need to remove both the condition check.
> > In uncompressed bigjoiner, compression_enable flag will be 0 and may not
> clear the bit of dss_ctl1_reg.
> > So can we remove both the checks, hoping it will not harm reseting the
> register even if it is not set.
>
> Now it only disables if *both* were enabled. It needs to be disabled if
> *either* was enabled. But if *neither* was enabled, we don't need to do this.
Ok.
>
>
> >
> >> > return;
> >> >
> >> > intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> >> > intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); }
> >> >
> >> > +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> >> > +*crtc_state) {
> >> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >> > + u32 dss_ctl1;
> >> > +
> >> > + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> >> > + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
> >> > + crtc_state->bigjoiner = true;
> >> > + if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> >> > + crtc_state->bigjoiner_linked_crtc =
> >> > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe +
> >> 1);
> >> > + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
> >> > + crtc_state->bigjoiner = true;
> >> > + crtc_state->bigjoiner_slave = true;
> >> > + if (!WARN_ON(crtc->pipe == PIPE_A))
> >> > + crtc_state->bigjoiner_linked_crtc =
> >> > + intel_get_crtc_for_pipe(dev_priv, crtc->pipe -
> >> 1);
> >> > + }
> >>
> >> Nitpick: This duplicates a bunch of logic for figuring out master/slave.
> >>
> >> The static checker warning was about crtc->pipe + 1 usage. Since
> >> INTEL_NUM_PIPES() looks at the hamming weight of i915->pipe_mask, the
> >> checker has a hard time figuring out it does not overflow
> >> i915->pipe_to_crtc_mapping[] in intel_get_crtc_for_pipe().
> >>
> >> So here in intel_vdsc.c the checks are for overflowing/underflowing
> >> the pipe range. In intel_get_crtc_for_pipe() there's a check for the
> >> pipe actually existing - the pipe numbering might not be contiguous.
> >>
> >> Superficially the static checker warning is bogus, as in we won't
> >> overflow anything. However, deep down there are issues in the
> >> consistency of the checks and how to handle non-contigouous pipe
> numbering.
> >>
> >> Indeed, this does not *need* the number. We should figure out the
> >> next *crtc*, not the next pipe *number*, which may or may not be pipe + 1.
> >
> > dss_ctl1 value is used to identify master or slave crtc. If needed WARN_ON
> check can be removed... but pipe enum values like PIPE_A/B/C/D is used to get
> the master/slave crtc and always bigjoiner is possible with two adjacent pipes.
>
> I sent the patch for this and you reviewed it... but are adjacent pipes a
> requirement for bigjoiner? Would e.g. A+C work if B was fused off? If not, my
> patch 2/2 is incorrect.
Yes, I am also tried to check again in bspec. Adjacent pipe is needed for bigjoiner though have not mentioned anything in case of pipe fusing.
Regards,
Animesh
>
> BR,
> Jani.
>
>
> >
> > Regards,
> > Animesh
> >
> >>
> >>
> >> BR,
> >> Jani.
> >>
> >> > +}
> >> > +
> >> > void intel_dsc_get_config(struct intel_crtc_state *crtc_state) {
> >> > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; diff
> >> > --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> > b/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> > index 65d301c23580..fe4d45561253 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> >> > @@ -12,11 +12,13 @@ struct intel_encoder; struct intel_crtc_state;
> >> >
> >> > bool intel_dsc_source_support(const struct intel_crtc_state
> >> > *crtc_state);
> >> > +void intel_uncompressed_joiner_enable(const struct
> >> > +intel_crtc_state *crtc_state);
> >> > void intel_dsc_enable(struct intel_encoder *encoder,
> >> > const struct intel_crtc_state *crtc_state); void
> >> > intel_dsc_disable(const struct intel_crtc_state *crtc_state); int
> >> > intel_dsc_compute_params(struct intel_encoder *encoder,
> >> > struct intel_crtc_state *pipe_config);
> >> > +void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> >> > +*crtc_state);
> >> > void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
> >> > enum intel_display_power_domain intel_dsc_power_domain(const
> >> > struct intel_crtc_state *crtc_state); diff --git
> >> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 31bc413dbba1..dd6e0bae9573 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -11493,6 +11493,8 @@ enum skl_power_gate {
> >> > #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> >> > #define SPLITTER_CONFIGURATION_2_SEGMENT
> >> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> >> > #define SPLITTER_CONFIGURATION_4_SEGMENT
> >> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> >> > +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
> >> > +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
> >> >
> >> > #define _ICL_PIPE_DSS_CTL2_PB 0x78204
> >> > #define _ICL_PIPE_DSS_CTL2_PC 0x78404
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Intel-gfx] [CI 16/19] drm/i915/adl_p: Add IPs stepping mapping
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (14 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 17/19] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
` (6 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
This will allow us to better implement workarounds.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
drivers/gpu/drm/i915/intel_step.c | 12 +++++++++++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 61308ce19059..39b5e019c1a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1551,6 +1551,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ALDERLAKE_S(__i915) && \
IS_GT_STEP(__i915, since, until))
+#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+ (IS_ALDERLAKE_P(__i915) && \
+ IS_DISPLAY_STEP(__i915, since, until))
+
+#define IS_ADLP_GT_STEP(__i915, since, until) \
+ (IS_ALDERLAKE_P(__i915) && \
+ IS_GT_STEP(__i915, since, until))
+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 4d71547a5b83..ba9479a67521 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -47,6 +47,13 @@ static const struct intel_step_info adls_revid_step_tbl[] = {
[0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0 },
};
+static const struct intel_step_info adlp_revid_step_tbl[] = {
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+ [0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
+ [0xC] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
+};
+
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -54,7 +61,10 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
- if (IS_ALDERLAKE_S(i915)) {
+ if (IS_ALDERLAKE_P(i915)) {
+ revids = adlp_revid_step_tbl;
+ size = ARRAY_SIZE(adlp_revid_step_tbl);
+ } else if (IS_ALDERLAKE_S(i915)) {
revids = adls_revid_step_tbl;
size = ARRAY_SIZE(adls_revid_step_tbl);
} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 17/19] drm/i915/adl_p: Implement Wa_22011091694
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (15 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 16/19] drm/i915/adl_p: Add IPs stepping mapping Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 18/19] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
` (5 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Adding a new hook to ADL-P just to avoid another platform check in
gen12lp_init_clock_gating() but also open to it.
BSpec: 54369
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dd6e0bae9573..089b5a59bed3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4176,6 +4176,9 @@ enum {
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
+#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
+#define DPCE_GATING_DIS REG_BIT(17)
+
#define _CLKGATE_DIS_PSL_A 0x46520
#define _CLKGATE_DIS_PSL_B 0x46524
#define _CLKGATE_DIS_PSL_C 0x46528
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 86a78cbb60fc..15d9a64e7b4c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7141,6 +7141,14 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
CLKREQ_POLICY_MEM_UP_OVRD, 0);
}
+static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ gen12lp_init_clock_gating(dev_priv);
+
+ /* Wa_22011091694:adlp */
+ intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
+}
+
static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
{
gen12lp_init_clock_gating(dev_priv);
@@ -7618,7 +7626,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_DG1(dev_priv))
+ if (IS_ALDERLAKE_P(dev_priv))
+ dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ else if (IS_DG1(dev_priv))
dev_priv->display.init_clock_gating = dg1_init_clock_gating;
else if (IS_GEN(dev_priv, 12))
dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 18/19] drm/i915/display/adl_p: Implement Wa_22011320316
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (16 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 17/19] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 19/19] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057) Matt Roper
` (4 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c9f1484f3811..4656a6edc3be 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1253,6 +1253,21 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
@@ -2801,7 +2816,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = adlp_cdclk_table;
+ /* Wa_22011320316:adlp[a0] */
+ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+ dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+ else
+ dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] [CI 19/19] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057)
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (17 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 18/19] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
@ 2021-05-14 15:37 ` Matt Roper
2021-05-14 16:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Another batch of reviewed XeLPD / ADL-P patches Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2021-05-14 15:37 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Buffer compression is not usable in A stepping.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton A Taylor <clinton.a.taylor@intel.com>
Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 20 ++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 8444744f4437..59e032f3687a 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -199,6 +199,13 @@ static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
+static const u64 adlp_step_a_plane_format_modifiers[] = {
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
@@ -1879,6 +1886,10 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
return false;
+ /* Wa_22011186057 */
+ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+ return false;
+
return plane_id < PLANE_SPRITE4;
}
@@ -1896,8 +1907,12 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ break;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ /* Wa_22011186057 */
+ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+ return false;
break;
default:
return false;
@@ -1952,7 +1967,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
+ /* Wa_22011186057 */
+ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+ return adlp_step_a_plane_format_modifiers;
+ else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
return gen12_plane_format_modifiers_mc_ccs;
else
return gen12_plane_format_modifiers_rc_ccs;
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Another batch of reviewed XeLPD / ADL-P patches
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (18 preceding siblings ...)
2021-05-14 15:37 ` [Intel-gfx] [CI 19/19] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057) Matt Roper
@ 2021-05-14 16:38 ` Patchwork
2021-05-14 16:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2021-05-14 16:38 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Another batch of reviewed XeLPD / ADL-P patches
URL : https://patchwork.freedesktop.org/series/90169/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dc16ea52587b drm/i915/xelpd: Handle new location of outputs D and E
314d49aa2d02 drm/i915/xelpd: Increase maximum watermark lines to 255
bcc1af51c6e6 drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
1d494651f544 drm/i915/xelpd: Support DP1.4 compression BPPs
-:41: CHECK:LINE_SPACING: Please don't use multiple blank lines
#41: FILE: drivers/gpu/drm/i915/display/intel_dp.c:524:
+
total: 0 errors, 0 warnings, 1 checks, 75 lines checked
376ad1f5149e drm/i915: Get slice height before computing rc params
964d5a8d3a60 drm/i915/xelpd: Provide port/phy mapping for vbt
7286424486be drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
406c1002291e drm/i915/adl_p: Add cdclk support for ADL-P
d07a1c416e0f drm/i915/display/tc: Rename safe_mode functions ownership
0d2dc8550001 drm/i915/adl_p: Enable modular fia
afe8c4d0449e drm/i915: Move intel_modeset_all_pipes()
bb2924fe8a7d drm/i915/adl_p: Enable/disable loadgen sharing
-:27: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#27: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1464:
+ if ((intel_crtc_has_dp_encoder(crtc_state) &&
+ crtc_state->port_clock == 162000) ||
total: 0 errors, 0 warnings, 1 checks, 21 lines checked
f5c0cc6e05ae drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
801654db5b66 drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
c0ab3dda42fe drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
05f26cdcc673 drm/i915/adl_p: Add IPs stepping mapping
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/i915_drv.h:1554:
+#define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
+ (IS_ALDERLAKE_P(__i915) && \
+ IS_DISPLAY_STEP(__i915, since, until))
-:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#29: FILE: drivers/gpu/drm/i915/i915_drv.h:1558:
+#define IS_ADLP_GT_STEP(__i915, since, until) \
+ (IS_ALDERLAKE_P(__i915) && \
+ IS_GT_STEP(__i915, since, until))
total: 0 errors, 0 warnings, 2 checks, 38 lines checked
1929a3b973d9 drm/i915/adl_p: Implement Wa_22011091694
909eca03ec38 drm/i915/display/adl_p: Implement Wa_22011320316
d66be9f4eff1 drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Another batch of reviewed XeLPD / ADL-P patches
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (19 preceding siblings ...)
2021-05-14 16:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Another batch of reviewed XeLPD / ADL-P patches Patchwork
@ 2021-05-14 16:40 ` Patchwork
2021-05-14 17:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-15 2:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
22 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2021-05-14 16:40 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Another batch of reviewed XeLPD / ADL-P patches
URL : https://patchwork.freedesktop.org/series/90169/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Another batch of reviewed XeLPD / ADL-P patches
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (20 preceding siblings ...)
2021-05-14 16:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-05-14 17:09 ` Patchwork
2021-05-15 2:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
22 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2021-05-14 17:09 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 13535 bytes --]
== Series Details ==
Series: Another batch of reviewed XeLPD / ADL-P patches
URL : https://patchwork.freedesktop.org/series/90169/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10083 -> Patchwork_20127
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_20127 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20127, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20127:
### IGT changes ###
#### Warnings ####
* igt@runner@aborted:
- fi-bdw-5557u: [FAIL][1] ([i915#1602] / [i915#2029]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bdw-5557u/igt@runner@aborted.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bdw-5557u/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-1115g4}: [FAIL][3] ([i915#1436] / [i915#2966]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-tgl-1115g4/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-tgl-1115g4/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_20127 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][5] ([i915#2283])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fence@basic-await@rcs0:
- fi-bsw-nick: [PASS][6] -> [FAIL][7] ([i915#3457])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-nick/igt@gem_exec_fence@basic-await@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-nick/igt@gem_exec_fence@basic-await@rcs0.html
* igt@gem_exec_fence@nb-await@rcs0:
- fi-glk-dsi: [PASS][8] -> [FAIL][9] ([i915#3457]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-glk-dsi/igt@gem_exec_fence@nb-await@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-glk-dsi/igt@gem_exec_fence@nb-await@rcs0.html
- fi-bsw-kefka: [PASS][10] -> [FAIL][11] ([i915#3457])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@gem_exec_fence@nb-await@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-kefka/igt@gem_exec_fence@nb-await@rcs0.html
* igt@gem_exec_fence@nb-await@vecs0:
- fi-bsw-n3050: [PASS][12] -> [FAIL][13] ([i915#3457]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html
* igt@i915_selftest@live@execlists:
- fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][14] ([i915#3462])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bdw-5557u/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@mman:
- fi-bdw-5557u: NOTRUN -> [DMESG-WARN][15] ([i915#3457]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bdw-5557u/igt@i915_selftest@live@mman.html
* igt@kms_busy@basic@flip:
- fi-ilk-650: [PASS][16] -> [INCOMPLETE][17] ([i915#3457])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-ilk-650/igt@kms_busy@basic@flip.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-ilk-650/igt@kms_busy@basic@flip.html
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-u2: [PASS][18] -> [FAIL][19] ([i915#2416])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-tgl-u2/igt@kms_frontbuffer_tracking@basic.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-tgl-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-elk-e7500: [PASS][20] -> [FAIL][21] ([i915#53]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-elk-e7500/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-elk-e7500/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
- fi-bwr-2160: [PASS][22] -> [FAIL][23] ([i915#53])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bwr-2160/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bwr-2160/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_psr@cursor_plane_move:
- fi-bdw-5557u: NOTRUN -> [SKIP][24] ([fdo#109271]) +5 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html
#### Possible fixes ####
* igt@gem_busy@busy@all:
- fi-elk-e7500: [FAIL][25] ([i915#3457]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-elk-e7500/igt@gem_busy@busy@all.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-elk-e7500/igt@gem_busy@busy@all.html
* igt@gem_exec_fence@basic-await@bcs0:
- fi-bsw-n3050: [FAIL][27] ([i915#3457]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html
* igt@gem_exec_fence@basic-await@vecs0:
- fi-bsw-kefka: [FAIL][29] ([i915#3457]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vecs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vecs0.html
* igt@gem_exec_fence@nb-await@vecs0:
- fi-bsw-nick: [FAIL][31] ([i915#3457]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-nick/igt@gem_exec_fence@nb-await@vecs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-nick/igt@gem_exec_fence@nb-await@vecs0.html
* igt@gem_wait@busy@all:
- fi-bsw-kefka: [FAIL][33] ([i915#3177] / [i915#3457]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@gem_wait@busy@all.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-kefka/igt@gem_wait@busy@all.html
* igt@gem_wait@wait@all:
- fi-bwr-2160: [FAIL][35] ([i915#3457]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bwr-2160/igt@gem_wait@wait@all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bwr-2160/igt@gem_wait@wait@all.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- fi-tgl-u2: [FAIL][37] -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-tgl-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-tgl-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-elk-e7500: [FAIL][39] ([i915#53]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-bsw-kefka: [FAIL][41] ([i915#53]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-tgl-u2: [DMESG-FAIL][43] ([i915#3462]) -> [INCOMPLETE][44] ([i915#3462])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-tgl-u2/igt@i915_selftest@live@execlists.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-tgl-u2/igt@i915_selftest@live@execlists.html
- fi-cml-s: [INCOMPLETE][45] ([i915#3462]) -> [DMESG-FAIL][46] ([i915#3462])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-cml-s/igt@i915_selftest@live@execlists.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-cml-s/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-kbl-x1275: [FAIL][47] ([i915#1436] / [i915#3363]) -> [FAIL][48] ([i915#1436] / [i915#2426] / [i915#3363])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-kbl-x1275/igt@runner@aborted.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-kbl-x1275/igt@runner@aborted.html
- fi-kbl-guc: [FAIL][49] ([i915#1436] / [i915#3363]) -> [FAIL][50] ([i915#1436] / [i915#2426] / [i915#3363])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-kbl-guc/igt@runner@aborted.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-kbl-guc/igt@runner@aborted.html
- fi-cml-u2: [FAIL][51] ([i915#2082] / [i915#2426] / [i915#3363]) -> [FAIL][52] ([i915#3363])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-cml-u2/igt@runner@aborted.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-cml-u2/igt@runner@aborted.html
- fi-kbl-7567u: [FAIL][53] ([i915#1436] / [i915#3363]) -> [FAIL][54] ([i915#1436] / [i915#2426] / [i915#3363])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-kbl-7567u/igt@runner@aborted.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/fi-kbl-7567u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2416]: https://gitlab.freedesktop.org/drm/intel/issues/2416
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
Participating hosts (40 -> 37)
------------------------------
Missing (3): fi-rkl-11500t fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10083 -> Patchwork_20127
CI-20190529: 20190529
CI_DRM_10083: 63c1a45e11736b26f82b6d6ad107c3ddd4b5c1c2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6084: 5c5734d8ee1afac871b69c4554ff14e9b56100e4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20127: d66be9f4eff18b48b7022abc712c6b0a1562dda6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d66be9f4eff1 drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057)
909eca03ec38 drm/i915/display/adl_p: Implement Wa_22011320316
1929a3b973d9 drm/i915/adl_p: Implement Wa_22011091694
05f26cdcc673 drm/i915/adl_p: Add IPs stepping mapping
c0ab3dda42fe drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
801654db5b66 drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
f5c0cc6e05ae drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
bb2924fe8a7d drm/i915/adl_p: Enable/disable loadgen sharing
afe8c4d0449e drm/i915: Move intel_modeset_all_pipes()
0d2dc8550001 drm/i915/adl_p: Enable modular fia
d07a1c416e0f drm/i915/display/tc: Rename safe_mode functions ownership
406c1002291e drm/i915/adl_p: Add cdclk support for ADL-P
7286424486be drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
964d5a8d3a60 drm/i915/xelpd: Provide port/phy mapping for vbt
376ad1f5149e drm/i915: Get slice height before computing rc params
1d494651f544 drm/i915/xelpd: Support DP1.4 compression BPPs
bcc1af51c6e6 drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
314d49aa2d02 drm/i915/xelpd: Increase maximum watermark lines to 255
dc16ea52587b drm/i915/xelpd: Handle new location of outputs D and E
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/index.html
[-- Attachment #1.2: Type: text/html, Size: 17200 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Another batch of reviewed XeLPD / ADL-P patches
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
` (21 preceding siblings ...)
2021-05-14 17:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-05-15 2:24 ` Patchwork
2021-05-15 3:00 ` Matt Roper
22 siblings, 1 reply; 33+ messages in thread
From: Patchwork @ 2021-05-15 2:24 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30270 bytes --]
== Series Details ==
Series: Another batch of reviewed XeLPD / ADL-P patches
URL : https://patchwork.freedesktop.org/series/90169/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10083_full -> Patchwork_20127_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20127_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20127_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20127_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-glk: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk7/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@kms_flip_tiling@flip-changes-tiling@dp-1-pipe-a:
- shard-apl: [PASS][2] -> [FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-apl7/igt@kms_flip_tiling@flip-changes-tiling@dp-1-pipe-a.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl1/igt@kms_flip_tiling@flip-changes-tiling@dp-1-pipe-a.html
* igt@kms_flip_tiling@flip-changes-tiling@hdmi-a-2-pipe-c:
- shard-glk: [PASS][4] -> [FAIL][5] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk8/igt@kms_flip_tiling@flip-changes-tiling@hdmi-a-2-pipe-c.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk7/igt@kms_flip_tiling@flip-changes-tiling@hdmi-a-2-pipe-c.html
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-snb: NOTRUN -> [FAIL][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
#### Warnings ####
* igt@gem_exec_fair@basic-none@bcs0:
- shard-glk: [SKIP][7] ([fdo#109271] / [i915#3457]) -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk9/igt@gem_exec_fair@basic-none@bcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk6/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-glk: [INCOMPLETE][9] ([i915#3468]) -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk4/igt@gem_mmap_gtt@fault-concurrent-x.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk5/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@kms_plane_cursor@pipe-b-primary-size-64:
- shard-snb: [FAIL][11] ([i915#3457]) -> [FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-snb5/igt@kms_plane_cursor@pipe-b-primary-size-64.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb6/igt@kms_plane_cursor@pipe-b-primary-size-64.html
* igt@kms_plane_cursor@pipe-c-viewport-size-64:
- shard-tglb: [FAIL][13] ([i915#3457]) -> [FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-tglb8/igt@kms_plane_cursor@pipe-c-viewport-size-64.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-tglb5/igt@kms_plane_cursor@pipe-c-viewport-size-64.html
Known issues
------------
Here are the changes found in Patchwork_20127_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-noreloc-purge-cache:
- shard-skl: NOTRUN -> [DMESG-WARN][15] ([i915#3457]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl1/igt@api_intel_bb@blit-noreloc-purge-cache.html
* igt@gem_create@create-clear:
- shard-skl: [PASS][16] -> [FAIL][17] ([i915#3160])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-skl4/igt@gem_create@create-clear.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl7/igt@gem_create@create-clear.html
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][18] ([i915#3002])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb7/igt@gem_create@create-massive.html
- shard-kbl: NOTRUN -> [DMESG-WARN][19] ([i915#3002])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl2/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@engines-persistence@bcs0:
- shard-apl: NOTRUN -> [FAIL][20] ([i915#3457]) +13 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl6/igt@gem_ctx_persistence@engines-persistence@bcs0.html
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#1099]) +5 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb7/igt@gem_ctx_persistence@idempotent.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][22] -> [FAIL][23] ([i915#2842] / [i915#3457])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
- shard-glk: [PASS][24] -> [SKIP][25] ([fdo#109271] / [i915#3457])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk3/igt@gem_exec_fair@basic-flow@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk9/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][26] -> [FAIL][27] ([i915#2842] / [i915#3457])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][28] ([i915#2842] / [i915#3457])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][29] ([i915#2842] / [i915#3457])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-kbl: NOTRUN -> [FAIL][30] ([i915#2842] / [i915#3457])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][31] -> [SKIP][32] ([fdo#109271] / [i915#3457])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fence@syncobj-export:
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#3457]) +23 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk4/igt@gem_exec_fence@syncobj-export.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk6/igt@gem_exec_fence@syncobj-export.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271]) +453 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][36] ([i915#2389] / [i915#3457]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb2/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][37] ([i915#2389] / [i915#3457])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#180]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-iclb: [PASS][40] -> [INCOMPLETE][41] ([i915#2910] / [i915#3468])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb3/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb6/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-iclb: [PASS][42] -> [INCOMPLETE][43] ([i915#3468])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb8/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb4/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb: NOTRUN -> [INCOMPLETE][44] ([i915#3468]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb2/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_mmap_offset@clear:
- shard-glk: [PASS][45] -> [FAIL][46] ([i915#1888] / [i915#3160])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk7/igt@gem_mmap_offset@clear.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk9/igt@gem_mmap_offset@clear.html
* igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
- shard-apl: NOTRUN -> [INCOMPLETE][47] ([i915#3468]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl1/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html
- shard-glk: NOTRUN -> [INCOMPLETE][48] ([i915#3468]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-skl: NOTRUN -> [INCOMPLETE][49] ([i915#3468]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl1/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
- shard-kbl: NOTRUN -> [INCOMPLETE][50] ([i915#3468]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
* igt@gem_spin_batch@engines@vcs0:
- shard-apl: NOTRUN -> [FAIL][51] ([i915#2898] / [i915#3457]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl6/igt@gem_spin_batch@engines@vcs0.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#3323])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
- shard-glk: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3323])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@set-cache-level:
- shard-apl: NOTRUN -> [FAIL][54] ([i915#3324])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@gem_userptr_blits@set-cache-level.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][55] ([i915#2724] / [i915#3457])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb2/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][56] -> [DMESG-WARN][57] ([i915#180] / [i915#3457])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_hangman@error-state-capture@bcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][58] ([i915#3457]) +8 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@i915_hangman@error-state-capture@bcs0.html
* igt@i915_hangman@error-state-capture@rcs0:
- shard-glk: NOTRUN -> [DMESG-WARN][59] ([i915#3457]) +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk7/igt@i915_hangman@error-state-capture@rcs0.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][60] ([i915#454])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl1/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rps@waitboost:
- shard-snb: NOTRUN -> [DMESG-WARN][61] ([i915#3457]) +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb7/igt@i915_pm_rps@waitboost.html
* igt@i915_pm_sseu@full-enable:
- shard-apl: NOTRUN -> [DMESG-WARN][62] ([i915#3457]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@i915_pm_sseu@full-enable.html
* igt@kms_big_joiner@basic:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2705]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl6/igt@kms_big_joiner@basic.html
- shard-glk: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2705])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@kms_big_joiner@basic.html
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2705])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl1/igt@kms_big_joiner@basic.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [fdo#111827]) +5 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl1/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][67] ([fdo#109271] / [fdo#111827]) +25 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +17 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [fdo#111827]) +10 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-glk: NOTRUN -> [SKIP][70] ([fdo#109271] / [fdo#111827]) +10 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][71] ([i915#1319]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl6/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][72] ([i915#2105])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
- shard-kbl: [PASS][73] -> [FAIL][74] ([i915#3444] / [i915#3457]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-apl: [PASS][75] -> [FAIL][76] ([i915#3444] / [i915#3457])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3457]) +22 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
- shard-glk: [PASS][78] -> [FAIL][79] ([i915#3444] / [i915#3457])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk5/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
* igt@kms_cursor_crc@pipe-a-cursor-dpms:
- shard-glk: NOTRUN -> [FAIL][80] ([i915#3444] / [i915#3457]) +6 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
- shard-snb: NOTRUN -> [FAIL][81] ([i915#3457]) +9 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb7/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: NOTRUN -> [FAIL][82] ([i915#3444] / [i915#3457]) +5 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen:
- shard-skl: [PASS][83] -> [FAIL][84] ([i915#3444] / [i915#3457]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
- shard-iclb: [PASS][85] -> [FAIL][86] ([i915#3457])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-random:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3457]) +10 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-max-size-random.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding:
- shard-kbl: NOTRUN -> [FAIL][88] ([i915#3444] / [i915#3457]) +11 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-dpms:
- shard-apl: NOTRUN -> [FAIL][89] ([i915#3444] / [i915#3457])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-dpms.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-random:
- shard-glk: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#3457]) +11 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk7/igt@kms_cursor_crc@pipe-d-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding:
- shard-snb: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#3457]) +67 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb7/igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-offscreen:
- shard-tglb: [PASS][92] -> [FAIL][93] ([i915#2124] / [i915#3457]) +3 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-64x64-offscreen.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-64x64-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#3457]) +19 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge:
- shard-apl: [PASS][95] -> [FAIL][96] ([i915#70])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-apl7/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl1/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: NOTRUN -> [INCOMPLETE][97] ([i915#155] / [i915#180] / [i915#636])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1:
- shard-glk: [PASS][98] -> [FAIL][99] ([i915#2122])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2642])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271]) +112 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][102] ([fdo#109271]) +60 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#533])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-a:
- shard-glk: [PASS][104] -> [FAIL][105] ([i915#2472])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk5/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-a.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][107] ([i915#265])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][108] ([fdo#108145] / [i915#265]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_cursor@pipe-a-overlay-size-256:
- shard-iclb: [PASS][109] -> [FAIL][110] ([i915#2657])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb2/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb3/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
* igt@kms_plane_cursor@pipe-a-primary-size-128:
- shard-snb: NOTRUN -> [FAIL][111] ([i915#3461]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb7/igt@kms_plane_cursor@pipe-a-primary-size-128.html
* igt@kms_plane_cursor@pipe-a-primary-size-64:
- shard-snb: NOTRUN -> [FAIL][112] ([i915#3457] / [i915#3461])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-snb7/igt@kms_plane_cursor@pipe-a-primary-size-64.html
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-glk: [PASS][113] -> [FAIL][114] ([i915#2657]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk3/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk8/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
- shard-kbl: NOTRUN -> [FAIL][115] ([i915#2657]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
* igt@kms_plane_cursor@pipe-b-primary-size-64:
- shard-skl: NOTRUN -> [FAIL][116] ([i915#2657] / [i915#3457]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl9/igt@kms_plane_cursor@pipe-b-primary-size-64.html
* igt@kms_plane_cursor@pipe-c-overlay-size-64:
- shard-iclb: [PASS][117] -> [FAIL][118] ([i915#2657] / [i915#3457]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb2/igt@kms_plane_cursor@pipe-c-overlay-size-64.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb5/igt@kms_plane_cursor@pipe-c-overlay-size-64.html
* igt@kms_plane_cursor@pipe-c-viewport-size-256:
- shard-iclb: [PASS][119] -> [FAIL][120] ([i915#2657] / [i915#3461])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb2/igt@kms_plane_cursor@pipe-c-viewport-size-256.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb3/igt@kms_plane_cursor@pipe-c-viewport-size-256.html
* igt@kms_plane_cursor@pipe-c-viewport-size-64:
- shard-glk: [PASS][121] -> [FAIL][122] ([i915#2657] / [i915#3457]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk4/igt@kms_plane_cursor@pipe-c-viewport-size-64.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk5/igt@kms_plane_cursor@pipe-c-viewport-size-64.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: [PASS][123] -> [FAIL][124] ([i915#1779])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk6/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk7/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-kbl: NOTRUN -> [SKIP][125] ([fdo#109271] / [i915#2733])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#658]) +4 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#658]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#658]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-kbl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-skl: NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#658]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-skl1/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][130] -> [SKIP][131] ([fdo#109441]) +3 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb2/igt@kms_psr@psr2_basic.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-iclb3/igt@kms_psr@psr2_basic.html
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- shard-glk: NOTRUN -> [FAIL][132] ([i915#3457]) +9 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-glk3/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][133] ([fdo#109271]) +158 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/shard-apl7/igt@kms_vblank@pipe-d-ts-continuation-idl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20127/index.html
[-- Attachment #1.2: Type: text/html, Size: 33595 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread