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From: Samuel Holland <samuel@sholland.org>
To: Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Ondrej Jirman <megous@megous.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
	Samuel Holland <samuel@sholland.org>,
	stable@vger.kernel.org,
	Roman Stratiienko <r.stratiienko@gmail.com>
Subject: [PATCH] clocksource/arm_arch_timer: Improve Allwinner A64 timer workaround
Date: Fri, 14 May 2021 21:14:39 -0500	[thread overview]
Message-ID: <20210515021439.55316-1-samuel@sholland.org> (raw)

Bad counter reads are experienced sometimes when bit 10 or greater rolls
over. Originally, testing showed that at least 10 lower bits would be
set to the same value during these bad reads. However, some users still
reported time skips.

Wider testing revealed that on some chips, occasionally only the lowest
9 bits would read as the anomalous value. During these reads (which
still happen only when bit 10), bit 9 would read as the correct value.

Reduce the mask by one bit to cover these cases as well.

Cc: stable@vger.kernel.org
Fixes: c950ca8c35ee ("clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

The tool used for testing is here:
 https://github.com/smaeul/timer-tools

For examples of the 9-bit pattern, see the data here:
 https://github.com/8bitgc/timer-tools/tree/master/output

I was able to reproduce the same pattern (although _extremely_ rarely)
on 1 of the 8 A64 boards I currently have access to.

This explanation is consistent with the earlier report here:
 https://lore.kernel.org/lkml/20200929111347.1967438-1-r.stratiienko@gmail.com/

In that report, the time went backward 20542 ns == 493 cycles @ 24 MHz,
which matches the expected 2^9 == 512 cycles minus system call overhead.

 drivers/clocksource/arm_arch_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index d0177824c518..f4881764bf8f 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -352,7 +352,7 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
 	do {								\
 		_val = read_sysreg(reg);				\
 		_retries--;						\
-	} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries);	\
+	} while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries);	\
 									\
 	WARN_ON_ONCE(!_retries);					\
 	_val;								\
-- 
2.26.3


WARNING: multiple messages have this Message-ID
From: Samuel Holland <samuel@sholland.org>
To: Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Ondrej Jirman <megous@megous.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
	Samuel Holland <samuel@sholland.org>,
	stable@vger.kernel.org,
	Roman Stratiienko <r.stratiienko@gmail.com>
Subject: [PATCH] clocksource/arm_arch_timer: Improve Allwinner A64 timer workaround
Date: Fri, 14 May 2021 21:14:39 -0500	[thread overview]
Message-ID: <20210515021439.55316-1-samuel@sholland.org> (raw)

Bad counter reads are experienced sometimes when bit 10 or greater rolls
over. Originally, testing showed that at least 10 lower bits would be
set to the same value during these bad reads. However, some users still
reported time skips.

Wider testing revealed that on some chips, occasionally only the lowest
9 bits would read as the anomalous value. During these reads (which
still happen only when bit 10), bit 9 would read as the correct value.

Reduce the mask by one bit to cover these cases as well.

Cc: stable@vger.kernel.org
Fixes: c950ca8c35ee ("clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

The tool used for testing is here:
 https://github.com/smaeul/timer-tools

For examples of the 9-bit pattern, see the data here:
 https://github.com/8bitgc/timer-tools/tree/master/output

I was able to reproduce the same pattern (although _extremely_ rarely)
on 1 of the 8 A64 boards I currently have access to.

This explanation is consistent with the earlier report here:
 https://lore.kernel.org/lkml/20200929111347.1967438-1-r.stratiienko@gmail.com/

In that report, the time went backward 20542 ns == 493 cycles @ 24 MHz,
which matches the expected 2^9 == 512 cycles minus system call overhead.

 drivers/clocksource/arm_arch_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index d0177824c518..f4881764bf8f 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -352,7 +352,7 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
 	do {								\
 		_val = read_sysreg(reg);				\
 		_retries--;						\
-	} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries);	\
+	} while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries);	\
 									\
 	WARN_ON_ONCE(!_retries);					\
 	_val;								\
-- 
2.26.3


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             reply	other threads:[~2021-05-15  2:14 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-15  2:14 Samuel Holland [this message]
2021-05-15  2:14 ` Samuel Holland
2021-06-18 16:03 ` [tip: timers/core] " tip-bot2 for Samuel Holland

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