From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support
Date: Fri, 14 May 2021 20:10:12 -0700 [thread overview]
Message-ID: <20210515031035.2561658-1-matthew.d.roper@intel.com> (raw)
Many of the ALD-P patches have received review and landed on drm-tip
now. Let's rebase and resend the remaining patches that still need
review (or have prereq patches that need review).
Previous version of the series was
https://patchwork.freedesktop.org/series/89899/#rev2
Aside from general rebasing, this version also updates the DP
translation tables in since the bspec was just updated with new values.
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Anusha Srivatsa (4):
drm/i915/adl_p: Setup ports/phys
drm/i915/adl_p: Add PLL Support
drm/i915/adlp: Add PIPE_MISC2 programming
drm/i915/adl_p: Update memory bandwidth parameters
Gwan-gyeong Mun (4):
drm/i915/display: Replace dc3co_enabled with dc3co_exitline on
intel_psr struct
drm/i915/display: Remove a redundant function argument from
intel_psr_enable_source()
drm/i915/display: Add PSR interrupt error check function
drm/i915/display: Introduce new intel_psr_pause/resume function
Imre Deak (1):
drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL
José Roberto de Souza (3):
drm/i915/adl_p: Handle TC cold
drm/i915/adl_p: Implement TC sequences
drm/i915/adl_p: Don't config MBUS and DBUF during display
initialization
Manasi Navare (1):
drm/i915/xelpd: Add VRR guardband for VRR CTL
Matt Roper (2):
drm/i915/xelpd: Enhanced pipe underrun reporting
drm/i915/adl_p: Add dedicated SAGV watermarks
Mika Kahola (2):
drm/i915/adl_p: Tx escape clock with DSI
drm/i915/adl_p: Define and use ADL-P specific DP translation tables
Vandita Kulkarni (5):
drm/i915/xelpd: Support DP1.4 compression BPPs
drm/i915/xelpd: Calculate VDSC RC parameters
drm/i915/xelpd: Add rc_qp_table for rcparams calculation
drm/i915/adl_p: Add ddb allocation support
drm/i915/adl_p: MBUS programming
Ville Syrjälä (1):
drm/i915: Introduce MBUS relative dbuf offsets
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/icl_dsi.c | 21 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 20 ++
drivers/gpu/drm/i915/display/intel_atomic.h | 1 +
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++-
.../drm/i915/display/intel_ddi_buf_trans.c | 53 +++
.../drm/i915/display/intel_ddi_buf_trans.h | 4 +
drivers/gpu/drm/i915/display/intel_display.c | 77 ++++-
.../drm/i915/display/intel_display_power.c | 9 +-
.../drm/i915/display/intel_display_types.h | 5 +-
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 +++-
.../drm/i915/display/intel_fifo_underrun.c | 57 +++-
drivers/gpu/drm/i915/display/intel_psr.c | 131 ++++++--
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
.../gpu/drm/i915/display/intel_qp_tables.c | 311 ++++++++++++++++++
.../gpu/drm/i915/display/intel_qp_tables.h | 14 +
drivers/gpu/drm/i915/display/intel_tc.c | 134 +++++++-
drivers/gpu/drm/i915/display/intel_vdsc.c | 105 +++++-
drivers/gpu/drm/i915/display/intel_vrr.c | 58 +++-
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_irq.c | 19 +-
drivers/gpu/drm/i915/i915_irq.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 135 ++++++--
drivers/gpu/drm/i915/intel_pm.c | 303 ++++++++++++++++-
drivers/gpu/drm/i915/intel_pm.h | 2 +-
27 files changed, 1440 insertions(+), 143 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.c
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
--
2.25.4
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next reply other threads:[~2021-05-15 3:10 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-15 3:10 Matt Roper [this message]
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-05-17 6:52 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-17 15:18 ` Jani Nikula
2021-05-18 6:33 ` Kulkarni, Vandita
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-05-18 18:06 ` Navare, Manasi
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-05-24 13:40 ` Aditya Swarup
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-05-17 6:49 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-05-17 18:01 ` Imre Deak
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold Matt Roper
2021-05-17 14:53 ` Imre Deak
2021-05-17 23:15 ` Souza, Jose
2021-05-17 23:22 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-05-17 15:12 ` Imre Deak
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-05-18 11:58 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-05-18 12:22 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-05-17 6:38 ` Lisovskiy, Stanislav
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming Matt Roper
2023-07-17 10:32 ` Tvrtko Ursulin
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-05-17 7:36 ` Kulkarni, Vandita
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
2021-05-17 6:39 ` Gupta, Anshuman
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
2021-05-19 6:49 ` Anshuman Gupta
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function Matt Roper
2021-05-17 17:03 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
2021-05-17 16:58 ` Souza, Jose
2021-05-18 9:33 ` Mun, Gwan-gyeong
2021-05-18 11:06 ` Ville Syrjälä
2021-05-21 10:58 ` Mun, Gwan-gyeong
2021-05-21 21:52 ` Souza, Jose
2021-06-01 10:23 ` Mun, Gwan-gyeong
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-05-17 23:02 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support Matt Roper
2021-05-17 21:55 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
2021-05-17 17:01 ` Souza, Jose
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-05-17 21:46 ` Clint Taylor
2021-05-15 3:10 ` [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-05-17 17:02 ` Souza, Jose
2021-05-15 4:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3) Patchwork
2021-05-15 4:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15 5:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-17 23:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support (rev4) Patchwork
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