All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peng Ju Zhou <PengJu.Zhou@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Victor <Victor.Zhao@amd.com>
Subject: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
Date: Mon, 17 May 2021 22:39:09 +0800	[thread overview]
Message-ID: <20210517143910.2125-9-PengJu.Zhou@amd.com> (raw)
In-Reply-To: <20210517143910.2125-1-PengJu.Zhou@amd.com>

use psp to program IH_RB_CNTL* if indirect access
for ih enabled in SRIOV environment.

Signed-off-by: Victor <Victor.Zhao@amd.com>
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
 drivers/gpu/drm/amd/amdgpu/nv.c        |  2 +-
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..2e69cf8db072 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
 	/* enable_intr field is only valid in ring0 */
 	if (ih == &adev->irq.ih)
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
-	WREG32(ih_regs->ih_rb_cntl, tmp);
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+			return -ETIMEDOUT;
+		}
+	} else {
+		WREG32(ih_regs->ih_rb_cntl, tmp);
+	}
 
 	if (enable) {
 		ih->enabled = true;
@@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev,
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
 	}
-	WREG32(ih_regs->ih_rb_cntl, tmp);
+
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+			return -ETIMEDOUT;
+		}
+	} else {
+		WREG32(ih_regs->ih_rb_cntl, tmp);
+	}
 
 	if (ih == &adev->irq.ih) {
 		/* set the ih ring 0 writeback address whether it's enabled or not */
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a9ad28fb55b3..b9c9c4d4606c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 	case CHIP_NAVI12:
 		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
-		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2021-05-17 14:39 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 02/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* Peng Ju Zhou
2021-05-20  4:33   ` Felix Kuehling
2021-05-17 14:39 ` [PATCH v5 04/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 05/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5* Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 06/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 07/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* Peng Ju Zhou
2021-05-20  3:48   ` Alex Deucher
2021-05-17 14:39 ` Peng Ju Zhou [this message]
2021-05-20  3:46   ` [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Alex Deucher
2021-05-21  9:58     ` Zhou, Peng Ju
2021-05-21 10:07       ` Deng, Emily
2021-05-21 14:25         ` Alex Deucher
2021-05-23 11:41         ` Zhou, Peng Ju
2021-05-17 14:39 ` [PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV Peng Ju Zhou
2021-05-20  3:47   ` Alex Deucher
2021-05-17 14:49 ` [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Zhou, Peng Ju
2021-05-19 14:34   ` Zhou, Peng Ju
2021-05-25 15:18     ` Ming, Davis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210517143910.2125-9-PengJu.Zhou@amd.com \
    --to=pengju.zhou@amd.com \
    --cc=Victor.Zhao@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.