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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC
Date: Tue, 18 May 2021 22:42:02 -0700	[thread overview]
Message-ID: <20210519054202.r72oowbobewrzt5s@ldmartin-desk2> (raw)
In-Reply-To: <20210518213444.11420-3-anusha.srivatsa@intel.com>

On Tue, May 18, 2021 at 02:34:41PM -0700, Anusha Srivatsa wrote:
>No functional change.
>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_csr.c             | 12 ++++++------
> drivers/gpu/drm/i915/display/intel_display_debugfs.c |  2 +-
> drivers/gpu/drm/i915/i915_drv.h                      |  2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c                |  2 +-
> drivers/gpu/drm/i915/i915_pci.c                      |  4 ++--
> drivers/gpu/drm/i915/intel_device_info.c             |  2 +-
> drivers/gpu/drm/i915/intel_device_info.h             |  2 +-
> 7 files changed, 13 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
>index a22339ebdffd..5ed286dc6720 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.c
>+++ b/drivers/gpu/drm/i915/display/intel_csr.c
>@@ -315,9 +315,9 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
> 	u32 *payload = dev_priv->dmc.dmc_payload;
> 	u32 i, fw_size;
>
>-	if (!HAS_CSR(dev_priv)) {
>+	if (!HAS_DMC(dev_priv)) {
> 		drm_err(&dev_priv->drm,
>-			"No CSR support available for this platform\n");
>+			"No DMC support available for this platform\n");
> 		return;
> 	}
>
>@@ -686,7 +686,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>
> 	INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
>
>-	if (!HAS_CSR(dev_priv))
>+	if (!HAS_DMC(dev_priv))
> 		return;
>
> 	/*
>@@ -776,7 +776,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>  */
> void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
> {
>-	if (!HAS_CSR(dev_priv))
>+	if (!HAS_DMC(dev_priv))
> 		return;
>
> 	flush_work(&dev_priv->dmc.work);
>@@ -795,7 +795,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
>  */
> void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
> {
>-	if (!HAS_CSR(dev_priv))
>+	if (!HAS_DMC(dev_priv))
> 		return;
>
> 	/*
>@@ -815,7 +815,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
>  */
> void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
> {
>-	if (!HAS_CSR(dev_priv))
>+	if (!HAS_DMC(dev_priv))
> 		return;
>
> 	intel_csr_ucode_suspend(dev_priv);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index a875f3c9b358..6cd7f8c1724f 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -535,7 +535,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> 	struct intel_dmc *dmc;
> 	i915_reg_t dc5_reg, dc6_reg = {};
>
>-	if (!HAS_CSR(dev_priv))
>+	if (!HAS_DMC(dev_priv))
> 		return -ENODEV;
>
> 	dmc = &dev_priv->dmc;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 3c9f6bbb5dd7..469783003309 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1662,7 +1662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)
>
>-#define HAS_CSR(dev_priv)	(INTEL_INFO(dev_priv)->display.has_csr)
>+#define HAS_DMC(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dmc)
>
> #define HAS_MSO(i915)		(INTEL_GEN(i915) >= 12)
>
>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>index 03d1221de13b..06828ff90ccf 100644
>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>@@ -788,7 +788,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>
> 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>
>-	if (HAS_CSR(m->i915)) {
>+	if (HAS_DMC(m->i915)) {
> 		struct intel_dmc *dmc = &m->i915->dmc;
>
> 		err_printf(m, "DMC loaded: %s\n",
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index 574881c0e339..97c98f4fb265 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -643,7 +643,7 @@ static const struct intel_device_info chv_info = {
> 	GEN8_FEATURES, \
> 	GEN(9), \
> 	GEN9_DEFAULT_PAGE_SIZES, \
>-	.display.has_csr = 1, \
>+	.display.has_dmc = 1, \
> 	.has_gt_uc = 1, \
> 	.display.has_hdcp = 1, \
> 	.display.has_ipc = 1, \
>@@ -698,7 +698,7 @@ static const struct intel_device_info skl_gt4_info = {
> 	.display.has_psr = 1, \
> 	.display.has_psr_hw_tracking = 1, \
> 	.has_runtime_pm = 1, \
>-	.display.has_csr = 1, \
>+	.display.has_dmc = 1, \
> 	.has_rc6 = 1, \
> 	.has_rps = true, \
> 	.display.has_dp_mst = 1, \
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index 8cb58a238c68..e16599b67b83 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -353,7 +353,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> 			info->display.has_fbc = 0;
>
> 		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
>-			info->display.has_csr = 0;
>+			info->display.has_dmc = 0;
>
> 		if (INTEL_GEN(dev_priv) >= 10 &&
> 		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index e98b36959736..1390fad5ec06 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -141,7 +141,7 @@ enum intel_ppgtt_type {
> #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> 	/* Keep in alphabetical order */ \
> 	func(cursor_needs_physical); \
>-	func(has_csr); \
>+	func(has_dmc); \
> 	func(has_ddi); \
> 	func(has_dp_mst); \
> 	func(has_dsb); \
>-- 
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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  reply	other threads:[~2021-05-19  5:42 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
2021-05-18 21:34 ` [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc Anusha Srivatsa
2021-05-19  5:40   ` Lucas De Marchi
2021-05-18 21:34 ` [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC Anusha Srivatsa
2021-05-19  5:42   ` Lucas De Marchi [this message]
2021-05-18 21:34 ` [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr Anusha Srivatsa
2021-05-19  5:45   ` Lucas De Marchi
2021-05-21  7:45     ` Jani Nikula
2021-05-21 16:31       ` Srivatsa, Anusha
2021-05-18 21:34 ` [Intel-gfx] [CI 4/5] drm/i915/dmc: Rename functions names having "csr" Anusha Srivatsa
2021-05-19  5:46   ` Lucas De Marchi
2021-05-18 21:34 ` [Intel-gfx] [CI 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h Anusha Srivatsa
2021-05-19  5:48   ` Lucas De Marchi
2021-05-18 21:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rename all CSR references to DMC (rev5) Patchwork
2021-05-18 21:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-18 22:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-20  0:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2021-05-18 19:53 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
2021-05-18 19:53 ` [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC Anusha Srivatsa

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