* [PATCH v2] target/riscv: Dump CSR mscratch/sscratch/satp
@ 2021-05-19 15:57 ` Changbin Du
0 siblings, 0 replies; 4+ messages in thread
From: Changbin Du @ 2021-05-19 15:57 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann
Cc: Alistair Francis, Bin Meng, qemu-riscv, qemu-devel, Changbin Du
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
v2: Rebase to latest mainline.
---
target/riscv/cpu.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3191fd0082..c4132d9845 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -286,12 +286,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
}
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
#endif
for (i = 0; i < 32; i++) {
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v2] target/riscv: Dump CSR mscratch/sscratch/satp
@ 2021-05-19 15:57 ` Changbin Du
0 siblings, 0 replies; 4+ messages in thread
From: Changbin Du @ 2021-05-19 15:57 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann
Cc: qemu-riscv, qemu-devel, Changbin Du, Alistair Francis, Bin Meng
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
v2: Rebase to latest mainline.
---
target/riscv/cpu.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3191fd0082..c4132d9845 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -286,12 +286,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
}
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
#endif
for (i = 0; i < 32; i++) {
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v2] target/riscv: Dump CSR mscratch/sscratch/satp
2021-05-19 15:57 ` Changbin Du
@ 2021-05-20 7:20 ` Alistair Francis
-1 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2021-05-20 7:20 UTC (permalink / raw)
To: Changbin Du
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Thu, May 20, 2021 at 1:58 AM Changbin Du <changbin.du@gmail.com> wrote:
>
> This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
> the output of CSR mtval/stval.
>
> Signed-off-by: Changbin Du <changbin.du@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> ---
> v2: Rebase to latest mainline.
> ---
> target/riscv/cpu.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3191fd0082..c4132d9845 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -286,12 +286,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> if (riscv_has_ext(env, RVH)) {
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
> }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
> if (riscv_has_ext(env, RVH)) {
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
> }
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
> #endif
>
> for (i = 0; i < 32; i++) {
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] target/riscv: Dump CSR mscratch/sscratch/satp
@ 2021-05-20 7:20 ` Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2021-05-20 7:20 UTC (permalink / raw)
To: Changbin Du
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Thu, May 20, 2021 at 1:58 AM Changbin Du <changbin.du@gmail.com> wrote:
>
> This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
> the output of CSR mtval/stval.
>
> Signed-off-by: Changbin Du <changbin.du@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> ---
> v2: Rebase to latest mainline.
> ---
> target/riscv/cpu.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3191fd0082..c4132d9845 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -286,12 +286,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> if (riscv_has_ext(env, RVH)) {
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
> }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
> if (riscv_has_ext(env, RVH)) {
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
> }
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
> + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
> #endif
>
> for (i = 0; i < 32; i++) {
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-05-20 7:22 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-05-19 15:57 [PATCH v2] target/riscv: Dump CSR mscratch/sscratch/satp Changbin Du
2021-05-19 15:57 ` Changbin Du
2021-05-20 7:20 ` Alistair Francis
2021-05-20 7:20 ` Alistair Francis
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