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From: Darren Powell <darren.powell@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Darren Powell <darren.powell@amd.com>
Subject: [PATCH 4/5] amdgpu/pm: modify smu_get_power_limit to implement Powerplay API
Date: Wed, 19 May 2021 23:57:21 -0400	[thread overview]
Message-ID: <20210520035722.4877-5-darren.powell@amd.com> (raw)
In-Reply-To: <20210520035722.4877-1-darren.powell@amd.com>

 modify smu_get_power_limit to match Powerplay .get_power_limit signature
 add smu_get_power_limit to swsmu_pm_funcs
 simplify calling functions to use Powerplay API rather than direct call

* Test
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
 AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
 HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default

* Test (VANGOGH only)
 echo "=== power2 cap ===" ; cat $HWMON_DIR/power2_cap ;           \
 echo "=== power2 cap max ===" ; cat $HWMON_DIR/power2_cap_max ;   \
 echo "=== power2 cap def ===" ; cat $HWMON_DIR/power2_cap_default

Signed-off-by: Darren Powell <darren.powell@amd.com>
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c        | 48 +++++++++++------------
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  5 +--
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  5 ++-
 3 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 6130318dd993..1e8f9e8c13a2 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2735,16 +2735,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 	}
 
 	limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_MAX : PP_PWR_LIMIT_MAX;
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, limit_level);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, PP_PWR_LIMIT_MAX);
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
+				&limit, limit_level);
+	else
+		r = -ENODATA;
+
+	if (!r)
 		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else {
+	else
 		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2776,16 +2776,16 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
 	}
 
 	limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_CURRENT : PP_PWR_LIMIT_CURRENT;
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, limit_level);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, PP_PWR_LIMIT_CURRENT);
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
+				&limit, limit_level);
+	else
+		r = -ENODATA;
+
+	if (!r)
 		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else {
+	else
 		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2817,16 +2817,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
 	}
 
 	limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_DEFAULT : PP_PWR_LIMIT_DEFAULT;
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, limit_level);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, PP_PWR_LIMIT_DEFAULT);
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
+				&limit, limit_level);
+	else
+		r = -ENODATA;
+
+	if (!r)
 		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else {
+	else
 		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 6bdd112d64cb..3fbc5f7bf048 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1260,9 +1260,8 @@ enum smu_cmn2asic_mapping_type {
 	[profile] = {1, (workload)}
 
 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
-int smu_get_power_limit(struct smu_context *smu,
-			uint32_t *limit,
-			enum pp_power_limit_level limit_level);
+int smu_get_power_limit(void *handle, uint32_t *limit,
+			enum pp_power_limit_level pwr_limit_level);
 
 bool smu_mode1_reset_is_support(struct smu_context *smu);
 bool smu_mode2_reset_is_support(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index e192192e99d0..2815e932580b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2166,10 +2166,10 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
 	return ret;
 }
 
-int smu_get_power_limit(struct smu_context *smu,
-			uint32_t *limit,
+int smu_get_power_limit(void *handle, uint32_t *limit,
 			enum pp_power_limit_level pwr_limit_level)
 {
+	struct smu_context *smu = handle;
 	enum smu_ppt_limit_level limit_level;
 	enum smu_ppt_limit_type limit_type;
 	int ret = -EOPNOTSUPP;
@@ -3002,6 +3002,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
 	.load_firmware           = smu_load_microcode,
 	.set_powergating_by_smu  = smu_dpm_set_power_gate,
 	.set_power_limit         = smu_set_power_limit,
+	.get_power_limit         = smu_get_power_limit,
 	.get_power_profile_mode  = smu_get_power_profile_mode,
 	.set_power_profile_mode  = smu_set_power_profile_mode,
 	.odn_edit_dpm_table      = smu_od_edit_dpm_table,
-- 
2.25.1

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  parent reply	other threads:[~2021-05-20  3:58 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-20  3:57 [PATCH 0/5] Modify smu_get_power_limit to implement Powerplay API Darren Powell
2021-05-20  3:57 ` [PATCH 1/5] amdgpu/pm: reorder definition of swsmu_pm_funcs for readability Darren Powell
2021-05-20  3:57 ` [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level Darren Powell
2021-05-20  8:32   ` Lijo Lazar
2021-05-20  3:57 ` [PATCH 3/5] amdgpu/pm: modify Powerplay API get_power_limit to use pp_power_limit_level Darren Powell
2021-05-20  3:57 ` Darren Powell [this message]
2021-05-20  3:57 ` [PATCH 5/5] amdgpu/pm: add kernel documentation for smu_get_power_limit Darren Powell

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