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* [PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces
@ 2021-05-21 20:05 Andreas Rehn
  2021-05-21 20:05 ` [PATCH v2 4/6] net: sun8i-emac: add v3s variant Andreas Rehn
  2021-05-21 20:05 ` [PATCH v2 5/6] dts: sunxi: v3s: enable emac Andreas Rehn
  0 siblings, 2 replies; 8+ messages in thread
From: Andreas Rehn @ 2021-05-21 20:05 UTC (permalink / raw)
  To: hdegoede, jagan, andre.przywara
  Cc: icenowy, u-boot, linux-sunxi, Andreas Rehn

align CLK_USB_PHY0 with tabs

Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>
---
 drivers/clk/sunxi/clk_v3s.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 55fc597043..bc6b7b4870 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -29,7 +29,7 @@ static struct ccu_clk_gate v3s_gates[] = {
 
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 
-	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 };
 
 static struct ccu_reset v3s_resets[] = {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH v2 4/6] net: sun8i-emac: add v3s variant
  2021-05-21 20:05 [PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces Andreas Rehn
@ 2021-05-21 20:05 ` Andreas Rehn
  2021-05-21 20:05 ` [PATCH v2 5/6] dts: sunxi: v3s: enable emac Andreas Rehn
  1 sibling, 0 replies; 8+ messages in thread
From: Andreas Rehn @ 2021-05-21 20:05 UTC (permalink / raw)
  To: hdegoede, jagan, andre.przywara
  Cc: icenowy, u-boot, linux-sunxi, Andreas Rehn

Add variant V3S_EMAC.
Skip GPIO setup for V3s because it uses internal phy and don't expose pins.

Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>
---
 drivers/net/sun8i_emac.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5a1b38bf80..7541d3cf68 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -145,6 +145,7 @@ enum emac_variant {
 	A64_EMAC,
 	R40_GMAC,
 	H6_EMAC,
+	V3S_EMAC,
 };
 
 struct emac_dma_desc {
@@ -303,7 +304,7 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
 static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
 {
 	if (priv->use_internal_phy) {
-		/* H3 based SoC's that has an Internal 100MBit PHY
+		/* H3 and V3s based SoC's that has an Internal 100MBit PHY
 		 * needs to be configured and powered up before use
 		*/
 		reg &= ~H3_EPHY_DEFAULT_MASK;
@@ -343,7 +344,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
 	reg &= ~(SC_ETCS_MASK | SC_EPIT);
 	if (priv->variant == H3_EMAC ||
 	    priv->variant == A64_EMAC ||
-	    priv->variant == H6_EMAC)
+	    priv->variant == H6_EMAC ||
+	    priv->variant == V3S_EMAC)
 		reg &= ~SC_RMII_EN;
 
 	switch (priv->interface) {
@@ -354,7 +356,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
 	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
-		reg |= SC_EPIT | SC_ETCS_INT_GMII;
+		if (priv->variant != V3S_EMAC)
+			reg |= SC_EPIT | SC_ETCS_INT_GMII;
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		if (priv->variant == H3_EMAC ||
@@ -566,6 +569,9 @@ static int parse_phy_pins(struct udevice *dev)
 		iomux = SUN8I_IOMUX;
 	else if (IS_ENABLED(CONFIG_MACH_SUN50I))
 		iomux = SUN8I_IOMUX;
+	else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S))
+		// V3s does not expose any MAC pins - skip gpio setup.
+		return 0;
 	else
 		BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
 
@@ -956,7 +962,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	if (priv->variant == H3_EMAC) {
+	if (priv->variant == H3_EMAC ||
+	    priv->variant == V3S_EMAC) {
 		ret = sun8i_handle_internal_phy(dev, priv);
 		if (ret)
 			return ret;
@@ -1009,6 +1016,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
 		.data = (uintptr_t)R40_GMAC },
 	{.compatible = "allwinner,sun50i-h6-emac",
 		.data = (uintptr_t)H6_EMAC },
+	{.compatible = "allwinner,sun8i-v3s-emac",
+		.data = (uintptr_t)V3S_EMAC },
 	{ }
 };
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH v2 5/6] dts: sunxi: v3s: enable emac
  2021-05-21 20:05 [PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces Andreas Rehn
  2021-05-21 20:05 ` [PATCH v2 4/6] net: sun8i-emac: add v3s variant Andreas Rehn
@ 2021-05-21 20:05 ` Andreas Rehn
  2021-12-07  6:10   ` Jagan Teki
  1 sibling, 1 reply; 8+ messages in thread
From: Andreas Rehn @ 2021-05-21 20:05 UTC (permalink / raw)
  To: hdegoede, jagan, andre.przywara
  Cc: icenowy, u-boot, linux-sunxi, Andreas Rehn

Enable emac for licheepi-zero-dock as it provides a ethernet port

Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>
---
 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
index db5cd0b857..4d564028f2 100644
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -49,6 +49,10 @@
 	compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
 		     "allwinner,sun8i-v3s";
 
+	aliases {
+		ethernet0 = &emac;
+	};
+
 	leds {
 		/* The LEDs use PG0~2 pins, which conflict with MMC1 */
 		status = "disabled";
@@ -94,3 +98,8 @@
 		voltage = <800000>;
 	};
 };
+
+&emac {
+	allwinner,leds-active-low;
+	status = "okay";
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH v2 5/6] dts: sunxi: v3s: enable emac
  2021-05-21 20:05 ` [PATCH v2 5/6] dts: sunxi: v3s: enable emac Andreas Rehn
@ 2021-12-07  6:10   ` Jagan Teki
  0 siblings, 0 replies; 8+ messages in thread
From: Jagan Teki @ 2021-12-07  6:10 UTC (permalink / raw)
  To: Andreas Rehn; +Cc: hdegoede, andre.przywara, icenowy, u-boot, linux-sunxi

On Sat, May 22, 2021 at 1:36 AM Andreas Rehn <rehn.andreas86@gmail.com> wrote:
>
> Enable emac for licheepi-zero-dock as it provides a ethernet port
>
> Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>
> ---
>  arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
> index db5cd0b857..4d564028f2 100644
> --- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
> +++ b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
> @@ -49,6 +49,10 @@
>         compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
>                      "allwinner,sun8i-v3s";
>
> +       aliases {
> +               ethernet0 = &emac;
> +       };
> +
>         leds {
>                 /* The LEDs use PG0~2 pins, which conflict with MMC1 */
>                 status = "disabled";
> @@ -94,3 +98,8 @@
>                 voltage = <800000>;
>         };
>  };
> +
> +&emac {
> +       allwinner,leds-active-low;
> +       status = "okay";
> +};

We (atleast on sunXi) cannot support intermediate dst changes, better
sync any specific tag or commit from upstream linux.

Jagan.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH v2 4/6] net: sun8i-emac: add v3s variant
  2021-05-22 23:22 ` [PATCH v2 4/6] net: sun8i-emac: add v3s variant Andreas Rehn
  2021-05-25  6:53   ` Ramon Fried
  2021-05-26 23:24   ` Andre Przywara
@ 2021-12-07  6:13   ` Jagan Teki
  2 siblings, 0 replies; 8+ messages in thread
From: Jagan Teki @ 2021-12-07  6:13 UTC (permalink / raw)
  To: Andreas Rehn; +Cc: hdegoede, andre.przywara, icenowy, u-boot, linux-sunxi

On Sun, May 23, 2021 at 4:52 AM Andreas Rehn <rehn.andreas86@gmail.com> wrote:
>
> Add variant V3S_EMAC.
> Handle pinmux compile time error by skipping goio setup, because
> V3s uses internal phy and don't expose pins.
>
> Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>
> ---
> Changes in v2:
>         - skip pinmux and add proper description
>         - Add V3S variant add it to compatible list
>         - Skip (R)GMII flags and handle sun8i_handle_internal_phy
>
>  drivers/net/sun8i_emac.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 5a1b38bf80..ab9f61994c 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -145,6 +145,7 @@ enum emac_variant {
>         A64_EMAC,
>         R40_GMAC,
>         H6_EMAC,
> +       V3S_EMAC,
>  };
>
>  struct emac_dma_desc {
> @@ -303,7 +304,7 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
>  static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
>  {
>         if (priv->use_internal_phy) {
> -               /* H3 based SoC's that has an Internal 100MBit PHY
> +               /* H3 and V3s based SoC's that has an Internal 100MBit PHY
>                  * needs to be configured and powered up before use
>                 */
>                 reg &= ~H3_EPHY_DEFAULT_MASK;
> @@ -354,7 +355,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
>         case PHY_INTERFACE_MODE_RGMII_ID:
>         case PHY_INTERFACE_MODE_RGMII_RXID:
>         case PHY_INTERFACE_MODE_RGMII_TXID:
> -               reg |= SC_EPIT | SC_ETCS_INT_GMII;
> +               if (priv->variant != V3S_EMAC)
> +                       reg |= SC_EPIT | SC_ETCS_INT_GMII;
>                 break;
>         case PHY_INTERFACE_MODE_RMII:
>                 if (priv->variant == H3_EMAC ||
> @@ -566,6 +568,10 @@ static int parse_phy_pins(struct udevice *dev)
>                 iomux = SUN8I_IOMUX;
>         else if (IS_ENABLED(CONFIG_MACH_SUN50I))
>                 iomux = SUN8I_IOMUX;
> +       else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S))
> +               // V3s does not expose any MAC pins,
> +               // but case is required to handle BUILD_BUG_ON_MSG.

Wrong multi-line comment. please fix it?

Jagan.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH v2 4/6] net: sun8i-emac: add v3s variant
  2021-05-22 23:22 ` [PATCH v2 4/6] net: sun8i-emac: add v3s variant Andreas Rehn
  2021-05-25  6:53   ` Ramon Fried
@ 2021-05-26 23:24   ` Andre Przywara
  2021-12-07  6:13   ` Jagan Teki
  2 siblings, 0 replies; 8+ messages in thread
From: Andre Przywara @ 2021-05-26 23:24 UTC (permalink / raw)
  To: Andreas Rehn; +Cc: hdegoede, jagan, icenowy, u-boot, linux-sunxi

On Sun, 23 May 2021 01:22:38 +0200
Andreas Rehn <rehn.andreas86@gmail.com> wrote:

Hi,

> Add variant V3S_EMAC.
> Handle pinmux compile time error by skipping goio setup, because
> V3s uses internal phy and don't expose pins.
> 
> Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> Changes in v2:
> 	- skip pinmux and add proper description
> 	- Add V3S variant add it to compatible list
> 	- Skip (R)GMII flags and handle sun8i_handle_internal_phy
> 
>  drivers/net/sun8i_emac.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 5a1b38bf80..ab9f61994c 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -145,6 +145,7 @@ enum emac_variant {
>  	A64_EMAC,
>  	R40_GMAC,
>  	H6_EMAC,
> +	V3S_EMAC,
>  };
>  
>  struct emac_dma_desc {
> @@ -303,7 +304,7 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
>  static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
>  {
>  	if (priv->use_internal_phy) {
> -		/* H3 based SoC's that has an Internal 100MBit PHY
> +		/* H3 and V3s based SoC's that has an Internal 100MBit PHY
>  		 * needs to be configured and powered up before use
>  		*/
>  		reg &= ~H3_EPHY_DEFAULT_MASK;
> @@ -354,7 +355,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
>  	case PHY_INTERFACE_MODE_RGMII_ID:
>  	case PHY_INTERFACE_MODE_RGMII_RXID:
>  	case PHY_INTERFACE_MODE_RGMII_TXID:
> -		reg |= SC_EPIT | SC_ETCS_INT_GMII;
> +		if (priv->variant != V3S_EMAC)
> +			reg |= SC_EPIT | SC_ETCS_INT_GMII;
>  		break;
>  	case PHY_INTERFACE_MODE_RMII:
>  		if (priv->variant == H3_EMAC ||
> @@ -566,6 +568,10 @@ static int parse_phy_pins(struct udevice *dev)
>  		iomux = SUN8I_IOMUX;
>  	else if (IS_ENABLED(CONFIG_MACH_SUN50I))
>  		iomux = SUN8I_IOMUX;
> +	else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S))
> +		// V3s does not expose any MAC pins,
> +		// but case is required to handle BUILD_BUG_ON_MSG.
> +		return 0;
>  	else
>  		BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
>  
> @@ -956,7 +962,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
>  		return -EINVAL;
>  	}
>  
> -	if (priv->variant == H3_EMAC) {
> +	if (priv->variant == H3_EMAC ||
> +	    priv->variant == V3S_EMAC) {
>  		ret = sun8i_handle_internal_phy(dev, priv);
>  		if (ret)
>  			return ret;
> @@ -1009,6 +1016,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
>  		.data = (uintptr_t)R40_GMAC },
>  	{.compatible = "allwinner,sun50i-h6-emac",
>  		.data = (uintptr_t)H6_EMAC },
> +	{.compatible = "allwinner,sun8i-v3s-emac",
> +		.data = (uintptr_t)V3S_EMAC },
>  	{ }
>  };
>  


^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH v2 4/6] net: sun8i-emac: add v3s variant
  2021-05-22 23:22 ` [PATCH v2 4/6] net: sun8i-emac: add v3s variant Andreas Rehn
@ 2021-05-25  6:53   ` Ramon Fried
  2021-05-26 23:24   ` Andre Przywara
  2021-12-07  6:13   ` Jagan Teki
  2 siblings, 0 replies; 8+ messages in thread
From: Ramon Fried @ 2021-05-25  6:53 UTC (permalink / raw)
  To: Andreas Rehn
  Cc: hdegoede, Jagan Teki, Andre Przywara, icenowy,
	U-Boot Mailing List, linux-sunxi

On Sun, May 23, 2021 at 2:23 AM Andreas Rehn <rehn.andreas86@gmail.com> wrote:
>
> Add variant V3S_EMAC.
> Handle pinmux compile time error by skipping goio setup, because
> V3s uses internal phy and don't expose pins.
>
> Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>
> ---
> Changes in v2:
>         - skip pinmux and add proper description
>         - Add V3S variant add it to compatible list
>         - Skip (R)GMII flags and handle sun8i_handle_internal_phy
>
>  drivers/net/sun8i_emac.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 5a1b38bf80..ab9f61994c 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -145,6 +145,7 @@ enum emac_variant {
>         A64_EMAC,
>         R40_GMAC,
>         H6_EMAC,
> +       V3S_EMAC,
>  };
>
>  struct emac_dma_desc {
> @@ -303,7 +304,7 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
>  static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
>  {
>         if (priv->use_internal_phy) {
> -               /* H3 based SoC's that has an Internal 100MBit PHY
> +               /* H3 and V3s based SoC's that has an Internal 100MBit PHY
>                  * needs to be configured and powered up before use
>                 */
>                 reg &= ~H3_EPHY_DEFAULT_MASK;
> @@ -354,7 +355,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
>         case PHY_INTERFACE_MODE_RGMII_ID:
>         case PHY_INTERFACE_MODE_RGMII_RXID:
>         case PHY_INTERFACE_MODE_RGMII_TXID:
> -               reg |= SC_EPIT | SC_ETCS_INT_GMII;
> +               if (priv->variant != V3S_EMAC)
> +                       reg |= SC_EPIT | SC_ETCS_INT_GMII;
>                 break;
>         case PHY_INTERFACE_MODE_RMII:
>                 if (priv->variant == H3_EMAC ||
> @@ -566,6 +568,10 @@ static int parse_phy_pins(struct udevice *dev)
>                 iomux = SUN8I_IOMUX;
>         else if (IS_ENABLED(CONFIG_MACH_SUN50I))
>                 iomux = SUN8I_IOMUX;
> +       else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S))
> +               // V3s does not expose any MAC pins,
> +               // but case is required to handle BUILD_BUG_ON_MSG.
> +               return 0;
>         else
>                 BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
>
> @@ -956,7 +962,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
>                 return -EINVAL;
>         }
>
> -       if (priv->variant == H3_EMAC) {
> +       if (priv->variant == H3_EMAC ||
> +           priv->variant == V3S_EMAC) {
>                 ret = sun8i_handle_internal_phy(dev, priv);
>                 if (ret)
>                         return ret;
> @@ -1009,6 +1016,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
>                 .data = (uintptr_t)R40_GMAC },
>         {.compatible = "allwinner,sun50i-h6-emac",
>                 .data = (uintptr_t)H6_EMAC },
> +       {.compatible = "allwinner,sun8i-v3s-emac",
> +               .data = (uintptr_t)V3S_EMAC },
>         { }
>  };
>
> --
> 2.25.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com >

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH v2 4/6] net: sun8i-emac: add v3s variant
  2021-05-19 19:42 [PATCH 4/6] net: sun8i-emac: add v3s pinmux setting Andreas Rehn
@ 2021-05-22 23:22 ` Andreas Rehn
  2021-05-25  6:53   ` Ramon Fried
                     ` (2 more replies)
  0 siblings, 3 replies; 8+ messages in thread
From: Andreas Rehn @ 2021-05-22 23:22 UTC (permalink / raw)
  To: hdegoede, jagan, andre.przywara
  Cc: icenowy, u-boot, linux-sunxi, Andreas Rehn

Add variant V3S_EMAC.
Handle pinmux compile time error by skipping goio setup, because
V3s uses internal phy and don't expose pins.

Signed-off-by: Andreas Rehn <rehn.andreas86@gmail.com>
---
Changes in v2:
	- skip pinmux and add proper description
	- Add V3S variant add it to compatible list
	- Skip (R)GMII flags and handle sun8i_handle_internal_phy

 drivers/net/sun8i_emac.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5a1b38bf80..ab9f61994c 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -145,6 +145,7 @@ enum emac_variant {
 	A64_EMAC,
 	R40_GMAC,
 	H6_EMAC,
+	V3S_EMAC,
 };
 
 struct emac_dma_desc {
@@ -303,7 +304,7 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
 static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
 {
 	if (priv->use_internal_phy) {
-		/* H3 based SoC's that has an Internal 100MBit PHY
+		/* H3 and V3s based SoC's that has an Internal 100MBit PHY
 		 * needs to be configured and powered up before use
 		*/
 		reg &= ~H3_EPHY_DEFAULT_MASK;
@@ -354,7 +355,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
 	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
-		reg |= SC_EPIT | SC_ETCS_INT_GMII;
+		if (priv->variant != V3S_EMAC)
+			reg |= SC_EPIT | SC_ETCS_INT_GMII;
 		break;
 	case PHY_INTERFACE_MODE_RMII:
 		if (priv->variant == H3_EMAC ||
@@ -566,6 +568,10 @@ static int parse_phy_pins(struct udevice *dev)
 		iomux = SUN8I_IOMUX;
 	else if (IS_ENABLED(CONFIG_MACH_SUN50I))
 		iomux = SUN8I_IOMUX;
+	else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S))
+		// V3s does not expose any MAC pins,
+		// but case is required to handle BUILD_BUG_ON_MSG.
+		return 0;
 	else
 		BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
 
@@ -956,7 +962,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	if (priv->variant == H3_EMAC) {
+	if (priv->variant == H3_EMAC ||
+	    priv->variant == V3S_EMAC) {
 		ret = sun8i_handle_internal_phy(dev, priv);
 		if (ret)
 			return ret;
@@ -1009,6 +1016,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
 		.data = (uintptr_t)R40_GMAC },
 	{.compatible = "allwinner,sun50i-h6-emac",
 		.data = (uintptr_t)H6_EMAC },
+	{.compatible = "allwinner,sun8i-v3s-emac",
+		.data = (uintptr_t)V3S_EMAC },
 	{ }
 };
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-12-07  6:14 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-21 20:05 [PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces Andreas Rehn
2021-05-21 20:05 ` [PATCH v2 4/6] net: sun8i-emac: add v3s variant Andreas Rehn
2021-05-21 20:05 ` [PATCH v2 5/6] dts: sunxi: v3s: enable emac Andreas Rehn
2021-12-07  6:10   ` Jagan Teki
  -- strict thread matches above, loose matches on Subject: below --
2021-05-19 19:42 [PATCH 4/6] net: sun8i-emac: add v3s pinmux setting Andreas Rehn
2021-05-22 23:22 ` [PATCH v2 4/6] net: sun8i-emac: add v3s variant Andreas Rehn
2021-05-25  6:53   ` Ramon Fried
2021-05-26 23:24   ` Andre Przywara
2021-12-07  6:13   ` Jagan Teki

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