* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 12:38 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:38 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: iommu, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Benjamin Gaignard
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
- Rebased on v5.13-rc3
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 85 ++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..16dd2bf4a859 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -485,6 +544,21 @@ static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
return dt_dma;
}
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
+{
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
+}
+
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
{
void __iomem *base = iommu->bases[index];
@@ -1316,11 +1390,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 12:38 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:38 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: iommu, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Benjamin Gaignard
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
- Rebased on v5.13-rc3
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 85 ++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..16dd2bf4a859 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -485,6 +544,21 @@ static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
return dt_dma;
}
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
+{
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
+}
+
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
{
void __iomem *base = iommu->bases[index];
@@ -1316,11 +1390,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 12:38 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:38 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: devicetree, Benjamin Gaignard, linux-kernel, linux-rockchip,
iommu, kernel, linux-arm-kernel
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
- Rebased on v5.13-rc3
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 85 ++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..16dd2bf4a859 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -485,6 +544,21 @@ static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
return dt_dma;
}
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
+{
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
+}
+
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
{
void __iomem *base = iommu->bases[index];
@@ -1316,11 +1390,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 12:38 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:38 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: iommu, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Benjamin Gaignard
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
- Rebased on v5.13-rc3
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 85 ++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..16dd2bf4a859 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -485,6 +544,21 @@ static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
return dt_dma;
}
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
+{
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
+}
+
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
{
void __iomem *base = iommu->bases[index];
@@ -1316,11 +1390,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
2021-05-25 12:15 ` Benjamin Gaignard
` (2 preceding siblings ...)
(?)
@ 2021-05-25 21:21 ` kernel test robot
-1 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 21:21 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: kbuild-all, clang-built-linux, iommu, devicetree,
linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 3006 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: arm-randconfig-r025-20210525 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 99155e913e9bad5f7f8a247f8bb3a3ff3da74af1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: use of undeclared identifier 'rk_dma_addr_dte'; did you mean 'rk_dma_addr_dte_v2'?
.dma_addr_dte = &rk_dma_addr_dte,
^~~~~~~~~~~~~~~
rk_dma_addr_dte_v2
drivers/iommu/rockchip-iommu.c:551:19: note: 'rk_dma_addr_dte_v2' declared here
static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
^
1 error generated.
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 37646 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 21:21 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 21:21 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: kbuild-all, clang-built-linux, iommu, devicetree,
linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 3006 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: arm-randconfig-r025-20210525 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 99155e913e9bad5f7f8a247f8bb3a3ff3da74af1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: use of undeclared identifier 'rk_dma_addr_dte'; did you mean 'rk_dma_addr_dte_v2'?
.dma_addr_dte = &rk_dma_addr_dte,
^~~~~~~~~~~~~~~
rk_dma_addr_dte_v2
drivers/iommu/rockchip-iommu.c:551:19: note: 'rk_dma_addr_dte_v2' declared here
static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
^
1 error generated.
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 37646 bytes --]
[-- Attachment #3: Type: text/plain, Size: 170 bytes --]
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 21:21 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 21:21 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: devicetree, kbuild-all, clang-built-linux, linux-rockchip, iommu,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 3006 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: arm-randconfig-r025-20210525 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 99155e913e9bad5f7f8a247f8bb3a3ff3da74af1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: use of undeclared identifier 'rk_dma_addr_dte'; did you mean 'rk_dma_addr_dte_v2'?
.dma_addr_dte = &rk_dma_addr_dte,
^~~~~~~~~~~~~~~
rk_dma_addr_dte_v2
drivers/iommu/rockchip-iommu.c:551:19: note: 'rk_dma_addr_dte_v2' declared here
static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
^
1 error generated.
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 37646 bytes --]
[-- Attachment #3: Type: text/plain, Size: 156 bytes --]
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 21:21 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 21:21 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: kbuild-all, clang-built-linux, iommu, devicetree,
linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 3006 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: arm-randconfig-r025-20210525 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 99155e913e9bad5f7f8a247f8bb3a3ff3da74af1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: use of undeclared identifier 'rk_dma_addr_dte'; did you mean 'rk_dma_addr_dte_v2'?
.dma_addr_dte = &rk_dma_addr_dte,
^~~~~~~~~~~~~~~
rk_dma_addr_dte_v2
drivers/iommu/rockchip-iommu.c:551:19: note: 'rk_dma_addr_dte_v2' declared here
static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
^
1 error generated.
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 37646 bytes --]
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 21:21 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 21:21 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3065 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: arm-randconfig-r025-20210525 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 99155e913e9bad5f7f8a247f8bb3a3ff3da74af1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: use of undeclared identifier 'rk_dma_addr_dte'; did you mean 'rk_dma_addr_dte_v2'?
.dma_addr_dte = &rk_dma_addr_dte,
^~~~~~~~~~~~~~~
rk_dma_addr_dte_v2
drivers/iommu/rockchip-iommu.c:551:19: note: 'rk_dma_addr_dte_v2' declared here
static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
^
1 error generated.
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 37646 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
2021-05-25 12:15 ` Benjamin Gaignard
` (2 preceding siblings ...)
(?)
@ 2021-05-25 16:51 ` kernel test robot
-1 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 16:51 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: kbuild-all, iommu, devicetree, linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 2776 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: powerpc-randconfig-s031-20210525 (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: 'rk_dma_addr_dte' undeclared here (not in a function); did you mean 'rk_dma_addr_dte_v2'?
1384 | .dma_addr_dte = &rk_dma_addr_dte,
| ^~~~~~~~~~~~~~~
| rk_dma_addr_dte_v2
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41569 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 16:51 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 16:51 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: kbuild-all, iommu, devicetree, linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 2776 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: powerpc-randconfig-s031-20210525 (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: 'rk_dma_addr_dte' undeclared here (not in a function); did you mean 'rk_dma_addr_dte_v2'?
1384 | .dma_addr_dte = &rk_dma_addr_dte,
| ^~~~~~~~~~~~~~~
| rk_dma_addr_dte_v2
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41569 bytes --]
[-- Attachment #3: Type: text/plain, Size: 170 bytes --]
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 16:51 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 16:51 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: devicetree, iommu, kbuild-all, linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 2776 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: powerpc-randconfig-s031-20210525 (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: 'rk_dma_addr_dte' undeclared here (not in a function); did you mean 'rk_dma_addr_dte_v2'?
1384 | .dma_addr_dte = &rk_dma_addr_dte,
| ^~~~~~~~~~~~~~~
| rk_dma_addr_dte_v2
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41569 bytes --]
[-- Attachment #3: Type: text/plain, Size: 156 bytes --]
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 16:51 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 16:51 UTC (permalink / raw)
To: Benjamin Gaignard, joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: kbuild-all, iommu, devicetree, linux-arm-kernel, linux-rockchip
[-- Attachment #1: Type: text/plain, Size: 2776 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: powerpc-randconfig-s031-20210525 (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: 'rk_dma_addr_dte' undeclared here (not in a function); did you mean 'rk_dma_addr_dte_v2'?
1384 | .dma_addr_dte = &rk_dma_addr_dte,
| ^~~~~~~~~~~~~~~
| rk_dma_addr_dte_v2
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41569 bytes --]
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 16:51 ` kernel test robot
0 siblings, 0 replies; 18+ messages in thread
From: kernel test robot @ 2021-05-25 16:51 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2831 bytes --]
Hi Benjamin,
I love your patch! Yet something to improve:
[auto build test ERROR on iommu/next]
[also build test ERROR on rockchip/for-next robh/for-next v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: powerpc-randconfig-s031-20210525 (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-341-g8af24329-dirty
# https://github.com/0day-ci/linux/commit/bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Benjamin-Gaignard/Add-IOMMU-driver-for-rk356x/20210525-201749
git checkout bd6c989c628be7c8ac1f8aeb9f301bd3a6e0a078
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/iommu/rockchip-iommu.c:1384:19: error: 'rk_dma_addr_dte' undeclared here (not in a function); did you mean 'rk_dma_addr_dte_v2'?
1384 | .dma_addr_dte = &rk_dma_addr_dte,
| ^~~~~~~~~~~~~~~
| rk_dma_addr_dte_v2
vim +1384 drivers/iommu/rockchip-iommu.c
0f181d3cf7d984b Jeffy Chen 2018-03-23 1378
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1379 static struct rk_iommu_ops iommu_data_ops_v1 = {
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1380 .pt_address = &rk_dte_pt_address,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1381 .mk_dtentries = &rk_mk_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1382 .mk_ptentries = &rk_mk_pte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1383 .dte_addr_phys = &rk_dte_addr_phys,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 @1384 .dma_addr_dte = &rk_dma_addr_dte,
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1385 .dma_bit_mask = DMA_BIT_MASK(32),
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1386 };
ce0eeece4c9ef42 Benjamin Gaignard 2021-05-25 1387
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 41569 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
2021-05-25 12:15 [PATCH v7 0/4] Add IOMMU driver for rk356x Benjamin Gaignard
2021-05-25 12:15 ` Benjamin Gaignard
(?)
@ 2021-05-25 12:15 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:15 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: iommu, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Benjamin Gaignard
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 84 +++++++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..edd05e488aa7 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -480,9 +539,19 @@ static inline phys_addr_t rk_dte_addr_phys(u32 addr)
return (phys_addr_t)addr;
}
-static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
{
- return dt_dma;
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
}
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
@@ -1316,11 +1385,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 12:15 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:15 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: iommu, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Benjamin Gaignard
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 84 +++++++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..edd05e488aa7 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -480,9 +539,19 @@ static inline phys_addr_t rk_dte_addr_phys(u32 addr)
return (phys_addr_t)addr;
}
-static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
{
- return dt_dma;
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
}
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
@@ -1316,11 +1385,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 12:15 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:15 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: devicetree, Benjamin Gaignard, linux-kernel, linux-rockchip,
iommu, kernel, linux-arm-kernel
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 84 +++++++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..edd05e488aa7 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -480,9 +539,19 @@ static inline phys_addr_t rk_dte_addr_phys(u32 addr)
return (phys_addr_t)addr;
}
-static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
{
- return dt_dma;
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
}
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
@@ -1316,11 +1385,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2
@ 2021-05-25 12:15 ` Benjamin Gaignard
0 siblings, 0 replies; 18+ messages in thread
From: Benjamin Gaignard @ 2021-05-25 12:15 UTC (permalink / raw)
To: joro, will, robh+dt, heiko, xxm, robin.murphy
Cc: iommu, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, kernel, Benjamin Gaignard
This second version of the hardware block has a different bits
mapping for page table entries.
Add the ops matching to this new mapping.
Define a new compatible to distinguish it from the first version.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
version 7:
- Set dma_bit_mask field.
- Add rk_dma_addr_dte_v2 function
version 5:
- Use internal ops to support v2 hardware block
- Use GENMASK macro.
- Keep rk_dte_pt_address() and rk_dte_pt_address_v2() separated
because I believe that is more readable like this.
- Do not duplicate code.
drivers/iommu/rockchip-iommu.c | 84 +++++++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index bd2cf7f08c71..edd05e488aa7 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -189,6 +189,33 @@ static inline phys_addr_t rk_dte_pt_address(u32 dte)
return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
}
+/*
+ * In v2:
+ * 31:12 - PT address bit 31:0
+ * 11: 8 - PT address bit 35:32
+ * 7: 4 - PT address bit 39:36
+ * 3: 1 - Reserved
+ * 0 - 1 if PT @ PT address is valid
+ */
+#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
+#define DTE_HI_MASK1 GENMASK(11, 8)
+#define DTE_HI_MASK2 GENMASK(7, 4)
+#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
+#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
+#define PAGE_DESC_HI_MASK1 GENMASK_ULL(39, 36)
+#define PAGE_DESC_HI_MASK2 GENMASK_ULL(35, 32)
+
+static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
+{
+ u64 dte_v2 = dte;
+
+ dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
+ ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
+ (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
+
+ return (phys_addr_t)dte_v2;
+}
+
static inline bool rk_dte_is_pt_valid(u32 dte)
{
return dte & RK_DTE_PT_VALID;
@@ -199,6 +226,15 @@ static inline u32 rk_mk_dte(dma_addr_t pt_dma)
return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
}
+static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
+{
+ pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
+ (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
+
+ return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
+}
+
/*
* Each PTE has a Page address, some flags and a valid bit:
* +---------------------+---+-------+-+
@@ -240,6 +276,29 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
return page | flags | RK_PTE_PAGE_VALID;
}
+/*
+ * In v2:
+ * 31:12 - Page address bit 31:0
+ * 11:9 - Page address bit 34:32
+ * 8:4 - Page address bit 39:35
+ * 3 - Security
+ * 2 - Readable
+ * 1 - Writable
+ * 0 - 1 if Page @ Page address is valid
+ */
+#define RK_PTE_PAGE_READABLE_V2 BIT(2)
+#define RK_PTE_PAGE_WRITABLE_V2 BIT(1)
+
+static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
+{
+ u32 flags = 0;
+
+ flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
+ flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
+
+ return rk_mk_dte_v2(page) | flags;
+}
+
static u32 rk_mk_pte_invalid(u32 pte)
{
return pte & ~RK_PTE_PAGE_VALID;
@@ -480,9 +539,19 @@ static inline phys_addr_t rk_dte_addr_phys(u32 addr)
return (phys_addr_t)addr;
}
-static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
+#define DT_HI_MASK GENMASK_ULL(39, 32)
+#define DT_SHIFT 28
+
+static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
+{
+ return (phys_addr_t)(addr & RK_DTE_PT_ADDRESS_MASK) |
+ ((addr & DT_HI_MASK) << DT_SHIFT);
+}
+
+static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
{
- return dt_dma;
+ return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
+ ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
}
static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
@@ -1316,11 +1385,22 @@ static struct rk_iommu_ops iommu_data_ops_v1 = {
.dma_bit_mask = DMA_BIT_MASK(32),
};
+static struct rk_iommu_ops iommu_data_ops_v2 = {
+ .pt_address = &rk_dte_pt_address_v2,
+ .mk_dtentries = &rk_mk_dte_v2,
+ .mk_ptentries = &rk_mk_pte_v2,
+ .dte_addr_phys = &rk_dte_addr_phys_v2,
+ .dma_addr_dte = &rk_dma_addr_dte_v2,
+ .dma_bit_mask = DMA_BIT_MASK(40),
+};
static const struct of_device_id rk_iommu_dt_ids[] = {
{ .compatible = "rockchip,iommu",
.data = &iommu_data_ops_v1,
},
+ { .compatible = "rockchip,rk3568-iommu",
+ .data = &iommu_data_ops_v2,
+ },
{ /* sentinel */ }
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
end of thread, other threads:[~2021-05-25 21:23 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-25 12:38 [PATCH v7 4/4] iommu: rockchip: Add support for iommu v2 Benjamin Gaignard
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-- strict thread matches above, loose matches on Subject: below --
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