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From: Keith Busch <kbusch@kernel.org>
To: "Limonciello, Mario" <Mario.Limonciello@amd.com>
Cc: Christoph Hellwig <hch@lst.de>,
	Hans de Goede <hdegoede@redhat.com>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Liang, Prike" <Prike.Liang@amd.com>,
	"axboe@fb.com" <axboe@fb.com>,
	"sagi@grimberg.me" <sagi@grimberg.me>,
	"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
	"S-k, Shyam-sundar" <Shyam-sundar.S-k@amd.com>
Subject: Re: [PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3 for s2idle
Date: Tue, 25 May 2021 10:45:05 -0700	[thread overview]
Message-ID: <20210525174505.GA3704559@dhcp-10-100-145-180.wdc.com> (raw)
In-Reply-To: <BYAPR12MB26939EE6323113FA9C43E875E2259@BYAPR12MB2693.namprd12.prod.outlook.com>

On Tue, May 25, 2021 at 03:18:46PM +0000, Limonciello, Mario wrote:
> > or by splitting the suspend method in different ones
> > for different use cases.  Platform-specific code (right now for Intel
> > and AMD) can then make sure drivers do get the right requests instead of
> > hardcoding platform information in every driver that wants to be able
> > to implement intelligent suspend behavior.
> 
> This seems like a gross assumption though that evicting the quirks into a
> central place that every driver needs to behave the same.  AMD's case is
> specific to NVME, particularly because APST will be used otherwise.

I don't think you mean APST. That feature enables controller power state
autonomy, and we do not messed with that on the driver's suspend path.

We do use the explicit nvme specific host managed power state feature,
though.

But I also don't see why this is specific to nvme. Are you saying that
if a some other protocol device was in the same slot, it would be okay
to use its protocol specific power settings? That doesn't sound right.

_______________________________________________
Linux-nvme mailing list
Linux-nvme@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-nvme

  reply	other threads:[~2021-05-25 17:57 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-25  2:48 [PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3 for s2idle Prike Liang
2021-05-25  6:21 ` Christoph Hellwig
2021-05-25 12:11   ` Liang, Prike
2021-05-25 12:15     ` Christoph Hellwig
2021-05-25 13:39   ` Deucher, Alexander
2021-05-25 13:54     ` Hans de Goede
2021-05-25 14:06       ` Limonciello, Mario
2021-05-25 14:16         ` Christoph Hellwig
2021-05-25 15:18           ` Limonciello, Mario
2021-05-25 17:45             ` Keith Busch [this message]
2021-05-25 18:27               ` Limonciello, Mario
2021-05-25 19:55                 ` Keith Busch
2021-05-25 20:02                 ` Chaitanya Kulkarni
2021-05-26  8:52             ` Hans de Goede
2021-05-26 13:02               ` Christoph Hellwig
2021-05-26 14:45               ` Keith Busch
2021-05-26 14:55                 ` Rafael J. Wysocki
2021-05-26 17:02                   ` Limonciello, Mario
2021-05-26 17:27                     ` Rafael J. Wysocki
2021-05-26 17:32                       ` Limonciello, Mario
2021-05-26 17:42                       ` Limonciello, Mario
2021-05-25 19:59         ` Keith Busch
2021-05-25 20:09           ` Limonciello, Mario
2021-05-25 20:24             ` Keith Busch
2021-05-25 21:51               ` Limonciello, Mario
2021-05-25 14:09       ` Deucher, Alexander

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